CN104881508A - Table look-up method-based modeling method and system of semiconductor device - Google Patents
Table look-up method-based modeling method and system of semiconductor device Download PDFInfo
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- CN104881508A CN104881508A CN201410708276.5A CN201410708276A CN104881508A CN 104881508 A CN104881508 A CN 104881508A CN 201410708276 A CN201410708276 A CN 201410708276A CN 104881508 A CN104881508 A CN 104881508A
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Abstract
The invention discloses a table look-up method-based modeling method and system of a semiconductor device. The method includes: according to intrinsic data of at least one semiconductor unit-cell device, acquiring intrinsic simulation data of the semiconductor device composed of at least one semiconductor unit-cell device; acquiring parasitic simulation data of the semiconductor device; according to the intrinsic simulation data and parasitic simulation data of the semiconductor device, establishing a table look-up model of the semiconductor device. The method and the system have the advantages that data quantity of simulation calculation is reduced, simulation calculation time is shortened and device layout in simulation is easier.
Description
Technical field
The present invention relates to organs weight field, particularly relate to a kind of modeling method and system of the semiconductor devices based on look-up table.
Background technology
Semiconductor devices modeling is the bridge of Joining Technology and circuit design, it both can produced problem in feedback process, instruct the design of device, may be used for again the design of circuit, therefore the modeling of semiconductor device model is a link indispensable in semiconductor device design.
The research of semiconductor devices modeling has the history of decades, and the main modeling pattern existed comprises physical model modeling method, look-up table model modelling approach and equivalent-circuit model method at present.Physical model modeling method uses device simulation software modeling usually.Look-up table model modelling approach is the method setting up accurate device model according to the test data of the semiconductor devices under different condition.Equivalent-circuit model method rule of thumb semiconductor devices is used circuit component equivalence, and the numerical value being extracted circuit component by test data carries out modeling.
Nowadays, in order to meet higher electric current and more high-power demand, the size of semiconductor devices is constantly increasing.At present, due to the complete test data of large scale semiconductor devices directly can not be obtained, so the modeling method of traditional large scale semiconductor devices first sets up the model of small size semiconductor unit cell device, more multiple small size semiconductor unit cell device is used to replace corresponding large scale semiconductor devices in simulations.Each small size semiconductor unit cell device correspondence one independently device model in this method, needs during emulation to distribute independently data storage cell for each small size unit cell device.This traditional method considerably increases the quantity of semiconductor devices in emulation, and this can cause expending more simulation time, processes more emulated data, and increases the complexity of device layout in emulation.
Summary of the invention
The invention provides a kind of modeling method and system of the semiconductor devices based on look-up table, during to solve large scale semiconductor devices modeling in prior art, the problem that simulation time is too much, emulated data is many and layout complexity is high.
First aspect, the invention provides a kind of modeling method of the semiconductor devices based on look-up table, comprising:
According to the intrinsic data of at least one semiconductor unit cell device, obtain the intrinsic emulated data of the semiconductor devices be made up of semiconductor unit cell device described at least one;
Obtain the parasitic emulated data of described semiconductor devices;
According to intrinsic emulated data and the parasitic emulated data of described semiconductor devices, set up the model of tabling look-up of described semiconductor devices.
Further, described semiconductor unit cell device is the bipolar junction transistor of enhancement mode, field effect transistor or bipolar transistor; Or
Described semiconductor unit cell device is the bipolar junction transistor of depletion type, field effect transistor or bipolar transistor.
Further, the described intrinsic data according at least one semiconductor unit cell device, obtains the intrinsic emulated data of the semiconductor devices be made up of semiconductor unit cell device described at least one, comprising:
Described semiconductor unit cell device is carried out to the test under different test condition, to obtain the test data under corresponding test condition;
Remove the parasitic parameter in described test data, obtain the intrinsic data of described semiconductor unit cell device;
According to the intrinsic data of described semiconductor unit cell device, set up the model of tabling look-up of the intrinsic part of described semiconductor unit cell device;
Combine semiconductor unit cell device described at least one, emulate the intrinsic emulated data getting the semiconductor devices be made up of semiconductor unit cell device described at least one.
Further, according to the intrinsic data of described semiconductor unit cell device, the concrete implementation of model of tabling look-up setting up the intrinsic part of described semiconductor unit cell device is:
According to the intrinsic data of described semiconductor unit cell device in varying environment temperature, set up the model of tabling look-up of described semiconductor unit cell device different temperatures.
Further, before the described parasitic emulated data obtaining described semiconductor devices, also comprise:
According to processing technology and the design layout of described semiconductor devices, emulate the parasitic structure of described semiconductor devices.
Further, set up the model of tabling look-up of described semiconductor devices, also comprise: according to the Temperature Distribution effect of semiconductor devices, obtain the temperature funtion of the semiconductor unit cell device in described semiconductor devices, set up the model of tabling look-up that described semiconductor devices comprises temperature model.
Further, the grid width of described semiconductor devices is the integral multiple of the grid width of described semiconductor unit cell device.
Second aspect, the invention provides a kind of modeling of the semiconductor devices based on look-up table, comprising:
Intrinsic emulated data acquisition module, for the intrinsic data according at least one semiconductor unit cell device, obtains the intrinsic emulated data of the semiconductor devices be made up of semiconductor unit cell device described at least one;
Parasitic emulated data acquisition module, for obtaining the parasitic emulated data of described semiconductor devices;
Model building module, for according to the intrinsic emulated data of described semiconductor devices and parasitic emulated data, sets up the model of tabling look-up of described semiconductor devices.
Further, described semiconductor unit cell device is the bipolar junction transistor of enhancement mode, field effect transistor or bipolar transistor; Or
Described semiconductor unit cell device is the bipolar junction transistor of depletion type, field effect transistor or bipolar transistor.
Further, described intrinsic emulated data acquisition module comprises:
Semiconductor unit cell device test data acquiring unit, for carrying out the test under different test condition to described semiconductor unit cell device, to obtain the test data under corresponding test condition;
Semiconductor unit cell device intrinsic data acquiring unit, for removing the parasitic parameter in described test data, obtains the intrinsic data of described semiconductor unit cell device;
Semiconductor unit cell device model sets up unit, for the intrinsic data according to described semiconductor unit cell device, sets up the model of tabling look-up of the intrinsic part of described semiconductor unit cell device;
Semiconductor devices intrinsic emulated data acquiring unit, for combining semiconductor unit cell device described at least one, emulates the intrinsic emulated data getting the semiconductor devices be made up of semiconductor unit cell device described at least one.
Further, described semiconductor unit cell device model is set up the concrete implementation of unit and is:
According to the intrinsic data of described semiconductor unit cell device in varying environment temperature, set up the model of tabling look-up of described semiconductor unit cell device different temperatures.
Further, before described parasitic emulated data acquisition module, described modeling also comprises:
Parasitic structure emulation module, for according to the processing technology of described semiconductor devices and design layout, emulates the parasitic structure of described semiconductor devices.
Further, described model building module also comprises: according to the Temperature Distribution effect of semiconductor devices, obtains the temperature funtion of the semiconductor unit cell device in described semiconductor devices, sets up the model of tabling look-up that described semiconductor devices comprises temperature model.
Further, the grid width of described semiconductor devices is the integral multiple of the grid width of described semiconductor unit cell device.
The modeling method of a kind of semiconductor devices based on look-up table provided by the invention and system, the intrinsic emulated data of the semiconductor devices be made up of at least one semiconductor unit cell device obtained by the intrinsic data of semiconductor unit cell device, and obtain the parasitic emulated data of semiconductor devices, set up the model of tabling look-up of this semiconductor devices thus, technical scheme of the present invention compared with prior art, relatively reduce the simulation calculating data volume in semiconductor devices modeling process, shorten the simulation calculating time in semiconductor devices modeling process, and the device layout's complexity in the emulation reducing in semiconductor devices modeling process.
Accompanying drawing explanation
In order to the technical scheme of exemplary embodiment of the present is clearly described, one is done to the accompanying drawing used required for describing in embodiment below and simply introduce.Obviously, the accompanying drawing introduced is the accompanying drawing of a part of embodiment that the present invention will describe, instead of whole accompanying drawings, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the process flow diagram of the modeling method of the semiconductor devices based on look-up table that the embodiment of the present invention one provides;
Fig. 2 is that in the modeling method of the semiconductor devices based on look-up table that the embodiment of the present invention one provides, grid width is the schematic symbol diagram of the model of tabling look-up of the intrinsic part of the semiconductor unit cell device of 1 millimeter;
Fig. 3 is that in the modeling method of the semiconductor devices based on look-up table that the embodiment of the present invention one provides, grid width is the schematic diagram of the array mode of the intrinsic part of the semiconductor devices of 10 millimeters;
Fig. 4 is that in the modeling method of the semiconductor devices based on look-up table that the embodiment of the present invention one provides, grid width is the schematic symbol diagram of the model of tabling look-up of the semiconductor devices of 10 millimeters;
Fig. 5 is the structural drawing of the modeling of the semiconductor devices based on look-up table that the embodiment of the present invention two provides.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below with reference to the accompanying drawing in the embodiment of the present invention, by embodiment, technical scheme of the present invention is intactly described.Obviously; described embodiment is a part of embodiment of the present invention, instead of whole embodiments, based on embodiments of the invention; the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all falls within protection scope of the present invention.
Embodiment one:
Fig. 1 gives the process flow diagram of the modeling method of the semiconductor devices based on look-up table that the embodiment of the present invention one provides, the technical scheme of the present embodiment is applicable to the semiconductor devices modeling with large-size, wherein, the semiconductor devices of large-size can be defined as the semiconductor devices of multiple semiconductor unit cell device composition.This modeling method can be performed by the modeling of the semiconductor devices based on look-up table, and this modeling can adopt the mode of software and/or hardware to realize, and configuration performs in a computer.This modeling method comprises the following steps:
Step S110, intrinsic data according at least one semiconductor unit cell device, obtain the intrinsic emulated data of the semiconductor devices be made up of at least one semiconductor unit cell device.
In this step, semiconductor unit cell device is the elementary cell of composition semiconductor devices, by at least one semiconductor unit cell device is connected by different connection modes, namely the large-size device of composition is semiconductor devices, and that is semiconductor devices can be formed by connecting according to certain connected mode by multiple identical semiconductor unit cell device.
At this, the grid width of semiconductor unit cell device is not more than 1 millimeter usually, and semiconductor devices is normally formed by least one semiconductor unit cell combination of devices, and therefore, the grid width of semiconductor devices is the integral multiple of the grid width of semiconductor unit cell device.
In this step, preferably, described semiconductor unit cell device can be the bipolar junction transistor of enhancement mode, field effect transistor or bipolar transistor, also can be the bipolar junction transistor of depletion type, field effect transistor or bipolar transistor.Wherein, field effect transistor can be mos field effect transistor, metal dielectric layer semiconductor field effect transistor, dual heterogeneity node field effect transistor, junction field effect transistor, metal-semiconductor field effect transistor or metal dielectric layer heterogeneous semiconductor junction field effect transistor, and bipolar junction transistor can be insulated gate bipolar transistor.
For step S110, according to the intrinsic data of at least one semiconductor unit cell device, obtain the operation of the intrinsic emulated data of the semiconductor devices be made up of semiconductor unit cell device described at least one, below provide a kind of preferred implementation: the intrinsic data of based semiconductor unit cell device obtains the intrinsic emulated data of semiconductor devices.The preferred implementation of this step S110 specifically can comprise the following steps:
Step S111, the test carried out semiconductor unit cell device under different test condition, to obtain the test data under corresponding test condition.
In this step, different test conditions can be test environment or other objective condition of semiconductor unit cell device, when test refers to that semiconductor unit cell device is in wherein under any one test condition, the data type used is needed to decide the method for testing of semiconductor unit cell device according in semiconductor unit cell device simulation process.
At this, preferably, different test conditions can be semiconductor unit cell device current residing temperature conditions, illumination condition or other environmental baseline, data type can refer to output data, transferring data, scattering parameter or load balance factor data etc. the performance data of semiconductor unit cell device, therefore according to the data type of semiconductor unit cell device, its method of testing can be the output characteristics of semiconductor unit cell device is tested, transfer characteristics test, S (scattering) parameter testing or Loadpull (load balance factor) test etc.
At this, semiconductor unit cell device can be placed at least one environmental baseline, and wherein in any one environmental baseline, one or more data of semiconductor unit cell device are tested according at least one method of testing, thus obtains the test data of semiconductor unit cell device in corresponding test environment.
Step S112, the parasitic parameter removed in test data, obtain the intrinsic data of semiconductor unit cell device.
In this step, the parasitic parameter that the parasitic structure removing semiconductor unit cell device causes, to obtain the intrinsic data of semiconductor unit cell device, wherein, parasitic parameter may be caused by lead-in wire, metal pad and element layout etc.Therefore, remove the parasitic parameter in test data, exactly the variable quantity of the semiconductor unit cell device property caused by the hardware components such as structure or lead-in wire in the test data of semiconductor unit cell device is removed, only remain the performance data of semiconductor unit cell device intrinsic.
Step S113, intrinsic data according to semiconductor unit cell device, set up the model of tabling look-up of the intrinsic part of semiconductor unit cell device.
Because the semiconductor devices of multiple semiconductor unit cell device composition is when real work, the actual working environment of each semiconductor unit cell device is different, in order to the accurately semiconductor devices of analog operation in external environment, in this actual external environment according to semiconductor devices, set up the external condition distribution index function of semiconductor devices under current outside environment.In addition, the foundation of this function is usually before model is tabled look-up in foundation, its detailed process is, increase an external condition control variable corresponding with semiconductor unit cell device, its numerical value is obtained by the position residing for given external environmental condition and each semiconductor unit cell device, if the numerical value change of external condition control variable, then the external environment of semiconductor unit cell device will change thereupon, and in semiconductor devices, the external environment function of the semiconductor unit cell device of diverse location may be different.
Based on above-mentioned external condition distribution index function, in this step, the intrinsic data of based semiconductor unit cell device, look-up table is utilized to set up the model of tabling look-up of the intrinsic part of semiconductor unit cell device, this intrinsic data on the basis of the test data of semiconductor unit cell device, removes parasitic parameter obtain, and this test data obtains under different test conditions.
In this step, the model of tabling look-up set up can by inquiry symbol wherein, the intrinsic data calling semiconductor unit cell device directly carries out modeling, semiconductor unit cell device is tabling look-up the symbol in model as shown in Figure 2, Fig. 2 gives the schematic symbol diagram that grid width is the model of tabling look-up of the intrinsic part of the semiconductor unit cell device of 1 millimeter, wherein, G20 is the grid of semiconductor unit cell device; D20 is the drain electrode of semiconductor unit cell device; S20 is the source electrode of semiconductor unit cell device.
The model of tabling look-up of the intrinsic part of semiconductor unit cell device can use DAC (MDAC, Data AccessComponent) to set up in ADS (Advanced Design System, Agilent Advanced Design System).
For the test data obtained under different test condition, after can parasitic parameter being removed, be combined into the document of a ctj form, ADS can obtain the test data of semiconductor unit cell device under different test condition by variable index conveniently by tabling look-up.
Step S114, combine at least one semiconductor unit cell device, emulate the intrinsic emulated data getting the semiconductor devices be made up of at least one semiconductor unit cell device.
In this step, semiconductor unit cell device can be combined into semiconductor devices according to connected mode as shown in Figure 3, in this step, specifically for the connected mode shown in Fig. 3, wherein a kind of array mode and the connected mode of semiconductor devices are described, semiconductor devices also can combine according to other connection mode in addition.
Fig. 3 gives the schematic diagram that grid width is the array mode of the intrinsic part of the semiconductor devices of 10 millimeters.As shown in Figure 3, semiconductor devices is made up of identical 10 semiconductor unit cell devices, and has port P1, port P2 and port P3.Concrete, 10 semiconductor unit cell devices are labeled as C1, C2, C3, C4, C5, C6, C7, C8, C9 and C10 successively, the drain electrode of semiconductor unit cell device C1-C10 is labeled as D1, D2, D3, D4, D5, D6, D7, D8, D9 and D10 respectively successively, the grid of semiconductor unit cell device C1-C10 is labeled as G1, G2, G3, G4, G5, G6, G7, G8, G9 and G10 respectively successively, and the source electrode of semiconductor unit cell device C1-C10 is labeled as S1, S2, S3, S4, S5, S6, S7, S8, S9 and S10 respectively successively.
As described in Figure, the drain electrode end D1-D10 of semiconductor unit cell device C1-C10 is connected respectively to port P1, and so port P1 is in the semiconductor device as drain electrode end; The gate terminal G1-G10 of semiconductor unit cell device C1-C10 is connected respectively to port P2, and so port P2 is in the semiconductor device as gate terminal; The source terminal S1-S10 of semiconductor unit cell device C1-C10 is connected respectively to port P3, and so port P3 is in the semiconductor device as source terminal.Set up the model of tabling look-up of the intrinsic part of semiconductor unit cell device, and the model of tabling look-up of intrinsic part according to semiconductor unit cell device, set up the emulated data of the intrinsic part of the semiconductor devices be made up of semiconductor unit cell device, wherein, the emulated data of the intrinsic part of semiconductor devices is exactly the intrinsic emulated data of semiconductor devices.
In this step, combining at least one semiconductor unit cell device can at ADS (Advanced Design System, Agilent Advanced Design System), HFSS (Frequency Structure Simulator, High FrequencyStructure Simulator) etc. in combine, these are existing conventional software, do not repeat at this.
In addition, at least one semiconductor unit cell device of above-mentioned composition semiconductor devices is generally same semiconductor devices, for the bipolar junction transistor of enhancement mode, according to the intrinsic emulated data of a undersized enhancement mode bipolar junction transistor, the intrinsic emulated data of the bipolar junction transistor of the large scale enhancement mode be made up of the bipolar junction transistor of n undersized enhancement mode can be obtained, at this, the bipolar junction transistor of described large-sized enhancement mode is the bipolar junction transistor of n the undersized enhancement mode connected to form by going between.Also it can thus be appreciated that, the grid width of large-sized semiconductor devices is generally the integral multiple of the grid width of undersized semiconductor unit cell device wherein.
The parasitic emulated data of step S120, acquisition semiconductor devices;
In this step, the intrinsic emulated data of known semiconductor device, according to the connection array mode of semiconductor devices, processing technology and design layout, the parasitic structure of emulation semiconductor devices, can obtain the parasitic emulated data of semiconductor devices thus.The parasitic emulated data obtained is the emulated data of the spurious portion of semiconductor devices.Wherein, spurious portion can be the lead-in wire and design layout etc. of semiconductor devices.
Step S130, according to the intrinsic emulated data of semiconductor devices and parasitic emulated data, set up the model of tabling look-up of semiconductor devices.In this step, the intrinsic emulated data of based semiconductor device and parasitic emulated data, utilize look-up table to set up the model of tabling look-up of semiconductor devices.
In this step, the symbol of the semiconductor devices in model of tabling look-up set up as shown in Figure 4, Fig. 4 gives the schematic symbol diagram that grid width is the model of tabling look-up of the semiconductor devices of 10 millimeters, wherein, G40 is the grid of semiconductor devices, D40 is the drain electrode of semiconductor devices, S40 is the source electrode of semiconductor devices, suppose when the semiconductor devices described in Fig. 4 is the semiconductor devices of Fig. 3, so corresponding, the grid G 40 of semiconductor devices is port P2, and the drain D 40 of semiconductor devices is port P1, and the source S 40 of semiconductor devices is port P3.
At this, the model of tabling look-up of semiconductor devices can at ADS (Advanced Design System, Agilent AdvancedDesign System) middle use DAC (MDAC, Data Access Component) set up, because this step carries out foundation according to the intrinsic emulated data that obtains before and parasitic emulated data to table look-up model, its calculated amount is little, and simulation time is short.
Knownly in step S111, the test under different test condition is carried out to semiconductor unit cell device, and the test data obtained under corresponding test condition, so the intrinsic emulated data of semiconductor unit cell device and parasitic emulated data are combined into the document of a ctj form, ADS can obtain by the variable index of semiconductor unit cell device the test data of semiconductor devices under different test condition be made up of at least one semiconductor unit cell device conveniently by tabling look-up.
This step is by superposing the intrinsic emulated data of the semiconductor devices obtained in advance and parasitic emulated data simply, obtain the model of tabling look-up of semiconductor devices, when solving large scale semiconductor devices modeling in prior art, the problem that simulation time is many, emulated data is many and layout complexity is high, decrease the simulation calculating data volume in semiconductor devices modeling process, the simulation calculating time shortened in semiconductor devices modeling process, reduce in semiconductor devices modeling process emulation in device layout's complexity.
The modeling method of the semiconductor devices based on look-up table that the embodiment of the present invention one provides is by the parasitic emulated data of the intrinsic emulated data of semiconductor devices that obtains according to the intrinsic data of semiconductor unit cell device and the semiconductor devices of acquisition, set up semiconductor devices to table look-up model, greatly reduce the simulation calculating data volume in semiconductor devices modeling process; Substantially reduce the simulation calculating time in semiconductor devices modeling process; Greatly reduce the device layout's complexity in the emulation in semiconductor devices modeling process.
Embodiment two
Embodiment one is the description the most basic to the present invention, because semiconductor devices is made up of multiple semiconductor unit cell device, therefore dimensions of semiconductor devices is larger, and during real work, condition in large-sized semiconductor devices residing for each semiconductor unit cell device is not identical, therefore should consider the Distribution Effect in semiconductor devices in modeling process.In order to the large-sized semiconductor devices of accurate analog, need the model of tabling look-up setting up the semiconductor devices considering Distribution Effect.In usual large scale semiconductor devices, Distribution Effect has multiple, specifically sets up at this model of tabling look-up considering Temperature Distribution effect.This modeling method, comprising:
Step S210, intrinsic data according at least one semiconductor unit cell device, obtain the intrinsic emulated data of the semiconductor devices be made up of semiconductor unit cell device described at least one.
In this step, by least one semiconductor unit cell device is connected can be formed semiconductor devices by different connection modes.
Wherein, preferably, described semiconductor unit cell device is the bipolar junction transistor of enhancement mode, field effect transistor or bipolar transistor; Or described semiconductor unit cell device is the bipolar junction transistor of depletion type, field effect transistor or bipolar transistor.
For step S210, preferably its specific implementation process comprises:
S211, the test carried out described semiconductor unit cell device under different test condition, to obtain the test data under corresponding test condition.
Different test conditions can be test environment or other objective condition of semiconductor unit cell device, when test refers to that semiconductor unit cell device is in wherein under any one test condition, the data type used is needed to decide the method for testing of semiconductor unit cell device according in semiconductor unit cell device simulation process.
S212, the parasitic parameter removed in described test data, obtain the intrinsic data of described semiconductor unit cell device.
As mentioned above, parasitic parameter may be caused by lead-in wire, metal pad and element layout etc., therefore the parasitic parameter in test data is removed, exactly the variable quantity of the semiconductor unit cell device property caused by the hardware components such as structure or lead-in wire in the test data of semiconductor unit cell device is removed, only remain the performance data of semiconductor unit cell device intrinsic.
S213, intrinsic data according to described semiconductor unit cell device, set up the model of tabling look-up of the intrinsic part of described semiconductor unit cell device.
Preferably, the preferred implementation process of this step is specially: according to the intrinsic data of described semiconductor unit cell device in varying environment temperature, sets up the model of tabling look-up of described semiconductor unit cell device different temperatures.
Its process specifically can be interpreted as: because the semiconductor devices of multiple semiconductor unit cell device composition is when real work, power is larger, the Temperature Distribution effect of semiconductor devices is serious, the actual working environment temperature of each semiconductor unit cell device is different, be usually expressed as intermediate semiconductor unit cell device equivalent environment temperature high, edge semiconductor unit cell device environment temperature is close to actual environment temperature.In order to the accurately semiconductor devices of analog operation in external environment, in this actual external environment according to semiconductor devices, set up the temperature model of semiconductor devices, the equivalent environment temperature in semiconductor devices during each unit cell devices function is by temperature funtion T=f (R
th, T
0) calculate, wherein T is equivalent environment temperature, R
thfor with the semiconductor unit cell device thermal resistance that present position is relevant in the semiconductor device, T
0for semiconductor devices actual working environment temperature.
In addition, the foundation of this function is usually before model is tabled look-up in foundation, its detailed process is, first the Temperature Distribution of different actual environment temperature lower semiconductor device is measured, obtain the Temperature numerical of diverse location, then obtain temperature funtion T=f (R according to the temperature foh of each unit cell device present position
th, T
0).During emulation, the operating ambient temperature of equivalence can be derived according to the temperature funtion of each semiconductor unit cell device, when then tabling look-up, select the data of relevant temperature.
The model of tabling look-up of the intrinsic part of semiconductor unit cell device can use DAC to set up in ADS, at this, test data removing parasitic parameter obtained under condition of different temperatures is combined into a caj format file, ADS can obtain the test data of semiconductor unit cell device under condition of different temperatures by temperature variable index conveniently by tabling look-up.
S214, combine semiconductor unit cell device described at least one, emulate the intrinsic emulated data getting the semiconductor devices be made up of semiconductor unit cell device described at least one.
As mentioned above, temperature model is added in the model of tabling look-up of known semiconductor unit cell device, study the Temperature Distribution effect of the semiconductor devices combined, according to the Temperature Distribution of semiconductor unit cell device and existing work with semiconductor devices time the environment temperature semiconductor unit cell device temperature index function that is benchmark, so when a certain environment temperature, temperature index function can specify the temperature of diverse location place unit cell device in semiconductor devices.Therefore according to the data of the model of tabling look-up of semiconductor unit cell device, semiconductor devices intrinsic emulated data is at different temperatures set up in emulation.
In addition, in ADS modeling, after use semiconductor unit cell device is combined into semiconductor devices intrinsic part according to certain bus connection method, the temperature control variable corresponding with each semiconductor unit cell device is added in semiconductor devices, its numerical value is obtained by the positional information serviceability temperature index function that given environment temperature and semiconductor unit cell device are residing in the semiconductor device, if temperature control variable numerical value change, the temperature of the semiconductor unit cell device corresponded will change thereupon.
Step S220, obtain the parasitic emulated data of described semiconductor devices.
As mentioned above, the known intrinsic emulated data obtaining semiconductor devices, so preferably, before the parasitic emulated data obtaining described semiconductor devices, according to processing technology and the design layout of semiconductor devices, emulate the parasitic structure of described semiconductor devices, obtain the parasitic emulated data of semiconductor devices successively.
Step S230, according to the intrinsic emulated data of described semiconductor devices and parasitic emulated data, set up the model of tabling look-up of described semiconductor devices.
Preferably, the model of tabling look-up setting up described semiconductor devices also comprises: according to the Temperature Distribution effect of semiconductor devices, obtain the temperature funtion of the semiconductor unit cell device in described semiconductor devices, set up the model of tabling look-up that described semiconductor devices comprises temperature model.
As mentioned above, the intrinsic emulated data of known semiconductor device and parasitic emulated data, according to the Temperature Distribution effect of semiconductor devices, obtain the temperature funtion of the semiconductor unit cell device in semiconductor devices, set up according to intrinsic emulated data and parasitic emulated data the model of tabling look-up that described semiconductor devices comprises temperature model so accordingly, this model of tabling look-up considers the Temperature Distribution effect in semiconductor devices.
In addition, in the present embodiment known, at least one semiconductor unit cell device constitutes semiconductor devices, and so, preferably, the grid width of described semiconductor devices is the integral multiple of the grid width of described semiconductor unit cell device.
The embodiment of the present invention two is on the basis of Temperature Distribution effect considering semiconductor devices, by the parasitic emulated data of the intrinsic emulated data of semiconductor devices that obtains according to the intrinsic data of semiconductor unit cell device and the semiconductor devices of acquisition, set up the model of tabling look-up that semiconductor devices comprises temperature model, according to the Temperature Distribution effect Modling model of semiconductor devices in real work, the simulation calculating data volume in semiconductor devices modeling process can be greatly reduced; Substantially reduce the simulation calculating time in semiconductor devices modeling process; Greatly reduce the device layout's complexity in the emulation in semiconductor devices modeling process.
Embodiment three:
Fig. 5 gives the structural drawing of the modeling of the semiconductor devices based on look-up table that the embodiment of the present invention three provides.This modeling comprises: intrinsic emulated data acquisition module 310, parasitic emulated data acquisition module 320 and model building module 330.
Wherein, intrinsic emulated data acquisition module 310, for the intrinsic data according at least one semiconductor unit cell device, obtains the intrinsic emulated data of the semiconductor devices be made up of at least one semiconductor unit cell device; Parasitic emulated data acquisition module 320 is for obtaining the parasitic emulated data of described semiconductor devices; Model building module 330, for according to the intrinsic emulated data of described semiconductor devices and parasitic emulated data, sets up the model of tabling look-up of described semiconductor devices.
Preferably, semiconductor unit cell device can be the bipolar junction transistor of enhancement mode, field effect transistor or bipolar transistor, or the bipolar junction transistor of depletion type, field effect transistor or bipolar transistor.
Wherein, field effect transistor can be mos field effect transistor, metal dielectric layer semiconductor field effect transistor, dual heterogeneity node field effect transistor, junction field effect transistor, metal-semiconductor field effect transistor or metal dielectric layer heterogeneous semiconductor junction field effect transistor, and bipolar junction transistor can be insulated gate bipolar transistor; The grid width of semiconductor devices is not less than 10 millimeters.
At this preferably, intrinsic emulated data acquisition module 310, can comprise: semiconductor unit cell device test data acquiring unit 311, semiconductor unit cell device intrinsic data acquiring unit 312, semiconductor unit cell device model set up unit 313 and semiconductor devices intrinsic emulated data acquiring unit 314.
Wherein, semiconductor unit cell device test data acquiring unit 311 for carrying out the test under different test condition to semiconductor unit cell device, to obtain the test data under corresponding test condition; Semiconductor unit cell device intrinsic data acquiring unit 312, for removing the parasitic parameter in test data, obtains the intrinsic data of semiconductor unit cell device; Semiconductor unit cell device model sets up unit 313 for the intrinsic data according to semiconductor unit cell device, sets up the model of tabling look-up of the intrinsic part of semiconductor unit cell device; Semiconductor devices intrinsic emulated data acquiring unit 314, for combining semiconductor unit cell device described at least one, emulates the intrinsic emulated data getting the semiconductor devices be made up of semiconductor unit cell device described at least one.
Preferably, described semiconductor unit cell device model is set up the concrete implementation of unit 313 and is:
According to the intrinsic data of described semiconductor unit cell device in varying environment temperature, set up the model of tabling look-up of described semiconductor unit cell device different temperatures.
Preferably, before described parasitic emulated data acquisition module 320, described modeling also comprises: parasitic structure emulation module 340.
Wherein, parasitic structure emulation module 340 for according to the processing technology of semiconductor devices and design layout, the parasitic structure of emulation semiconductor devices.
Preferably, described model building module 330 also comprises: according to the Temperature Distribution effect of semiconductor devices, obtains the temperature funtion of the semiconductor unit cell device in described semiconductor devices, sets up the model of tabling look-up that described semiconductor devices comprises temperature model.
Preferably, the grid width of described semiconductor devices is the integral multiple of the grid width of described semiconductor unit cell device.
The modeling of the semiconductor devices based on look-up table that the embodiment of the present invention three provides is by the parasitic emulated data of the intrinsic emulated data of semiconductor devices that obtains according to the intrinsic data of semiconductor unit cell device and the semiconductor devices of acquisition, set up semiconductor devices to table look-up model, greatly reduce the simulation calculating data volume in semiconductor devices modeling process; Substantially reduce the simulation calculating time in semiconductor devices modeling process; Greatly reduce the device layout's complexity in the emulation in semiconductor devices modeling process.
The know-why that above are only preferred embodiment of the present invention and use.The invention is not restricted to specific embodiment described here, the various significant changes can carried out for a person skilled in the art, readjust and substitute all can not depart from protection scope of the present invention.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by the scope of claim.
Claims (14)
1. based on a modeling method for the semiconductor devices of look-up table, it is characterized in that, comprising:
According to the intrinsic data of at least one semiconductor unit cell device, obtain the intrinsic emulated data of the semiconductor devices be made up of semiconductor unit cell device described at least one;
Obtain the parasitic emulated data of described semiconductor devices;
According to intrinsic emulated data and the parasitic emulated data of described semiconductor devices, set up the model of tabling look-up of described semiconductor devices.
2. the modeling method of the semiconductor devices based on look-up table according to claim 1, is characterized in that, described semiconductor unit cell device is the bipolar junction transistor of enhancement mode, field effect transistor or bipolar transistor; Or
Described semiconductor unit cell device is the bipolar junction transistor of depletion type, field effect transistor or bipolar transistor.
3. the modeling method of the semiconductor devices based on look-up table according to claim 1, it is characterized in that, the described intrinsic data according at least one semiconductor unit cell device, obtains the intrinsic emulated data of the semiconductor devices be made up of semiconductor unit cell device described at least one, comprising:
Described semiconductor unit cell device is carried out to the test under different test condition, to obtain the test data under corresponding test condition;
Remove the parasitic parameter in described test data, obtain the intrinsic data of described semiconductor unit cell device;
According to the intrinsic data of described semiconductor unit cell device, set up the model of tabling look-up of the intrinsic part of described semiconductor unit cell device;
Combine semiconductor unit cell device described at least one, emulate the intrinsic emulated data getting the semiconductor devices be made up of semiconductor unit cell device described at least one.
4. the modeling method of the semiconductor devices based on look-up table according to claim 3, is characterized in that, according to the intrinsic data of described semiconductor unit cell device, the concrete implementation of model of tabling look-up setting up the intrinsic part of described semiconductor unit cell device is:
According to the intrinsic data of described semiconductor unit cell device in varying environment temperature, set up the model of tabling look-up of described semiconductor unit cell device different temperatures.
5. the modeling method of the semiconductor devices based on look-up table according to claim 1, is characterized in that, before the described parasitic emulated data obtaining described semiconductor devices, also comprises:
According to processing technology and the design layout of described semiconductor devices, emulate the parasitic structure of described semiconductor devices.
6. the modeling method of the semiconductor devices based on look-up table according to claim 4, it is characterized in that, set up the model of tabling look-up of described semiconductor devices, also comprise: according to the Temperature Distribution effect of semiconductor devices, obtain the temperature funtion of the semiconductor unit cell device in described semiconductor devices, set up the model of tabling look-up that described semiconductor devices comprises temperature model.
7., according to the modeling method of the arbitrary described semiconductor devices based on look-up table of claim 1-6, it is characterized in that, the grid width of described semiconductor devices is the integral multiple of the grid width of described semiconductor unit cell device.
8. based on a modeling for the semiconductor devices of look-up table, it is characterized in that, comprising:
Intrinsic emulated data acquisition module, for the intrinsic data according at least one semiconductor unit cell device, obtains the intrinsic emulated data of the semiconductor devices be made up of semiconductor unit cell device described at least one;
Parasitic emulated data acquisition module, for obtaining the parasitic emulated data of described semiconductor devices;
Model building module, for according to the intrinsic emulated data of described semiconductor devices and parasitic emulated data, sets up the model of tabling look-up of described semiconductor devices.
9. the modeling of the semiconductor devices based on look-up table according to claim 8, is characterized in that, described semiconductor unit cell device is the bipolar junction transistor of enhancement mode, field effect transistor or bipolar transistor; Or
Described semiconductor unit cell device is the bipolar junction transistor of depletion type, field effect transistor or bipolar transistor.
10. the modeling of the semiconductor devices based on look-up table according to claim 8, is characterized in that, described intrinsic emulated data acquisition module comprises:
Semiconductor unit cell device test data acquiring unit, for carrying out the test under different test condition to described semiconductor unit cell device, to obtain the test data under corresponding test condition;
Semiconductor unit cell device intrinsic data acquiring unit, for removing the parasitic parameter in described test data, obtains the intrinsic data of described semiconductor unit cell device;
Semiconductor unit cell device model sets up unit, for the intrinsic data according to described semiconductor unit cell device, sets up the model of tabling look-up of the intrinsic part of described semiconductor unit cell device;
Semiconductor devices intrinsic emulated data acquiring unit, for combining semiconductor unit cell device described at least one, emulates the intrinsic emulated data getting the semiconductor devices be made up of semiconductor unit cell device described at least one.
The modeling of 11. semiconductor devices based on look-up table according to claim 10, is characterized in that, described semiconductor unit cell device model is set up the concrete implementation of unit and is:
According to the intrinsic data of described semiconductor unit cell device in varying environment temperature, set up the model of tabling look-up of described semiconductor unit cell device different temperatures.
The modeling of 12. semiconductor devices based on look-up table according to claim 8, is characterized in that, before described parasitic emulated data acquisition module, described modeling also comprises:
Parasitic structure emulation module, for according to the processing technology of described semiconductor devices and design layout, emulates the parasitic structure of described semiconductor devices.
The modeling of 13. semiconductor devices based on look-up table according to claim 11, it is characterized in that, described model building module also comprises: according to the Temperature Distribution effect of semiconductor devices, obtain the temperature funtion of the semiconductor unit cell device in described semiconductor devices, set up the model of tabling look-up that described semiconductor devices comprises temperature model.
The modeling of 14.-13 arbitrary described semiconductor devices based on look-up table according to Claim 8, it is characterized in that, the grid width of described semiconductor devices is the integral multiple of the grid width of described semiconductor unit cell device.
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