CN108878416A - ESD protection circuit - Google Patents

ESD protection circuit Download PDF

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Publication number
CN108878416A
CN108878416A CN201810691993.XA CN201810691993A CN108878416A CN 108878416 A CN108878416 A CN 108878416A CN 201810691993 A CN201810691993 A CN 201810691993A CN 108878416 A CN108878416 A CN 108878416A
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CN
China
Prior art keywords
protection circuit
esd protection
nmos tube
resistance
capacitor
Prior art date
Application number
CN201810691993.XA
Other languages
Chinese (zh)
Inventor
贺吉伟
周俊
Original Assignee
武汉新芯集成电路制造有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉新芯集成电路制造有限公司 filed Critical 武汉新芯集成电路制造有限公司
Priority to CN201810691993.XA priority Critical patent/CN108878416A/en
Publication of CN108878416A publication Critical patent/CN108878416A/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

The invention discloses a kind of ESD protection circuit, the ESD protection circuit includes NMOS tube, capacitor and resistance;The grid of the NMOS tube is connected to ground terminal by the resistance by the capacitance connection to power end, the grid of the NMOS tube, and the source electrode of the NMOS tube connects power end, and the drain electrode of the NMOS tube connects ground terminal.Then the ESD protection circuit is equivalent to the trigger circuit in grid increase by one capacitor and resistance of the NMOS tube; it can help improve grid voltage and reduce trigger voltage of the esd protection circuit in working condition; and the response speed of esd protection circuit is promoted, to greatly improve the antistatic performance of esd protection circuit.

Description

ESD protection circuit

Technical field

The present invention relates to field of semiconductor manufacture more particularly to a kind of ESD protection circuits.

Background technique

Integrated circuit is easy the destruction by electrostatic, generally all can in the input/output terminal of circuit or apparatus for protecting power supply Static discharge (Electro-Static discharge, ESD) protection circuit is designed to prevent internal circuit to be damaged because of electrostatic It is bad.Currently, quiet through being used as frequently with GGNMOS (Gate Grounded NMOS, grounded-grid N-type metal-oxide semiconductor (MOS)) Discharge of electricity protects circuit.

However, in the prior art, because the trigger voltage of GGNMOS structure itself is higher, the response speed of esd protection circuit Degree is slow, then ESD protective capability is not good enough.

Therefore, in view of the above technical problems, it is necessary to which a kind of improved ESD protection circuit is provided.

Summary of the invention

Technical problem to be solved by the invention is to provide a kind of ESD protection circuit, trigger voltage is lower and rings Fast speed is answered, the performance of esd protection circuit can be improved.

In order to solve the above technical problems, ESD protection circuit provided by the invention, including:NMOS tube, capacitor and electricity Resistance;The grid of the NMOS tube is connected by the capacitance connection to power end, the grid of the NMOS tube by the resistance To ground terminal, the source electrode of the NMOS tube connects power end, and the drain electrode of the NMOS tube connects ground terminal.

Further, in the ESD protection circuit, the capacitor is PMOS tube, wherein the PMOS tube Grid be connected as one end of the capacitor with the grid of the NMOS tube, three end of source electrode, drain electrode and trap of the PMOS tube It is shorted another termination power end as the capacitor.

Further, in the ESD protection circuit, the trap of the trap of the PMOS tube and the NMOS tube exists Reversed PN junction isolation is formed when working condition.

Optionally, in the ESD protection circuit, the resistance is p-type polysilicon resistance.

Further, in the ESD protection circuit, the width of the p-type polysilicon resistance is at 0.5 micron To between 1 micron.

Further, in the ESD protection circuit, the time constant of the resistance and the capacitor is 10 Nanosecond is between 500 nanoseconds.

Further, in the ESD protection circuit, the time constant of the resistance and the capacitor is 100 Nanosecond.

Further, in the ESD protection circuit, the resistance value of the resistance 20 kilo-ohms to 500 kilo-ohms it Between.

Further, in the ESD protection circuit, the capacitance of the capacitor is in 0.2 pico farad to 5 pico farads Between.

Compared with prior art, the invention has the advantages that:

ESD protection circuit of the invention includes NMOS tube, capacitor and resistance;The grid of the NMOS tube passes through institute Capacitance connection is stated to power end, the grid of the NMOS tube is connected to ground terminal, the source electrode of the NMOS tube by the resistance Power end is connected, the drain electrode of the NMOS tube connects ground terminal.Then the ESD protection circuit is equivalent in the NMOS The grid of pipe increases the trigger circuit of a capacitor and resistance, can help improve grid voltage and reduces esd protection circuit and exists Trigger voltage when working condition, and the response speed of esd protection circuit is promoted, to greatly improve the anti-of esd protection circuit Antistatic property.

Detailed description of the invention

Fig. 1 is a kind of attachment structure schematic diagram of the ESD protection circuit provided in the embodiment of the present invention;

Fig. 2 is the schematic diagram of the section structure inside ESD protection circuit described in the embodiment of the present invention.

Specific embodiment

In order to make those skilled in the art more fully understand the present invention program, below in conjunction with the drawings and specific embodiments to this The ESD protection circuit of invention is described in further detail, and according to following explanation, advantages and features of the invention will more It is clear.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to convenient, apparent Ground aids in illustrating the embodiment of the present invention, and the embodiment of the present invention should not be considered limited to the specific shape in region as shown in the figure Shape.For the sake of clarity, in whole attached drawings for aiding in illustrating the embodiment of the present invention, phase is marked in principle to same parts Same label, and omit to its repeat description, but the label of all identical components will not be marked in each figure by attached drawing.

Also, term used herein above is merely to description specific embodiment, and the implementation of not intended to limit the application Mode.As used herein, unless the context clearly indicates otherwise, otherwise singular is also intended to include plural form; It should be understood that indicating existing characteristics, step, behaviour when in the present specification using "comprising" and/or " comprising " is belonged to Work, device, component and/or their combination;Term " first " " second " etc. is used between similar element distinguish, and not It must be for describing certain order or time sequencing, it is understood that in the appropriate case, these terms so used are replaceable; It is similar, if method described herein includes series of steps, and the sequence of these steps presented herein be not can The unique order of these steps is executed, some steps can be omitted and/or some other steps not described herein can It is added to this method;For ease of description, spatially relative term can be used herein, as " ... on ", " ... Top ", " in ... upper surface ", " above " etc., for describing a device or feature as depicted in the figures and other The spatial relation of device or feature.It should be understood that spatially relative term is intended to comprising in addition to device is retouched in figure Different direction in use or operation except the orientation stated.For example, if the device in attached drawing is squeezed or with other Different modes positioning (as rotated), exemplary term " ... top " also may include " ... lower section " and other orientation pass System.

Please refer to Fig. 1 and Fig. 2, wherein Fig. 1 is a kind of connection structure of ESD protection circuit provided in this embodiment Schematic diagram, Fig. 2 are the schematic diagram of the section structure inside ESD protection circuit described in the present embodiment, and the static discharge is protected Protection circuit includes:NMOS tube, capacitor C and resistance R, wherein the grid of the NMOS tube is connected to power end by the capacitor C The grid of VCC, the NMOS tube are connected to ground terminal GND by the resistance R, and the source electrode of the NMOS tube connects power end The drain electrode of VCC, the NMOS tube connect ground terminal GND, as shown in Figure 1.

Preferably, in order to guarantee that RC trigger circuit works normally and esd protection circuit has enough electrostatic protections Ability, meanwhile, different electrostatic protection demands can be coped with, the time constant of the resistance R and the capacitor C should be received between 10 Second, in the present embodiment, the time constant was preferably that 100 nanoseconds, (time constant can be used as reference value between 500 nanoseconds Or representative value), ESD performance is preferable.Correspondingly, the numerical value of the capacitor C and resistance R are advanced optimized, to ensure that ESD is excellent Performance after change, it is preferred that the capacitance of the capacitor C can be in 0.2 pico farad between 5 pico farads, and such as capacitance is in 1 skin Method, 2 pico farads or 3 pico farads etc..Further, in order to save device area, the resistance R is p-type polysilicon resistance, the p-type The width of polysilicon resistance can be between 0.5 micron to 1 micron, such as 0.8 micron, as the length of the polysilicon resistance Depending on the resistance sizes that can according to need, herein and without limitation.The resistance value of the resistance 20 kilo-ohms to 500 kilo-ohms it Between, such as the resistance value is 100 kilo-ohms, 200 kilo-ohms, 300 kilo-ohms or 400 kilo-ohms.Preferably, in the present embodiment, the capacitor C For PMOS tube, wherein the grid of the PMOS tube is connected as one end of the capacitor C with the grid of the NMOS tube, described Source electrode, drain electrode and three end of trap of PMOS tube are shorted another termination power end VCC as the capacitor C.

Specifically, the schematic diagram of the section structure inside the ESD protection circuit is as shown in Fig. 2, the step of it is formed It can be, but not limited to following procedure:

Firstly, semi-conductive substrate (substrate) 1 is provided, such as P-type semiconductor substrate.

Then, p-well (P-Well) 10 and N trap (N-Well) 11 are formed in the semiconductor substrate 1, wherein in the P The region of trap forms required NMOS tube, the capacitor of required PMOS tube is formed in the region of the N trap, because of the static discharge Protect circuit in the operating condition, the N trap of the capacitor of the PMOS tube needs to connect power end VCC, then N trap 11 and p-well 10 it Between will form reversed PN junction isolation.In addition, in the semiconductor substrate 1 also shallow ridges can be formed by shallow ditch groove separation process Recess isolating structure STI, as shown in Figure 2.

Then, the deposit polycrystalline silicon layer in the semiconductor substrate 1, and required grid are formed by lithography and etching technique Pole structure, the gate structure include on the first grid (grid of NMOS tube) 20 and the N trap 11 in the p-well 10 Second grid (grid of PMOS tube) 21, while forming gate structure, on the fleet plough groove isolation structure STI also shape At required p-type polysilicon resistance 22.In addition, before deposit polycrystalline silicon layer, it will usually the first shape in the semiconductor substrate 1 At a gate oxide (schematic diagram omits in figure), this is technical means commonly used by such a person skilled in the art, is not detailed Jie herein It continues.

Next, at least forming two N-doped zones (N+, N-type source and drain in the p-well 10 by ion implantation technology Area) 100, N-doped zone can be used as the source electrode and drain electrode of NMOS tube;Equally, by ion implantation technology in the N trap 11 shape At two P-doped zones (P+, p-type source-drain area) 110, P-doped zone can be used as the source electrode and drain electrode of PMOS tube.Certainly, described Ion implantation technology includes shallow doping process (LDD) and deep doping process (HDD).

Then, as shown in Fig. 2, the p-well 10, first grid 20 and N-doped zone 100 just constitute NMOS tube, institute It states N trap 11, second grid 21 and two P-doped zones 110 and just constitutes PMOS tube, using the grid of the PMOS tube as electricity The one end for holding C connects the grid (first grid) 20 of the NMOS tube, by N trap 11 in the PMOS tube and two P-doped zones 110 are shorted the other end connection power end VCC as capacitor C, meanwhile, by the grid of the NMOS tube and the p-type polysilicon One end of resistance 22 is connected, and the other end of the p-type polysilicon resistance 22 connects ground terminal GND.In addition, by the NMOS tube In source electrode (N+) connect power end VCC, the drain electrode (N+) in the NMOS tube connects ground terminal GND.Pass through the connection type Just the connection structure diagram of electrostatic discharge protective circuit as shown in Figure 1 has been obtained.

ESD protection circuit described in the present embodiment is equivalent to the grid in NMOS tube and increases a resistance R and capacitor The trigger circuit of C carries out corresponding electrically emulation, the data electrically emulated to the ESD protection circuit and shows, Under the conditions of power end VCC adds different voltages, grid voltage VG, the drain current ID and substrate current IB of the NMOS tube are equal Can be significantly raised with the voltage value raising of power end VCC, such as when the voltage value of power end VCC increases 1V, grid voltage VG increases about 0.1V~0.5V, and drain current ID increases about 0.8A~1.2A, and substrate current IB about increases 0.5A;Work as power end When the voltage value of VCC increases 2V, grid voltage VG increases about 0.5V~1.0V, and drain current ID increases about 1.6A~2.6A, lining Bottom electric current IB about increases 1.3A~1.7A.Then for NMOS tube, by the increased mode of grid voltage VG, substrate can be allowed It first opens and replaces breakdown and shorting advance generates substrate current, i.e., parasitic NPN is connected (when substrate current IB is bigger in NMOS tube When, parasitic NPN is easier to be turned on), and then reduce the trigger voltage of the esd protection circuit and improve its response speed, Be finally reached improve esd protection circuit protective capacities, such as at human-body model (HBM) can anti-5000V, in Machinery model It (MM) can anti-200V.In addition, the esd protection circuit structure will not influence device area.

To sum up, ESD protection circuit of the invention includes NMOS tube, capacitor and resistance;The grid of the NMOS tube is logical The capacitance connection is crossed to power end, the grid of the NMOS tube is connected to ground terminal by the resistance, the NMOS tube Source electrode connects power end, and the drain electrode of the NMOS tube connects ground terminal.Then the ESD protection circuit is equivalent to described The grid of NMOS tube increases the trigger circuit of a capacitor and resistance, can help improve grid voltage and reduces ESD protection electricity Trigger voltage of the road in working condition, and the response speed of esd protection circuit is promoted, to greatly improve esd protection circuit Antistatic performance.

Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to include these modifications and variations.

Claims (9)

1. a kind of ESD protection circuit, which is characterized in that including:NMOS tube, capacitor and resistance;The grid of the NMOS tube By the capacitance connection to power end, the grid of the NMOS tube is connected to ground terminal, the NMOS tube by the resistance Source electrode connect power end, the drain electrode of the NMOS tube connects ground terminal.
2. ESD protection circuit as described in claim 1, it is characterised in that:The capacitor is PMOS tube, wherein described The grid of PMOS tube is connected as one end of the capacitor with the grid of the NMOS tube, the source electrode of the PMOS tube, drain electrode and Three end of trap is shorted another termination power end as the capacitor.
3. ESD protection circuit as claimed in claim 2, it is characterised in that:The trap of the PMOS tube and the NMOS tube Trap the isolation of reversed PN junction is formed in working condition.
4. ESD protection circuit as described in claim 1, it is characterised in that:The resistance is p-type polysilicon resistance.
5. ESD protection circuit as claimed in claim 4, it is characterised in that:The width of the p-type polysilicon resistance exists Between 0.5 micron to 1 micron.
6. the ESD protection circuit as described in claim 1 to 5 any one, it is characterised in that:The resistance and described The time constant of capacitor is in 10 nanoseconds between 500 nanoseconds.
7. ESD protection circuit as claimed in claim 6, it is characterised in that:The time of the resistance and the capacitor is normal Number was 100 nanoseconds.
8. the ESD protection circuit as described in claim 1 to 5 any one, it is characterised in that:The resistance value of the resistance Between 20 kilo-ohms to 500 kilo-ohms.
9. the ESD protection circuit as described in claim 1 to 5 any one, it is characterised in that:The capacitor of the capacitor Value is in 0.2 pico farad between 5 pico farads.
CN201810691993.XA 2018-06-28 2018-06-28 ESD protection circuit CN108878416A (en)

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Application Number Priority Date Filing Date Title
CN201810691993.XA CN108878416A (en) 2018-06-28 2018-06-28 ESD protection circuit

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060170054A1 (en) * 2004-12-15 2006-08-03 Mergens Markus P J Device having a low-voltage trigger element
KR20060135225A (en) * 2005-06-24 2006-12-29 주식회사 하이닉스반도체 Esd protective power clamp circuit for semiconductor circuit
CN101383345A (en) * 2007-09-04 2009-03-11 和舰科技(苏州)有限公司 Esd protection circuit with coupling capacitor
CN102593122A (en) * 2011-01-10 2012-07-18 英飞凌科技股份有限公司 Semiconductor ESD circuit and method
CN102593121A (en) * 2011-01-14 2012-07-18 半导体元件工业有限责任公司 Semiconductor device
CN103117280A (en) * 2013-02-25 2013-05-22 无锡凌湖科技有限公司 Electro-static discharge (ESD) protection structure between voltage drain drain (VDD) and voltage source source (VSS) under submicron process
CN106098683A (en) * 2016-07-06 2016-11-09 芯海科技(深圳)股份有限公司 A kind of esd protection circuit
CN207367971U (en) * 2017-11-07 2018-05-15 福建晋润半导体技术有限公司 A kind of esd protection circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060170054A1 (en) * 2004-12-15 2006-08-03 Mergens Markus P J Device having a low-voltage trigger element
KR20060135225A (en) * 2005-06-24 2006-12-29 주식회사 하이닉스반도체 Esd protective power clamp circuit for semiconductor circuit
CN101383345A (en) * 2007-09-04 2009-03-11 和舰科技(苏州)有限公司 Esd protection circuit with coupling capacitor
CN102593122A (en) * 2011-01-10 2012-07-18 英飞凌科技股份有限公司 Semiconductor ESD circuit and method
CN102593121A (en) * 2011-01-14 2012-07-18 半导体元件工业有限责任公司 Semiconductor device
CN103117280A (en) * 2013-02-25 2013-05-22 无锡凌湖科技有限公司 Electro-static discharge (ESD) protection structure between voltage drain drain (VDD) and voltage source source (VSS) under submicron process
CN106098683A (en) * 2016-07-06 2016-11-09 芯海科技(深圳)股份有限公司 A kind of esd protection circuit
CN207367971U (en) * 2017-11-07 2018-05-15 福建晋润半导体技术有限公司 A kind of esd protection circuit

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