CN109752612A - A kind of artificial circuit and method of chip esd protection circuit - Google Patents
A kind of artificial circuit and method of chip esd protection circuit Download PDFInfo
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- CN109752612A CN109752612A CN201811643069.0A CN201811643069A CN109752612A CN 109752612 A CN109752612 A CN 109752612A CN 201811643069 A CN201811643069 A CN 201811643069A CN 109752612 A CN109752612 A CN 109752612A
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Abstract
The present invention provides the artificial circuit and method of a kind of chip esd protection circuit, can find the device of anti-ESD ability difference in chip in advance by emulating, and optimizes circuit, improves the ability of the anti-ESD of chip.The artificial circuit includes an ESD driving source being connected between supply voltage VDD and common ground voltage VSS, an ESD protective module and at least one functional module；The ESD driving source is used to load ESD voltage according to the ESD current characteristic curve of setting；Power clamp NMOS tube NESD is provided in the ESD protective module, the drain electrode of power clamp NMOS tube NESD is arranged a current monitor Ifail and connect with supply voltage VDD, and source electrode connects common ground voltage VSS；It is provided with CMOS tube N1 in the functional module, a voltage monitor Efail is respectively set between the grid and drain electrode of CMOS tube N1 and between grid and source level.
Description
Technical field
The present invention relates to the emulation testing of chip, the specially a kind of artificial circuit and method of chip esd protection circuit.
Background technique
In the prior art, each chip includes ESD protective module and corresponding functional module, as shown in Figure 1.ESD is protected
The grid g1 that shield module generally comprises large scale power clamp NMOS tube NESD, NESD is connected to power vd D by capacitor C1, together
When by resistance R1 be connected to ground VSS.
The various functions of Implement of Function Module chip, including CMOS tube N1 it is very sensitive to ESD, the grid oxygen of N1 is very
It is easy to be destroyed by esd event, emphasis is needed to verify.In Fig. 1, Rvdd is VDD power supply from pad to the power supply of ESD protective module
Network resistor, Rvss are VSS from pad to the ground resistance of ESD protective module.
When the ESD impact that chip is in PS mode (VDD=+ESD pulse, VSS=0) occurs, there will be electric current to flow from VDD
To VSS, as shown in Figure 2.When esd event under PS mode occurs, positive current Iesd, by Rvdd, is flowed through since VDD pad
NESD, then by Rvss, eventually flow on VSS pad.If ESD intensity is very big, Iesd is very big, then flows through the electric current of NESD
It is very big, it may cause NESD and be burned out, as NESD node 1 may be blown in Fig. 2.Simultaneously if ESD intensity is big, may be used also
Drain-to-gate voltage (Vgd) or the gate source voltage (Vgs) of N1 pipe can be caused excessive, it is exhausted so as to cause the grid oxygen among grid leak or grid source
Edge layer (node 2 or node 3) is breakdown.
How in complicated esd event, whether look-ahead Fig. 2 interior joint 1, node 2 and node 3 can be by ESD impacts
Damage, it is very significant for optimization ESD protection scheme and electric power network.
Summary of the invention
Aiming at the problems existing in the prior art, the present invention provides artificial circuit and the side of a kind of chip esd protection circuit
Method, the device of anti-ESD ability difference in chip can be found by emulating in advance, and optimizes circuit, improve the energy of the anti-ESD of chip
Power.
The present invention is to be achieved through the following technical solutions:
A kind of artificial circuit of chip esd protection circuit, including it is connected to supply voltage VDD and common ground voltage VSS
Between an ESD driving source, ESD protective module and at least one functional module；
The ESD driving source is used to load ESD voltage according to the ESD current characteristic curve of setting；
Power clamp NMOS tube NESD, the drain electrode of power clamp NMOS tube NESD are provided in the ESD protective module
A current monitor Ifail is arranged to connect with supply voltage VDD, source electrode connects common ground voltage VSS；
CMOS tube N1 is provided in the functional module, between the grid and drain electrode of CMOS tube N1 and grid and source
A voltage monitor Efail is respectively set between grade.
Preferably, supply voltage VDD is public to connect from pad to setting electric power network resistance Rvdd ESD protective module
Ground voltage VSS is from pad to setting ground resistance Rvss ESD protective module.
Preferably, ESD protective module further includes that the grid of capacitor C1 and resistance R1 power clamp NMOS tube NESD passes through electricity
Hold C1 connection supply voltage VDD, grid passes through resistance R1 connection common ground voltage VSS.
A kind of emulation mode of chip esd protection circuit, includes the following steps,
Step 1 determines that chip needs ESD rank to be achieved；
Step 2, the ESD current characteristic curve for obtaining determining ESD rank from factory or customers' place；
Step 3 passes through mathematical modeling, removes fitting ESD current characteristic curve；
Step 4, according to the artificial circuit in above scheme, current monitor Ifail and voltage are inserted into artificial circuit
Monitor Efail；
Step 5, the current limit value that can bear and voltage limit that device is obtained from technique factory, and be input to corresponding
Current monitor Ifail and voltage monitor Efail in；
Step 6 opens current monitor Ifail switch, is monitored to the electric current in ESD emulation；
Step 7 opens ESD driving source, starts to emulate according to fitting ESD current characteristic curve；
If step 8, current monitor Ifail electric current exceed set limiting value, actual effect mistake is reported, is then increased
After power clamp NMOS tube NESD size in ESD protective module, repeats step 7 and emulate again；
If step 9, current monitor Ifail electric current open voltage monitor without departing from set limiting value
Efail switch is monitored the voltage in ESD emulation；
If step 10, voltage monitor Efail voltage exceed set limiting value, actual effect mistake is reported, reduces electricity
Source network resistance Rvdd and ground resistance Rvss increases power clamp NMOS tube NESD size in ESD protective module, imitates again
Very；
If step 11, voltage monitor Efail voltage have without departing from set limiting value, ESD protective module
Effect, emulation terminate.
Preferably, in step 1, determining that chip needs ESD rank to be achieved is the HBM model of 2000V.
Preferably, specifically, going the specific steps of fitting ESD current characteristic curve such as by mathematical modeling in step 3
Under,
Step 3.1, description ESD current characteristics, the electricity for the ESD driving source being fitted are gone by mathematical formulae below
Properties of flow curve；
As Time≤Td；
As Time > Td；
Wherein, Time is the time coordinate in esd discharge process,Vhbm is to determine that chip needs
The corresponding model voltage of ESD rank reached；τ 1 is the time constant that ESD electric current rises, and τ 2 is that the time of ESD electric current decline is normal
Number, Td are ESD electric current downward trend sart point in time；
Step 3.2, the current characteristic curve and work that are fitted ESD driving source are made by regulating time parameter τ 1, τ 2 and Td
Factory provides ESD current characteristic curve and approaches, to obtain the fitting ESD current characteristic curve for ESD driving source.
Compared with prior art, the invention has the following beneficial technical effects:
The present invention by increasing current monitor in the ESD protective device in ESD protective module, can emulation when pair
The maximum electric current that bears of ESD protective device is limited and is protected, and avoids protecting device itself to have an impact ESD, while real
The verifying and detection to current parameters are showed；By in the voltage monitor and grid in functional module in CMOS tube between grid leak pole
Voltage monitor between source electrode can bear voltage to CMOS tube grid oxygen maximum in emulation and be limited and be protected, avoid
CMOS tube itself is had an impact, while realizing the verifying and detection to voltage parameter.
Detailed description of the invention
Fig. 1 is chip interior modular structure schematic diagram in the prior art.
Fig. 2 is the ESD current path under chip PS mode in the prior art.
Fig. 3 is the modular structure schematic diagram of artificial circuit described in present example.
Fig. 4 is the ESD current characteristic curve of human body discharge's model described in present example.
Fig. 5 compares figure with current characteristic curve under truth for fitting described in present example.
Fig. 6 is the flow chart of emulation mode described in present example.
Specific embodiment
Below with reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
Artificial circuit of the present invention, as shown in figure 3, increasing between supply voltage VDD and common ground voltage VSS
1 current monitor (Ifail) and CMOS tube N1 is arranged in the drain electrode of power clamp NMOS tube NESD in 1 ESD driving source
1 voltage monitor (Efail) is respectively set between grid and drain electrode and between grid and source level.Power clamp NMOS tube
By capacitor C1 connection supply voltage VDD, grid passes through resistance R1 connection common ground voltage VSS, Rvdd is the grid of NESD
Electric power network resistance of the supply voltage VDD from pad to ESD protective module, Rvss are common ground voltage VSS from pad to ESD
The ground resistance of protective module.
Specifically, ESD driving source be describe specific esd event when current characteristic curve, with environment temperature, wetness with
And the way of contact is related, current characteristic curve is provided by chip application client or ESD test factory.If Fig. 4 is exactly certain factory
The HBM (human body discharge's model) of offer is equal to ESD current characteristic curve when 2000V.
ESD current characteristic curve, such as Fig. 4, founding mathematical models are provided according to factory.It goes to describe with mathematical formulae below
Current characteristics:
As Time≤Td；
As Time > Td；
Wherein Vhbm=2000v, human body discharge's model voltage are set as 2000V
Time parameter: τ 1=5.2ns τ 2=150ns Td=5.3ns (4)
When the time being less than Td, electric current such as formula (1) is indicated, when the time being greater than Td, electric current such as formula (2) is indicated.Its
Middle Ip is derived by formula (3).Shown in time parameter such as formula (4), Time is the time coordinate in esd discharge process, and τ 1 is
ESD current rise time constant, τ 2 are ESD downslope time constant, and Td is ESD electric current downward trend sart point in time.It adjusts
Time parameter τ 1 is saved, τ 2, Td can make the curve of ESD driving source and factory's offer ESD current characteristic curve close, such as Fig. 5
It is shown.
Ireal is the current characteristic curve that factory provides.Isim be by by mathematical formulae (1) and (2) fit come
Current characteristic curve.Come as seen from Figure 5, when ESD emulation, emulator calls formula (1) and (2), can produce
Raw and truth very close to ESD driving source.
Whether current monitor (Ifail) is to flow through the electric current of ESD protective device for monitoring and reach the limit values, if reached
It then reports an error to limiting value, emulation stops, by emulating again after optimization ESD protective module design.
The maximum current that current monitor needs to provide device size and unit sizes can bear.
Whether voltage monitor (Efail) is to flow through the voltage of ESD protective device for monitoring and reach the limit values, if reached
It then reports an error to limiting value, emulation stops, by emulating again after optimization ESD design.After emulation error, ESD designer can be
Channel width is increased to 350um from 300um by the larger of NESD, NESD can bear electric current when 2000V.
Voltage monitor needs to provide the positive voltage and negative voltage that device gate-oxide can bear.After emulation error, ESD is set
Channel width can be increased to 400um from 300um, or Rvdd's and Rvss by meter personnel by the larger of NESD
Resistance reduces, until the grid oxygen voltage of N1 is lower than limiting value.
Emulation schematic diagram based on Fig. 3, complete esd protection circuit simulation flow is as shown in fig. 6, when carrying out ESD emulation:
1, determine that chip needs ESD rank to be achieved.For example need to reach the 2000V of HBM model.
2, HBM 2000V current characteristic curve is obtained from factory or customers' place.
3, by mathematical modeling, fitting HBM 2000V current characteristic curve is removed.
4, it is inserted into current monitor Ifail and voltage monitor Efail in circuit.
5, the current limit value that can bear and voltage limit of device are obtained from technique factory, and are input to corresponding electricity
It flows in monitor Ifail and voltage monitor Efail.
6, current monitor Ifail switch is opened, the electric current in ESD emulation is monitored
7, start to emulate.
If 8, current monitor Ifail electric current exceeds set limiting value, actual effect mistake is reported.Then increase ESD
After device size, emulate again.
If 9, current monitor Ifail electric current opens voltage monitor Efail without departing from set limiting value
Switch is monitored the voltage in ESD emulation.
If 10, voltage monitor Efail voltage exceeds set limiting value, actual effect mistake is reported.Then, reduce electricity
Source network resistance Rvdd and ground resistance Rvss increases power clamp NMOS tube NESD size in ESD protective module, imitates again
Very.
If 11, voltage monitor Efail voltage terminates without departing from set limiting value, emulation.
Claims (6)
1. a kind of artificial circuit of chip esd protection circuit, which is characterized in that including being connected to supply voltage VDD and public connecing
An ESD driving source between ground voltage VSS, an ESD protective module and at least one functional module；
The ESD driving source is used to load ESD voltage according to the ESD current characteristic curve of setting；
Power clamp NMOS tube NESD, the drain electrode setting of power clamp NMOS tube NESD are provided in the ESD protective module
One current monitor Ifail is connect with supply voltage VDD, and source electrode connects common ground voltage VSS；
CMOS tube N1 is provided in the functional module, between the grid and drain electrode of CMOS tube N1 and grid and source level it
Between a voltage monitor Efail is respectively set.
2. a kind of artificial circuit of chip esd protection circuit according to claim 1, which is characterized in that supply voltage VDD
Mould is protected from pad to ESD from pad to electric power network resistance Rvdd, common ground voltage VSS are arranged ESD protective module
Ground resistance Rvss is set between block.
3. a kind of artificial circuit of chip esd protection circuit according to claim 1, which is characterized in that ESD protective module
Further including capacitor C1 connects supply voltage VDD by capacitor C1 with the grid of resistance R1 power clamp NMOS tube NESD, and grid is logical
Cross resistance R1 connection common ground voltage VSS.
4. a kind of emulation mode of chip esd protection circuit, which is characterized in that include the following steps,
Step 1 determines that chip needs ESD rank to be achieved；
Step 2, the ESD current characteristic curve for obtaining determining ESD rank from factory or customers' place；
Step 3 passes through mathematical modeling, removes fitting ESD current characteristic curve；
Step 4, artificial circuit according to claim 1 to 3, are inserted into current monitor in artificial circuit
Ifail and voltage monitor Efail；
Step 5, the current limit value that can bear and voltage limit that device is obtained from technique factory, and it is input to corresponding electricity
It flows in monitor Ifail and voltage monitor Efail；
Step 6 opens current monitor Ifail switch, is monitored to the electric current in ESD emulation；
Step 7 opens ESD driving source, starts to emulate according to fitting ESD current characteristic curve；
If step 8, current monitor Ifail electric current exceed set limiting value, actual effect mistake is reported, ESD is then increased
After power clamp NMOS tube NESD size in protective module, repeats step 7 and emulate again；
If step 9, current monitor Ifail electric current open voltage monitor Efail without departing from set limiting value
Switch is monitored the voltage in ESD emulation；
If step 10, voltage monitor Efail voltage exceed set limiting value, actual effect mistake is reported, reduces power net
Network resistance Rvdd and ground resistance Rvss increases power clamp NMOS tube NESD size in ESD protective module, emulates again；
If step 11, voltage monitor Efail voltage are without departing from set limiting value, ESD protective module is effective, imitates
Really terminate.
5. a kind of emulation mode of chip esd protection circuit according to claim 4, which is characterized in that in step 1, really
Determine chip to need ESD rank to be achieved to be the HBM model of 2000V.
6. a kind of emulation mode of chip esd protection circuit according to claim 4, which is characterized in that specifically, step
By mathematical modeling in 3, removing fitting ESD current characteristic curve, specific step is as follows,
Step 3.1, description ESD current characteristics, the current characteristics for the ESD driving source being fitted are gone by mathematical formulae below
Curve；
As Time≤Td；
As Time > Td；
Wherein, Time is the time coordinate in esd discharge process,Vhbm is to determine that chip needs reach
The corresponding model voltage of ESD rank；τ 1 is the time constant that ESD electric current rises, and τ 2 is the time constant of ESD electric current decline,
Td is ESD electric current downward trend sart point in time；
Step 3.2, by regulating time parameter τ 1, τ 2 and Td the current characteristic curve for being fitted ESD driving source and factory are mentioned
It is close for ESD current characteristic curve, to obtain the fitting ESD current characteristic curve for ESD driving source.
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| CN113723041A (en) * | 2021-09-01 | 2021-11-30 | 联芸科技（杭州）有限公司 | Power supply clamping circuit insertion method and device and storage medium |
| CN113761818A (en) * | 2021-11-09 | 2021-12-07 | 微龛(广州)半导体有限公司 | ESD simulation method and simulation circuit |
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| CN113690153A (en) * | 2021-08-10 | 2021-11-23 | 深圳市华星光电半导体显示技术有限公司 | Method for preventing ESD from damaging TFT, preparation method of TFT and display panel |
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| CN113761818B (en) * | 2021-11-09 | 2022-02-11 | 微龛(广州)半导体有限公司 | ESD simulation method and simulation circuit |
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