CN103001205A - Electrostatic protection circuit applied to power supply pin - Google Patents

Abstract

The invention discloses an electrostatic protection circuit applied to a power supply pin. The circuit controls instantaneous conduction of an MOS (metal oxide semiconductor) field-effect transistor by response characteristics of an RC (resistor-capacitor) circuit to electrostatic pulse, an electrostatic discharge closed circuit to ground is closed, electrostatic discharge time can be controlled by adjusting values of RC, the electrostatic discharge closed circuit can be opened after the time to complete electrostatic discharge, and accordingly the power supply pin is protected from electrostatic damage.

Description

A kind of electrostatic discharge protective circuit that is applied to power pin

Technical field

The present invention relates generally to the ESD Circuits Design for High field, refers in particular to a kind of electrostatic discharge protective circuit that is applied to power pin.

Background technology

Integrated circuit (IC) chip must have electrostatic leakage (ESD:electrostatic discharge) problem with the interface in the external world.When the electrified body of a high potential touched the outer pin of circuit, the electrostatic leakage phenomenon will occur.Since chip each to input or output the electric capacity of pin very little, so the voltage that ESD produces is very large, the device on the possible defective chip causes chip failure.

In order to alleviate the problem of ESD, chip I/O can adopt esd protection circuit usually, normally with the external charge Clamping to VDD or GND, thereby limited the voltage that is added on the chip internal circuit.Because the circuit structure of ESD itself is different, has also introduced some serious problems in protective circuit, first esd protection circuit has reduced the matching degree of operating rate and circuit input/output port at node sizable electric capacity of introducing over the ground and between VDD; It two is that the ESD device can be with the input of the noise coupling on the VDD-to-VSS signal to circuit, thereby has affected the quality of signal; If three to be that the ESD circuit designs improper for it, may cause when electrostatic leakage, causing cmos circuit generation latch-up.

Summary of the invention

The problem to be solved in the present invention just is: the technical problem for prior art exists proposes a kind of electrostatic discharge protective circuit that is applied to power pin.

The solution that the present invention proposes is: this circuit is by the response characteristic of RC circuit to electrostatic pulse; the instantaneous conducting of control metal-oxide-semiconductor; open electrostatic leakage path over the ground; the value of regulating RC can be controlled the time t of electrostatic leakage; t after the time electrostatic leakage path can turn-off; finish electrostatic leakage, the protection power source pin is not subjected to electrostatic damage.

Description of drawings

Fig. 1 is circuit theory schematic diagram of the present invention;

Embodiment

Below with reference to accompanying drawing and implementation the present invention is described in further details.

As shown in Figure 1, suppose that static is a step signal U _s, suppose metal-oxide-semiconductor M ₁, M ₂, M ₃, M ₄Corresponding threshold voltage is respectively V _TH1, V _TH2, V _TH3And V _TH4, grid voltage is respectively V _G1, V _G2, V _G3And V _G4, then PMOS manages M ₁Grid voltage V _G1Can be expressed as

$V_{G1}\left(t\right)=U_s(1-e^{-\frac{t}{\mathrm{\τ}}})---\left(1\right)$

Wherein t represents the time, and τ is time constant, i.e. τ=R ₁C ₁According to be (1) as can be known, V _G1Along with the variation of time, namely magnitude of voltage increases gradually from 0, when the time is tending towards infinity, and V _G1=U _s, namely PMOS manages M ₁Have from being opened to the process of shutoff, its critical condition namely

U _s-V _G1(t ₁)=|V _TH1| (2)

Namely

$U_s{e}^{-\frac{t_1}{\mathrm{\τ}}}=\left|V_{\mathrm{TH}1}\right|---\left(3\right)$

Namely

$t_1=-R_1{C}_1\·\ln \frac{\left|V_{\mathrm{TH}1}\right|}{U_s}---\left(4\right)$

As time t ∈ (0, t ₁) time, PMOS manages M ₁Open, suppose that its leakage current is I _D1, because V _G1, V _G2All at temporal evolution, so I _D1Also be temporal evolution, in like manner PMOS manages M ₂Also have from being opened to the process of shutoff, if with M ₁Consider that as perfect switch then its critical condition is

U _s-V _G2(t ₂)=|V _TH2| (5)

As time t ∈ (0, t ₂) time, PMOS manages M ₂Can open bias voltage VB〉V _TH3, NMOS manages M ₃Be in conducting state always, but because M ₂Breadth length ratio (W/L) much larger than M ₃Breadth length ratio (W/L) so that this moment V _G4Be high level, NMOS pipe M4 conducting, static passes through M ₄GND releases; Behind the electrostatic leakage, i.e. t ∈ (t ₂, in the time of ∞), M ₁, M ₂Turn-off in the capital, and NMOS pipe M ₃Conducting is so that V _G4Be low level, M ₄Turn-off, ESD finishes.Occurrence that it should be noted that R, C need to be according to actual conditions and applied environment setting, and NMOS manages M ₄Size need to determine in conjunction with ESD electric current and technological parameter.

In sum, this circuit is by the response characteristic of RC circuit to electrostatic pulse, and the instantaneous conducting of control metal-oxide-semiconductor has realized electrostatic leakage, has protected power pin not to be subjected to electrostatic damage.

Claims (1)

1. electrostatic discharge protective circuit that is applied to power pin is characterized in that:

Power pin signal VDD is connected to resistance R ₁, PMOS manages M ₁Source electrode and NMOS pipe M ₄Drain electrode; Earth signal GND is connected to capacitor C ₁, capacitor C ₂, NMOS manages M ₃Source electrode and NMOS pipe M ₄Source electrode; Resistance R ₁The other end is connected to PMOS pipe M ₁Grid and capacitor C ₁An end, resistance R ₂An end be connected to PMOS pipe M ₁Drain electrode and PMOS pipe M ₂Source electrode, the other end is connected to capacitor C ₂With PMOS pipe M ₂Grid; NMOS manages M ₃Grid meets offset signal VB; NMOS manages M ₄Grid be connected to PMOS pipe M ₂With NMOS pipe M ₃Drain electrode.

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