CN104392984B

CN104392984B - A kind of electrostatic discharge protective circuit for being applied to power pin

Info

Publication number: CN104392984B
Application number: CN201410757507.1A
Authority: CN
Inventors: 蒋仁杰
Original assignee: CHANGSHA JINGJIA MICROELECTRONIC Co Ltd
Current assignee: CHANGSHA JINGJIA MICROELECTRONIC Co Ltd
Priority date: 2014-12-12
Filing date: 2014-12-12
Publication date: 2017-05-31
Anticipated expiration: 2034-12-12
Also published as: CN104392984A

Abstract

The invention discloses a kind of electrostatic discharge protective circuit for being applied to power pin.This circuit, to the response characteristic and metal-oxide-semiconductor gain characteristic quick response electrostatic of electrostatic, controls metal-oxide-semiconductor instantaneously to turn on by metal-oxide-semiconductor conducting resistance and electric capacity, opens electrostatic leakage path over the ground, completes electrostatic leakage, protects power pin not receive electrostatic damage.

Description

A kind of electrostatic discharge protective circuit for being applied to power pin

Technical field

The invention mainly relates to ESD Circuits Design for High field, a kind of electrostatic protection electricity for being applied to power pin is refered in particular to Road.

Background technology

IC chip necessarily has electrostatic leakage with the interface in the external world（ESD：electrostatic discharge） Problem.When the electrical body of a high potential touches the outer pin of circuit, electrostatic leakage phenomenon will occur.Because chip is every Individual input or the electric capacity very little of output pin, so the voltage that ESD is produced is very big, the device that may be damaged on chip causes core Piece fails.

In order to mitigate the problem of ESD, chip I/O would generally use esd protection circuit, and typically external charge is discharged pincers VDD or GND is arrived in position, so as to limit the voltage being added on chip internal circuits.Because ESD circuit structures in itself are different, Some serious problems are have also been introduced while protection circuit, one is esd protection circuit introduces phase and between VDD over the ground in node When big electric capacity, the matching degree of operating rate and circuit input/output port is reduced；The second is ESD device can be by power supply and ground Noise coupling on signal to circuit input, so as to have impact on the quality of signal；The third is if ESD circuit design is improper, can Be able to can cause to cause cmos circuit that latch-up occurs in electrostatic leakage.

The content of the invention

The problem to be solved in the present invention is that：For the technical problem that prior art is present, propose that one kind is applied to electricity The electrostatic discharge protective circuit of source capsule pin.

Solution proposed by the present invention is：This circuit passes through the response characteristic of metal-oxide-semiconductor conducting resistance and electric capacity to electrostatic And metal-oxide-semiconductor gain characteristic, control metal-oxide-semiconductor instantaneously to turn on, electrostatic leakage path over the ground is opened, complete electrostatic leakage, protection Power pin does not receive electrostatic damage.

Brief description of the drawings

Fig. 1 is circuit theory schematic diagram of the invention.

Specific embodiment

The present invention is described in further details below with reference to accompanying drawing and specific implementation.

As shown in Figure 1：

When VDD pins do not have electrostatic to attack

Phase inverter U₁Input be high level, be output as low level, then M₉Conducting；M₃、M₄、M₅、M₆、M₇、M₈Form one directly Stream biasing so that M₁₀Conducting, M₁₁It is down that is, conducting resistance is very big, it is ensured that M than pipe₁₁Drain electrode be high level, then M₀Grid It is low level, M₀Cut-off, due to M₅、M₆、M₇、M₁₁Conducting resistance it is very big, so quiescent current can be ignored；

When VDD pins are subject to positive electrostatic to attack

VDD moments uprise, M₅、M₆、M₇Forward bias voltage it is very big, conducting resistance very little, M₈Grid be pulled low, M₁₀ Grid uprise, M₁₀Cut-off, M₁₁Conducting causes M₁₅Grid step-down, M₀Grid uprise, M₀Conducting, completes electrostatic leakage, M₁₈ And M₁₉Ensureing M₀While can discharging, it is ensured that M₀Grid voltage be unlikely to too high and puncture M₀, cause tube failure；

When VDD pins are subject to negative electrostatic to attack

VDD moment step-downs, then it is now high level in logic that now the voltage of GND will be far above vdd voltage, i.e. GND； M₅、M₆、M₇Cut-off, due to electric capacity C₁The characteristic that both end voltage will not be mutated so that M₈Cut-off；M₂Conducting causes phase inverter U₁It is defeated It is high level to enter, now U₁Characteristic is no longer direction device, U₁High level is output as, then M₉Cut-off； M₁₁Grid step-down, then M₁₁Cut Only；Now M₁₇Turn on, then M₁₅Grid be high level in logic, then M₁₅Conducting, U₂、U₃Form voltage buffer, M₁₈、M₁₉ Cut-off, M₀By M₁₅Grid leak connection status is formed, electrostatic leakage path is formed, electric discharge is completed.

In sum, due to increased M₃~M₈And M₁₄So that circuit can be to the electric discharge of electrostatic quick response simultaneously, circuit Normal operating conditions can quickly be recovered, and due to increased M₁₈、M₁₉, greatly strengthen the reliability of circuit, i.e. this hair It is bright to be rapidly completed electrostatic leakage, it is reliable to protect power pin not receive electrostatic damage.

Claims

1. a kind of electrostatic discharge protective circuit for being applied to power pin, it is characterised in that：

Power pin signal VDD is connected to PMOS M₁、M₃、M₄、M₉、M₁₃Source electrode and NMOS tube M₀Drain electrode and electric capacity C₁、 C₂One end；Earth signal GND is connected to NMOS tube M₂、M₇、M₈、M₁₁、M₁₅、M₁₇、M₁₉Source electrode and PMOS M₁₆Drain electrode, PMOS M₁With NMOS tube M₂Grounded-grid, drain electrode be connected to phase inverter U₁Input, phase inverter U₁Output be connected to PMOS Pipe M₉Grid；PMOS M₃And M₄Grid and PMOS M₃Drain electrode and NMOS tube M₅Drain electrode connection, NMOS tube M₅、 M₆、M₇Grid be connected to power supply, M₅Source electrode is connected to M₆Drain electrode, M₆Source electrode be connected to M₇Drain electrode and NMOS tube M₈'s Grid and electric capacity C₁The other end；PMOS M₄Drain electrode and NMOS tube M₈Drain electrode be connected to PMOS M₁₀Grid；PMOS M₉Drain electrode and PMOS M₁₀Source electrode connection, M₁₀Drain electrode and NMOS tube M₁₁Drain electrode and NMOS tube M₁₇Drain electrode be connected to PMOS M₁₃、M₁₄Grid and NMOS tube M₁₅Grid and electric capacity C₂The other end, and M₁₁It is down than pipe；NMOS tube M₁₇'s Grounded-grid；PMOS M₁₃Drain electrode be connected to PMOS M₁₄、M₁₆Source electrode, M₁₄Drain electrode be connected to M₁₅Drain electrode and M₁₆ Grid and phase inverter U₂Input, U₂Output is connected to phase inverter U₃Input, U₃Output be connected to NMOS tube M₁₈Grid Pole and drain electrode and NMOS tube M₀Grid, NMOS tube M₁₈Source electrode be connected to NMOS tube M₁₉Grid and drain electrode.