CN101626228A - Switch circuit of ESD protection of integrated circuit chip input/output pins - Google Patents
Switch circuit of ESD protection of integrated circuit chip input/output pins Download PDFInfo
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- CN101626228A CN101626228A CN 200910304280 CN200910304280A CN101626228A CN 101626228 A CN101626228 A CN 101626228A CN 200910304280 CN200910304280 CN 200910304280 CN 200910304280 A CN200910304280 A CN 200910304280A CN 101626228 A CN101626228 A CN 101626228A
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- H01—ELECTRIC ELEMENTS
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Abstract
The invention discloses a switch circuit of ESD protection of integrated circuit chip input/output pins, which comprises a CMOS signal transmission gate, an MP1 selective switch (42) and an MN1 selective switch (43), wherein the CMOS signal transmission gate comprises an MP0 transmission tube (40) and an MN0 transmission tube (41) and is used for transmitting normal signals when the circuit works normally; the MP1 selective switch (42) and the MN1 selective switch (43) are used for switching on and off selectively; a grid and a substrate of the MP1 selective switch (42) are connected with a power supply VDD, and a source electrode of the MP1 selective switch (42) is connected with an input/output signal; a grid of the MN1 selective switch (43) is connected with an ESD detection signal, and a source electrode and a substrate of the MN1 selective switch (43) are connected with a VSS; drain electrodes of the MP1 selective switch (42) and the MN1 selective switch (43) are connected with a grid of the MP0 transmission tube (40), and a grid of the MP0 transmission tube (41) is connected with the ESD detection signal. The invention can effectively improve the reliability of the ESD protection.
Description
Technical field
The present invention relates to a kind of be used for integrated circuit (IC) chip input the switching circuit of output pin ESD protection, belong to integrated circuit fields, be used to improve the reliability of integrated circuit ESD protection.
Background technology
Natural Electrostatic Discharge phenomenon produces serious influence to the reliability of integrated circuit always.In industrial quarters, 30% of ic failure product all is owing to suffer the static discharge phenomenon caused.Therefore, the reliability of improving integrated circuit electrostatic discharge protection is to the rate of finished products that improves product and even drive whole national economy and have very important effect.
The static discharge phenomenon is divided into three kinds of discharge mode: HBM (human body discharge mode) usually according to the difference of charge source, MM (machine discharge mode), CDM (assembly charging and discharging pattern).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause the gate oxide of internal components to puncture, thereby causes circuit malfunction.Therefore, damaged by ESD, all will carry out effective ESD protection each pin of chip in order to prevent inside chip.And two main points are mainly considered in the design of ESD protective unit: the one, and the ESD electric current that the ESD protective unit can be released bigger; The 2nd, the ESD protective unit can be with the strangulation of input pin terminal voltage at electronegative potential.
In the research and development process of ESD protection, diode, GGNMOS (NMOS of grid ground connection), SCR devices such as (controllable silicons) are used as the ESD protective unit usually.Along with the development of CMOS technology, the CMOS integrated circuit has become the main flow of integrated circuit development.For the CMOS integrated circuit, the input of chip output have usually the input buffering level output buffer stage or the grid of MOS device as input.Therefore, when esd event takes place, the stress (voltage) that ESD produces can directly act on the gate oxide of MOS device, if the ESD protective unit can not in time be opened and with the input strangulation electronegative potential (being often referred to the gate oxide breakdown voltage that is lower than the MOS device), then can cause input the gate oxide generation punch-through of output MOS device, thereby cause the inefficacy of chip performance.
General local ESD protectiving scheme as shown in Figure 1.Fig. 1 by input output ESD protective unit (ESD Clamp) 10,11 and power supply clamp protective unit (Power Clamp) 13 and internal core circuit (Core) 12 form.VDD and VSS represent power line and ground wire.Input output ESD protective unit 10 be used for realizing input output pin (Input Output) protect with ESD between power line VDD, input output ESD protective unit 11 be used to realize to import ESD protection between output pin and power line VSS, power supply clamp protective unit 13 is used to realize that the ESD between power line VDD and VSS protects.Wherein import output ESD protective unit 10 and 11 can adopt protective devices such as diode commonly used, GGNMOS, SCR, power supply clamp protective unit 13 can adopt NMOS that RC triggers or DTSCR (SCR of diode triggered) etc. as protective unit.Though adopt protectiving scheme to carry out effective ESD protection to chip as Fig. 1, but because when adopting above-mentioned ESD protective device, ESD stress all act directly on chip input output, if pressure drop that back ESD electric current the produces grid oxygen puncture voltage greater than the MOS device can not in time be opened or open to the ESD protective unit on the ESD protective unit, still can cause input output MOS device generation grid oxygen punch-through.
In order to improve the reliability of ESD protection, the employing that also has input two-stage protectiving scheme as shown in Figure 2.This scheme is by the elementary protective unit of input (PrimaryClamp) 20,22, secondary protective unit (Secondary Clamp) 21,23, and current-limiting resistance 26 and power supply clamp protective unit 13 are formed.12 is internal core circuit (Core).The elementary protective unit 20 of input, current-limiting resistance 26 and secondary protective unit 21 are used to realize that the ESD between input and power line VDD protects.The elementary protective unit 22 of input, current-limiting resistance 26 and secondary protective unit 23 are used to realize that the ESD between input and power line VSS protects.Power supply clamp protective unit 13 is used to realize that the ESD between power line VDD and VSS protects.General secondary protective unit 21 or 23 trigger voltage (cut-in voltage of ESD protective unit) are lower, and elementary protective unit 20 or 22 trigger voltage are higher.When esd event takes place when, secondary the protective unit 21 or 23 ESD electric current of opening earlier and release, when the pressure drop that produces on current-limiting resistance 26 and secondary protective unit 21 or 23 when the ESD electric current reaches the trigger voltage of elementary protective unit 20 or 22, elementary protective unit 20 or 22 is opened and the most ESD electric current of releasing, and fraction ESD electric current is released from secondary protective unit 21 or 23.The current potential of grid can be reduced by the dividing potential drop effect of current-limiting resistance 26, thereby the grid oxygen of input MOS device can be effectively protected.The shortcoming of this kind protectiving scheme is if current-limiting resistance 26 is bigger, then can cause the trigger voltage of secondary protective unit 21 or 23 to raise, if current-limiting resistance 26 is less, the dividing potential drop effect of current-limiting resistance 26 then can be not obvious, when the ESD electric current of flow through secondary protective unit 21 or 23 is big, the pressure drop that the ESD electric current produces on secondary protective unit 21 or 23 still may surpass the puncture voltage of the gate oxide of MOS device, thereby causes gate oxide generation punch-through.
All there is following shortcoming in above-mentioned two kinds of protectiving schemes: the first, and ESD stress directly acts on the internal core device; The second, when the ESD electric current was big, the pressure drop that the ESD electric current produces on the ESD protective unit still can cause the gate oxide of MOS device to puncture; The 3rd, when the chip input signal is not the grid (acting on the source electrode or the drain electrode of MOS device) that acts on the MOS device, and there is parasitic low impedance path in the internal core circuit, and then the ESD electric current can flow into the internal core circuit, thereby causes the internal core circuit to damage.
Summary of the invention
The technical problem to be solved in the present invention is: provide a kind of be used for integrated circuit (IC) chip input the switching circuit of output pin ESD protection, directly act on the internal core device to overcome the ESD stress that prior art exists, and when the ESD electric current is big, the pressure drop that the ESD electric current produces on the ESD protective unit causes the gate oxide of MOS device to puncture, even the deficiency that causes the internal core circuit to damage.
The technical scheme that the technical problem that the present invention solves is taked is: the input of chip a switching circuit is set between pad and the internal core circuit of output pin, and utilize the ESD detection signal of esd detection circuit to decide unlatching or stopcock circuit.This ESD switching circuit mainly consists of the following components: MP0 transfer tube 40 and MN0 transfer tube 41 constitute the cmos signal transmission gate; MP1 selective switch 42 and MN1 selective switch 43 are used for optionally opening and shutting off.The grid of MP1 selective switch 42 and substrate meet power vd D, source electrode connect the input output signal; The grid of MN1 selective switch 43 connects the ESD detection signal, and source electrode and substrate meet VSS; The drain electrode of MP1 selective switch 42 and MN1 selective switch 43 connects the grid of MP0 transfer tube 40, and the grid of MN0 transfer tube 41 connects the ESD detection signal.
When the circuit operate as normal, because the grid of MP1 selective switch 42 meets power vd D, the potential difference V between MP1 selective switch 42 source electrode this moment (signal input output) and grid
SGThreshold voltage V less than MP1 selective switch 42
ThpAbsolute value, thereby MP1 selective switch 42 turn-offs; And when the circuit operate as normal, the ESD detection signal is a high level, MN0 transfer tube 41 is opened and harmless transmission low level signal, the grid of MP0 transfer tube 40 is opened and power ground VSS signal is transferred to MN1 selective switch 43 simultaneously, thereby MP0 transfer tube 40 is opened and harmless transmission high level signal, and the cmos signal transmission gate that this moment, MP0 transfer tube 40 and MN0 transfer tube 41 constituted can realize that when the circuit operate as normal power line VSS transmits to the full swing between VDD; When esd event takes place when, the ESD detection signal is a low level, this moment, MN0 transfer tube 41 and MN1 selective switch 43 turn-offed, because the voltage that esd event produces will be higher than the voltage on the power line VDD far away, therefore, MP1 selective switch 42 is opened, and with the grid of ESD voltage transmission to MP0 transfer tube 40, MP0 transfer tube 40 source potential this moment (signal input output) equates with grid potential, i.e. the source grid potential difference V of MP0 transfer tube 40
SGThreshold voltage V less than MP0 transfer tube 40
ThpAbsolute value, thereby MP0 transfer tube 40 turn-offs; Therefore, when esd event took place, MP0 transfer tube 40 and MN0 transfer tube 41 can turn-off the ESD electric current, thereby prevented that the ESD electric current from flowing into inside chip and making the input terminal voltage of inside chip be in lower current potential.
Beneficial effect of the present invention: by the realization of above-mentioned ESD switching circuit, can overcome the deficiency of ESD protectiving scheme in the past, can prevent effectively that ESD stress from directly acting on inside chip and the ESD electric current flows into inside chip, thereby realize the reliable ESD protection of inner core circuit.
Description of drawings
Fig. 1 is the integrated circuit input output pin ESD protectiving scheme schematic diagram of prior art;
Fig. 2 is the another kind of integrated circuit input output pin ESD protectiving scheme schematic diagram of prior art;
Fig. 3 is for having adopted integrated circuit input output pin ESD protectiving scheme schematic diagram of the present invention;
Fig. 4 is an ESD switching circuit schematic diagram of the present invention.
Fig. 5 is esd detection circuit commonly used.
Embodiment
Embodiments of the invention: adopted integrated circuit input output pin ESD protectiving scheme of the present invention as schematically shown in Figure 3, this scheme is by ESD protective unit (ESDClamp) 10 and 11, power supply clamp units (Power Clamp) 13, ESD switching circuit 30 (switching circuit of the present invention) and esd detection circuit 31 are formed.Wherein ESD protective unit 10 be used for realizing input output pin (Input Output) protect with ESD between power line VDD; ESD protective unit 11 be used to realize to import ESD protection between output pin and power line VSS; Power supply clamp units (Power Clamp) 13 is used to realize that the ESD between power line VDD and VSS protects.ESD protective unit 10 and 11 safeguard function also can be realized (utilizing wherein parasitic diode as the ESD protective unit) by ESD switching circuit 30, be that ESD switching circuit 30 had both played the transmission normal signal or disconnected the ESD signal, work the ESD electric current of releasing again, parasitic diode and power supply clamp units (Power Clamp) 13 can constitute full chip protection in the ESD switching circuit 30 at this moment; ESD protective unit 10 and 11 also can adopt independently unit with ESD switching circuit 30, ESD protective unit 10 and 11 can adopt common ESD protective unit (as SCR at this moment, diode, GGNMOS etc.), the effect of most ESD electric current of promptly releasing is finished by ESD protective unit 10 and 11, and constitutes full chip protection with power supply clamp units (Power Clamp) 13.The esd detection circuit (as shown in Figure 5) that esd detection circuit 31 can adopt RC network commonly used to constitute.The power supply clamp units that power supply clamp units (Power Clamp) 13 can adopt NMOS that RC triggers or PMOS, DTSCR (SCR of diode triggered) etc. to use always the ESD electric current between power line VDD and VSS of releasing.
When the circuit operate as normal, because the grid of MP1 selective switch 42 meets power vd D, the potential difference V between MP1 selective switch 42 source electrode this moment (signal input output) and grid
SGLess than MP1 selective switch 4) threshold voltage V
ThpAbsolute value, thereby MP1 selective switch 42 turn-offs; And when the circuit operate as normal, the ESD detection signal is a high level, MN0 transfer tube 41 is opened and harmless transmission low level signal, the grid of MP0 transfer tube 40 is opened and power ground VSS signal is transferred to MN1 selective switch 43 simultaneously, thereby MP0 transfer tube 40 is opened and harmless transmission high level signal, and the cmos signal transmission gate that this moment, MP0 transfer tube 40 and MN0 transfer tube 41 constituted can realize that when the circuit operate as normal power line VSS transmits to the full swing between VDD; When esd event takes place when, the ESD detection signal is a low level, this moment, MN0 transfer tube 41 and MN1 selective switch 43 all turn-offed, because the voltage that esd event produces will be higher than the voltage on the power line VDD far away, therefore, MP1 selective switch 42 is opened, and with the grid of ESD voltage transmission to MP0 transfer tube 40, MP0 transfer tube 40 source potential this moment (signal input output) equates with grid potential, i.e. the source grid potential difference V of MP0 transfer tube 40
SGThreshold voltage V less than MP0 transfer tube 40
ThpAbsolute value, thereby MP0 transfer tube 40 turn-offs; Therefore, when esd event took place, MP0 transfer tube 40 and MN0 transfer tube 41 can turn-off the ESD electric current, thereby prevented that the ESD electric current from flowing into inside chip and making the input terminal voltage of inside chip be in lower current potential.
Claims (2)
1. a switching circuit that is used for integrated circuit (IC) chip input output pin ESD protection is characterized in that: MP0 transfer tube (40) and MN0 transfer tube (41) formation cmos signal transmission gate, transmission normal signal when being used for the circuit operate as normal; MP1 selective switch (42) and MN1 selective switch (43) are used for optionally opening and shutting off.
2. according to claim 1 be used for integrated circuit (IC) chip input the switching circuit of output pin ESD protection, it is characterized in that: the grid and the substrate of MP1 selective switch (42) meet power vd D, source electrode connect input output signal; The grid of MN1 selective switch (43) connects the ESD detection signal, and source electrode and substrate meet VSS; The drain electrode of MP1 selective switch (42) and MN1 selective switch (43) connects the grid of MP0 transfer tube (40), and the grid of MN0 transfer tube (41) connects the ESD detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910304280 CN101626228B (en) | 2009-07-13 | 2009-07-13 | Switch circuit of ESD protection of integrated circuit chip input/output pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910304280 CN101626228B (en) | 2009-07-13 | 2009-07-13 | Switch circuit of ESD protection of integrated circuit chip input/output pins |
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| CN101626228A true CN101626228A (en) | 2010-01-13 |
| CN101626228B CN101626228B (en) | 2012-08-08 |
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| CN 200910304280 Expired - Fee Related CN101626228B (en) | 2009-07-13 | 2009-07-13 | Switch circuit of ESD protection of integrated circuit chip input/output pins |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102255304A (en) * | 2011-07-19 | 2011-11-23 | 北京大学 | ESD (Electro Spark Detector) power clamping circuit |
| CN103036220A (en) * | 2012-04-28 | 2013-04-10 | 上海华虹Nec电子有限公司 | Electro spark detector (ESD) circuit protection structure |
| CN103683235A (en) * | 2012-09-24 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | Electrostatic discharge self-protection circuit |
| CN103795026A (en) * | 2014-02-28 | 2014-05-14 | 北京大学 | Input stage esd protection circuit |
| CN104465651A (en) * | 2014-11-28 | 2015-03-25 | 中国科学院上海微系统与信息技术研究所 | SOI ESD two-stage protection network |
| CN104483585A (en) * | 2014-12-31 | 2015-04-01 | 工业和信息化部电子第五研究所 | Automatic transmission line pulse testing system |
| CN104578035A (en) * | 2015-01-26 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | ESD protection circuit based on bidirectional I/O buffer |
| CN108028530A (en) * | 2016-07-12 | 2018-05-11 | 深圳市汇顶科技股份有限公司 | ESD detection devices, integrated circuit and method applied to digital integrated electronic circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330208B (en) * | 2007-06-21 | 2010-10-13 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
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2009
- 2009-07-13 CN CN 200910304280 patent/CN101626228B/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102255304B (en) * | 2011-07-19 | 2013-09-11 | 北京大学 | ESD (Electro Spark Detector) power clamping circuit |
| CN102255304A (en) * | 2011-07-19 | 2011-11-23 | 北京大学 | ESD (Electro Spark Detector) power clamping circuit |
| CN103036220B (en) * | 2012-04-28 | 2015-04-08 | 上海华虹宏力半导体制造有限公司 | Electro spark detector (ESD) circuit protection structure |
| CN103036220A (en) * | 2012-04-28 | 2013-04-10 | 上海华虹Nec电子有限公司 | Electro spark detector (ESD) circuit protection structure |
| CN103683235A (en) * | 2012-09-24 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | Electrostatic discharge self-protection circuit |
| CN103795026B (en) * | 2014-02-28 | 2016-08-17 | 北京大学 | Input stage esd protection circuit |
| CN103795026A (en) * | 2014-02-28 | 2014-05-14 | 北京大学 | Input stage esd protection circuit |
| CN104465651A (en) * | 2014-11-28 | 2015-03-25 | 中国科学院上海微系统与信息技术研究所 | SOI ESD two-stage protection network |
| CN104465651B (en) * | 2014-11-28 | 2017-06-16 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI ESD two class protection networks |
| CN104483585A (en) * | 2014-12-31 | 2015-04-01 | 工业和信息化部电子第五研究所 | Automatic transmission line pulse testing system |
| CN104483585B (en) * | 2014-12-31 | 2017-06-13 | 工业和信息化部电子第五研究所 | Transfermatic pulse test system |
| CN104578035A (en) * | 2015-01-26 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | ESD protection circuit based on bidirectional I/O buffer |
| CN104578035B (en) * | 2015-01-26 | 2017-09-15 | 浪潮电子信息产业股份有限公司 | A kind of esd protection circuit buffered based on two-way I/O |
| CN108028530A (en) * | 2016-07-12 | 2018-05-11 | 深圳市汇顶科技股份有限公司 | ESD detection devices, integrated circuit and method applied to digital integrated electronic circuit |
| US10359460B2 (en) | 2016-07-12 | 2019-07-23 | Shenzhen GOODIX Technology Co., Ltd. | ESD detection apparatus and method applied to digital integrated circuit, and integrated circuit |
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| Publication number | Publication date |
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| CN101626228B (en) | 2012-08-08 |
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