CN108565848A

CN108565848A - A kind of electrostatic discharge protective circuit in Internet of Things

Info

Publication number: CN108565848A
Application number: CN201810515796.2A
Authority: CN
Inventors: 陈磊
Original assignee: Danyang Constant Core Electronics Co Ltd
Current assignee: Danyang Constant Core Electronics Co Ltd
Priority date: 2018-05-26
Filing date: 2018-05-26
Publication date: 2018-09-21

Abstract

The invention discloses the electrostatic discharge protective circuits in a kind of Internet of Things, including：One protective circuit of diode, a detection circuit, a buffer circuit, a delay circuit, a leadage circuit.Delay circuit therein is composed of a PMOS tube and a NMOS tube.When chip works normally, electrostatic discharge protective circuit does not work, and when electrostatic event occurs, the present invention, which can generate the longer time, allows bleeder pipe static electricity discharge electric current, so that chip is with better antistatic property.

Description

A kind of electrostatic discharge protective circuit in Internet of Things

Technical field

The present invention relates to electrostatic protection fields, more particularly to a kind of power clamp electrostatic discharge protective circuit.

Background technology

In recent years with the fast development of integrated circuit technology, the line width of metal-oxide-semiconductor is more and more narrow, and junction depth is more and more shallow, grid The thickness of oxygen layer is also more and more thinner, these all accelerate circuit design to electrostatic protection（ESD, Electro-Static discharge）Demand.When line width is 1 μm, influence very little of the esd event to circuit, when entering 0.18 μm, 0.13 μm Generation, especially 90 nanometer or less epoch, ESD become very urgent problem.In the application of various Internet of Things chips, it is required for Corresponding electrostatic discharge protective circuit.

General ESD points are HBM（Human body model Human Body Models）Pattern, MM（Machine model machines Pattern）Pattern and CDM（Charged device model band power modes）Pattern.HBM and MM patterns are external to chip progress Electric discharge, the esd protection circuit for relying solely on input/output port is far from being enough, it is also necessary to add ESD between power supply and ground Protect circuit（Power clamp ESD circuit）, so as to more quick leakage current, to ensure the ESD performances of entire chip.

It is shown in Figure 1, existing power clamp ESD circuit.

Detection circuit is made of resistance R1 and capacitance C1, and RC delay times decide the time of leakage current, when delay Between it is bigger, the leakage current time is also more.The detection circuit is for detecting esd pulse, the correct esd pulse and normal distinguished Power supply electrifying pulse.When power supply normally powers on, detection circuit will ensure that power clamp ESD circuit is not turned on, when generation ESD things When part, detection circuit wants that esd pulse can be quickly detected, and power clamp ESD circuit is guided to work, thus leakage current, Protect chip internal circuits.

Buffer circuit, the phase inverter INV1~INV3 being connected in series with by three are formed, and are used for the output of amplification detection circuit, Driving capability is provided to leadage circuit, to drive bleeder pipe to work.

Leadage circuit is made of NMOS transistor NM1, for the ESD electric currents, when an esd event occurs, vent discharge of releasing Road can normally open ESD electric currents of releasing；When circuit works normally, leadage circuit is to close.When since esd event occurs, Electric current is all order of amps, and the NMOS transistor size of leadage circuit is all larger.

When esd event occurs at chip pin, ESD voltage or electric current are left to by D1 on VDD, are then passed through again NM1 pipes are come ESD electric currents of releasing.Grid voltage on NM1 pipes is exactly vdd voltage, the voltage lower than the voltage at chip pin place one A diode drop.

The time that power supply normally powers on is generally 1ms or so, and occur esd event time be tens nanosecond rank.Inspection Slowdown monitoring circuit not only will correctly distinguish esd pulse and normal power supply electrifying pulse, also increase delay time as possible, to increase It releases time of ESD electric currents.Detection circuit in Fig. 1 is designed with RC circuits into line delay, if the RC times are longer, leakage current Effect can be more preferable.For structure in Fig. 1 when releasing ESD electric currents, the voltage of grid is exactly VDD on NM1 pipes, and the voltage is higher, lets out Discharge stream also can be faster.

Invention content

The technical problem to be solved in the present invention is to provide a kind of electrostatic discharge protective circuits, when chip normally powers on, it is ensured that ESD circuit is closed, will not the work of false triggering ESD circuit, it is when an esd event occurs, as far as possible again to release more ESD electric currents, to protect the internal components of circuit without damage.

In order to solve the above technical problems, the present invention is achieved by the following technical solutions：

One protective circuit of diode is made of the first diode D1 and the second diode D2, for providing drain passageway；

One detection circuit is made of first resistor R1 and the first capacitance C1, for detecting whether electrostatic event occurs；

One buffer circuit is made of the first phase inverter INV1 and the second phase inverter INV2, for providing driving to bleeder pipe；

One delay circuit is made of, the time for increasing static electricity discharge electric current third NMOS tube NM3 and third PMOS tube PM3；

One leadage circuit is made of the second NMOS transistor NM2, for main electrostatic induced current of releasing.

The protective circuit of diode, chip pin end, the drain electrode of PM2 pipes, the anode of diode D1, diode D2 it is negative The input terminal of pole and internal circuit links together, which is labeled as VA points, and the cathode of diode D1 is connected with VDD, diode The anode of D2 is connected with ground.

The detection circuit, the first capacitance C1 and first resistor R1 series connection, output of the concatenated point as detection circuit End, the point are labeled as VD, and the other end and ground of capacitance C1 connect, and the other end of resistance R1 is connected with power vd D.

The input terminal of the buffer circuit, the output end of detection circuit and the first phase inverter INV1 are connected together, the The input terminal of the output end of one phase inverter INV1 and the second phase inverter INV2 connect, the output end of INV2, the grid of PM1 pipes and The grid of NM1 pipes is connected together, which is labeled as VB, and the drain electrode of PM1 pipes is connected with the drain electrode of NM1 pipes, the source of PM1 pipes Pole connects VDD, the source electrode ground connection of NM1 pipes.

The delay circuit, the grids of NM3 pipes meet VDD, and the drain electrode of NM3 pipes connects the drain electrode of PM1 pipes, the source electrode of NM3 pipes, The drain electrode of PM3 pipes is connected with the grid of NM2 pipes, which is labeled as VC points, and the source electrode of PM3 pipes connects VA points, and the grid of PM3 pipes meets VD Point.

The leadage circuit, the second NMOS tube NM2 source electrodes and ground connect, and the drain electrode of NM2 pipes is connected with VDD, the grid of NM2 pipes Pole is connected to VC points.

The present invention has the following advantages compared with existing electrostatic discharge protective circuit：

When an esd event occurs, bleeder pipe can be allowed there are more times come static electricity discharge electric current by delay circuit, allows electrostatic Current drain more fully, therefore can preferably protect internal components.

Description of the drawings

Fig. 1 is existing electrostatic discharge protective circuit schematic diagram；

Fig. 2 is the one embodiment schematic diagram of electrostatic discharge protective circuit of the present invention.

Specific implementation mode

The present invention is described in further detail with specific implementation mode below in conjunction with the accompanying drawings：

It is shown in Figure 2, in the following embodiments, electrostatic discharge protective circuit of the present invention, including：

One protective circuit of diode is made of the first diode D1 and the second diode D2；One detection circuit, by first resistor R1 With the first capacitance C1 compositions；One buffer circuit is made of the first phase inverter INV1 and the second phase inverter INV2；One delay circuit, It is made of third PMOS tube PM3 and third NMOS tube NM3；One leadage circuit is made of third NMOS transistor NM2.

The detection circuit of resistance R1 and capacitance C1 compositions, such as it is 150ns or so, general ESD to design its RC delay time The time of origin of event is all tens ns ranks, and when an esd event occurs, detection circuit can be detected correctly, when When chip normally powers on, and will not false triggering.

When chip normally powers on, the output end of detection circuit is high level, and the output end of phase inverter INV2 is exactly high The drain electrode of level, PM1 pipes is low level, and NM3 pipes are conductings at this time, therefore VC point voltages are also low level, at bleeder pipe NM2 In closed state.Although the voltage of VA points can be transferred to VC by PM3 pipes, it can also be released to ground quickly, VC points are still tieed up It holds in low level.

It waits when an esd event occurs, the output end of detection circuit is low level, and the output end of phase inverter INV1 is exactly high electricity Flat, then the output end VB points of phase inverter INV2 are exactly low level, PM1 pipes are conductings, and vdd voltage is just transmitted by NM3 pipes To VC points, NM2 pipes start leakage current.

It waits when an esd event occurs, the output end VD of detection circuit is low level, and PM3 is connected at this time, by the voltage of VA points It is transferred to VC points, NM2 equally can be with leakage current, since there are the delays of certain time can just become from zero level for the voltage of VD points For high level, just there are more times to be on conducting state then PM3 is managed.Since the voltage of VD points passes through two-stage reverse phase Device has arrived certain voltage threshold, and phase inverter output can just be overturn, and the conducting of PM3 pipes is directly controlled by grid voltage VD, place It is longer in the time of relative low voltage, so that the time that the time that PM1 pipes are on does not have PM3 pipes to be connected is long, also It is that the presence of PM3 pipes makes NM2 pipes have the more fully time to carry out leakage current.

Analog simulation being carried out using smic 0.13um techniques, under equal conditions, it is assumed that the ESD voltage of moment is 20V, The time of releasing of the circuit of background technology, NM2 pipes is 230ns, and in the circuit of the present invention, the time of releasing of bleeder pipe is 850ns, from the point of view of simulation comparison result, the present invention has the time of longer static electricity discharge electric current.

Although the present invention is illustrated using specific embodiment, the present invention's is not intended to limit to the explanation of embodiment Range.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention In the case of, it is easy to carry out various modifications or embodiment can be combined.

Claims

1. the electrostatic discharge protective circuit in a kind of Internet of Things, which is characterized in that including：

2. a kind of electrostatic discharge protective circuit as described in claim 1, which is characterized in that the protective circuit of diode, chip draw Foot, the anode of diode D1, the cathode of diode D2 and internal circuit input terminal link together, which is labeled as VA The cathode of point, diode D1 is connected with VDD, and the anode of diode D2 is connected with ground.

3. a kind of electrostatic discharge protective circuit as described in claim 1, which is characterized in that the detection circuit, the first capacitance C1 Connect with first resistor R1, concatenated output end of the point as detection circuit, the point is labeled as VD, the other end of capacitance C1 with Ground connects, and the other end of resistance R1 is connected with power vd D.

4. a kind of electrostatic discharge protective circuit as described in claim 1, which is characterized in that the buffer circuit, detection circuit it is defeated The input terminal of outlet and the first phase inverter INV1 are connected together, the output end and the second phase inverter INV2 of the first phase inverter INV1 Input terminal connection, the grid of the output end of INV2, the grid of PM1 pipes and NM1 pipes is connected together, which is labeled as VB, The drain electrode of PM1 pipes is connected with the drain electrode of NM1 pipes, and the source electrode of PM1 pipes connects VDD, the source electrode ground connection of NM1 pipes.

5. a kind of electrostatic discharge protective circuit as described in claim 1, which is characterized in that the grid of the delay circuit, NM3 pipes connects The drain electrode of VDD, NM3 pipe connects the drain electrode of PM1 pipes, and the drain electrode of the source electrode, PM3 pipes of NM3 pipes is connected with the grid of NM2 pipes, the point mark VC points are denoted as, the source electrode of PM3 pipes connects VA points, and the grid of PM3 pipes connects VD points.

6. a kind of electrostatic discharge protective circuit as described in claim 1, which is characterized in that the leadage circuit, the second NMOS tube NM2 Source electrode and ground connect, and the drain electrode of NM2 pipes is connected with VDD, and the grid of NM2 pipes is connected to VC points.