CN105630054A - Hysteresis voltage comparator - Google Patents
Hysteresis voltage comparator Download PDFInfo
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- CN105630054A CN105630054A CN201410612343.3A CN201410612343A CN105630054A CN 105630054 A CN105630054 A CN 105630054A CN 201410612343 A CN201410612343 A CN 201410612343A CN 105630054 A CN105630054 A CN 105630054A
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- pmos
- nmos tube
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Abstract
The invention discloses a hysteresis voltage comparator. The hysteresis voltage comparator comprises a first PMOS (P-channel metal oxide semiconductor) transistor and a second PMOS transistor, two grids are used for inputting a pair of differential signals, and drains are connected with a first load MOS (metal oxide semiconductor) transistor and a second load MOS transistor respectively; a third PMOS transistor and a first NMOS (N-channel metal oxide semiconductor) transistor have mirror-image relationships with current of the first load MOS transistor and the second load MOS transistor respectively; drains of the third PMOS transistor and the first NMOS transistor are connected together to form a first output end; the first output end is sequentially connected with a first CMOS (complementary metal oxide semiconductor) inverter and a second CMOS inverter, and a second output end and a third output end are formed respectively; a fourth PMOS switch transistor is connected between a second current source and the drain of the first PMOS transistor, and the grid is connected with the second output end; a fifth PMOS switch transistor is connected between a third current source and the drain of the second PMOS transistor, and the grid is connected with the third output end. According to the hysteresis voltage comparator, threshold voltage adjustment can be realized by adopting a switching circuit, integration is facilitated, the hysteresis width is convenient to adjust, and the application is convenient.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of hysteresis voltage comparator.
Background technology
Two level can be compared and export high level or low level by voltage comparator, so voltage comparator is generally used for level detection. Single voltage limit comparator only one of which threshold voltage, then exports high level more than incoming level more than this threshold voltage, otherwise output low level. The advantage of this single voltage limit comparator is simple in construction, but if having more noise in the environment of input signal, the output of single voltage limit comparator can be beated frequently between low and high level, and voltage detecting there will be problem. As shown in Figure 1A, it is that existing single voltage limit comparator is at the input inputted when signal has more noise and curve of output; Single voltage limit comparator only one of which threshold V T RP, input signal, when near threshold voltage, can make output signal frequently beat after being superimposed with noise signal.
In order to eliminate the noise impact on output signal, prior art is it is generally required to use hysteresis voltage comparator, different with single voltage limit comparator, hysteresis voltage comparator has two threshold voltages, output threshold voltage from low transition to high level is with to jump to low level threshold voltage from high level different, the two forms a sluggish interval, it is possible to avoid effect of noise. As shown in Figure 1B, it is that existing hysteresis voltage comparator is at the input inputted when signal has more noise and curve of output; Can be seen that threshold V T RP+ is greater than threshold V T RP-, both differences are greater than the excursion of noise, therefore can eliminate effect of noise.
Existing hysteresis voltage comparator connects formation positive feedback typically via non-essential resistance and forms two different threshold voltages, is unfavorable for integrated, and range of application is limited.
Summary of the invention
The technical problem to be solved is to provide a kind of hysteresis voltage comparator, on-off circuit can be adopted to realize threshold voltage adjustments, not only utilize integrated, and sluggish width adjusting is convenient, and application is convenient.
For solving above-mentioned technical problem, hysteresis voltage comparator provided by the invention includes:
First PMOS and the second PMOS, the source electrode of described first PMOS and described second PMOS links together and connects with the first current source; The grid of described first PMOS and described second PMOS is as the input of a pair differential signal.
The drain electrode of described first PMOS and the first load metal-oxide-semiconductor connect, and the drain electrode of described second PMOS and the second load metal-oxide-semiconductor connect.
3rd PMOS and the first NMOS tube, the electric current of described 3rd PMOS and described first load metal-oxide-semiconductor is mirror image relationship, and the electric current of described first NMOS tube and described second load metal-oxide-semiconductor is mirror image relationship; The drain electrode of described 3rd PMOS and the drain electrode of described first NMOS tube link together and as the first outfan, and the source electrode of described 3rd PMOS connects supply voltage, the source ground of described first NMOS tube.
First CMOS inverter and the second CMOS inverter, the input of described first CMOS inverter connects described first outfan, and the outfan of described first CMOS inverter is the second outfan; The input of described second CMOS inverter connects described second outfan, and the outfan of described second CMOS inverter is the 3rd outfan.
4th PMOS switch pipe is connected between the drain electrode of the second current source and described first PMOS, and the grid of described 4th PMOS switch pipe connects described second outfan.
5th PMOS switch pipe is connected between the drain electrode of the 3rd current source and described second PMOS, and the grid of described 5th PMOS switch pipe connects described 3rd outfan.
Described 4th PMOS switch pipe is opened when described first outfan output high level and increases the electric current of described first load metal-oxide-semiconductor and form positive feedback structure, and the electric current being input in described first load metal-oxide-semiconductor by regulating described 4th PMOS switch pipe regulates the output voltage of hysteresis voltage comparator by the first threshold voltage of high step-down.
Described 5th PMOS switch pipe is opened when described first outfan output low level and increases the electric current of described second load metal-oxide-semiconductor and form positive feedback structure, and the electric current being input in described second load metal-oxide-semiconductor by regulating described 5th PMOS switch pipe regulates the output voltage of described hysteresis voltage comparator by the low Second Threshold voltage uprised.
Further improving is that described first load metal-oxide-semiconductor includes the second NMOS tube, the 3rd NMOS tube and the 6th PMOS; The drain electrode of described second NMOS tube connects with the drain electrode of described first PMOS, the source ground of described second NMOS tube; The grid of described 3rd NMOS tube connects grid and drain electrode, the source ground of described 3rd NMOS tube of described second NMOS tube; The drain and gate of described 6th PMOS connects the drain electrode of described 3rd NMOS tube and the grid of described 3rd PMOS, and the source electrode of described 6th PMOS connects supply voltage.
Further improving and be, described second load metal-oxide-semiconductor includes the 4th NMOS tube, the grid of described 4th NMOS tube and drain electrode and connects the drain electrode of described second PMOS and the grid of described first NMOS tube, the source ground of described 4th NMOS tube.
Further improving and be, described second current source and described 3rd current source are for adopting same current source.
The present invention is controlled MOS switch pipe by exporting signal and is input to the load current size of corresponding differential input transistor by MOS switch management and control system, positive feedback can be formed and regulate two threshold voltage sizes that the output voltage of hysteresis voltage comparator changes, and can easily condition sluggishness width, the present invention need not adopt resistance but adopt on-off circuit to can be achieved with threshold voltage adjustments, not only utilize integrated, and sluggishness width adjusting is convenient, application is convenient and cost is low.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Figure 1A is that existing single voltage limit comparator is at the input inputted when signal has more noise and curve of output;
Figure 1B is that existing hysteresis voltage comparator is at the input inputted when signal has more noise and curve of output;
Fig. 2 is embodiment of the present invention hysteresis voltage comparator circuit diagram;
Fig. 3 is present pre-ferred embodiments hysteresis voltage comparator circuit diagram;
Fig. 4 A is input during present pre-ferred embodiments removal switch-mode regulation threshold voltage and Output simulation curve;
Fig. 4 B is input and the Output simulation curve of present pre-ferred embodiments.
Detailed description of the invention
As in figure 2 it is shown, be embodiment of the present invention hysteresis voltage comparator circuit diagram; Embodiment of the present invention hysteresis voltage comparator includes:
First PMOS MP1 and the second PMOS MP2, the source electrode of described first PMOS MP1 and described second PMOS MP2 links together and connects with the first current source I1; The grid of described first PMOS MP1 and described second PMOS MP2 is as the input of a pair differential signal Vinn and Vinp.
Drain electrode and the first load metal-oxide-semiconductor 1 of described first PMOS MP1 connect, and drain electrode and the second load metal-oxide-semiconductor 2 of described second PMOS MP2 connect.
3rd PMOS MP3 and the first NMOS tube MN1, the electric current of described 3rd PMOS MP3 and described first load metal-oxide-semiconductor 1 is mirror image relationship, and the electric current of described first NMOS tube MN1 and described second load metal-oxide-semiconductor 2 is mirror image relationship; The drain electrode of described 3rd PMOS MP3 and the drain electrode of described first NMOS tube MN1 link together and as the first output end vo ut1, and the source electrode of described 3rd PMOS MP3 meets supply voltage VDD, the source ground GND of described first NMOS tube MN1.
First CMOS inverter 3 and the second CMOS inverter 4, the input of described first CMOS inverter 3 connects described first output end vo ut1, and the outfan of described first CMOS inverter 3 is the second output end vo ut2; The input of described second CMOS inverter 4 connects described second output end vo ut2, and the outfan of described second CMOS inverter 4 is the 3rd output end vo ut3.
4th PMOS switch pipe MP4 is connected between the drain electrode of the second current source I2 and described first PMOS MP1, and the grid of described 4th PMOS switch pipe MP4 connects described second output end vo ut2.
5th PMOS switch pipe MP5 is connected between the drain electrode of the 3rd current source I2 and described second PMOS MP2, and the grid of described 5th PMOS switch pipe MP5 connects described 3rd output end vo ut3. Second current source I2 described in the embodiment of the present invention and described 3rd current source I2 adopts same current source.
Described 4th PMOS switch pipe MP4 opens when described first output end vo ut1 exports high level and increases the electric current of described first load metal-oxide-semiconductor 1 and form positive feedback structure, namely the electric current of described first load metal-oxide-semiconductor 1 increase after can be mirrored to described 3rd PMOS MP3 and make the electric current of described 3rd PMOS MP3 increase, make described first output end vo ut1 be more prone to reach or remain high level, form the relation of a positive feedback; The output voltage of hysteresis voltage comparator is regulated by the first threshold voltage of high step-down by regulating the described 4th PMOS switch pipe MP4 electric current being input in described first load metal-oxide-semiconductor 1, in the embodiment of the present invention, it is more many that electric current in described first load metal-oxide-semiconductor 1 increases, and first threshold voltage can be more little.
Described 5th PMOS switch pipe MP5 opens when described first output end vo ut1 output low level and increases the electric current of described second load metal-oxide-semiconductor 2 and form positive feedback structure, namely the electric current of described second load metal-oxide-semiconductor 2 increase after can be mirrored to described first NMOS tube MN1 and make the electric current of described first NMOS tube MN1 increase, make described first output end vo ut1 be more prone to reach or remain low level, form the relation of a positive feedback; The output voltage of described hysteresis voltage comparator is regulated by the low Second Threshold voltage uprised by regulating the described 5th PMOS switch pipe MP5 electric current being input in described second load metal-oxide-semiconductor 2; In the embodiment of the present invention, it is more many that the electric current in described second load metal-oxide-semiconductor 2 increases, and Second Threshold voltage can be more big.
As it is shown on figure 3, be present pre-ferred embodiments hysteresis voltage comparator circuit diagram; On the basis of the embodiment of the present invention shown in Fig. 2, present pre-ferred embodiments has done following improvement:
Described first load metal-oxide-semiconductor 1 includes the second NMOS tube MN2, the 3rd NMOS tube MN3 and the six PMOS MP6; The drain electrode of described second NMOS tube MN2 connects with the drain electrode of described first PMOS MP1, the source ground GND of described second NMOS tube MN2; The grid of described 3rd NMOS tube MN3 connects grid and drain electrode, the source ground GND of described 3rd NMOS tube MN3 of described second NMOS tube MN2; The drain and gate of described 6th PMOS MP6 connects the drain electrode of described 3rd NMOS tube MN3 and the grid of described 3rd PMOS MP3, and the source electrode of described 6th PMOS MP6 meets supply voltage VDD.
Described second load metal-oxide-semiconductor 2 includes the 4th NMOS tube, the grid of described 4th NMOS tube and drain electrode and connects the drain electrode of described second PMOS MP2 and the grid of described first NMOS tube MN1, the source ground GND of described 4th NMOS tube.
Described first current source I1 is formed by PMOS MP7 and MP8 mirror image by current source I3, and described second current source I2 is formed by PMOS MP7 and MP9 mirror image by current source I3.
Described first CMOS inverter 3 is formed by PMOS MP10 and NMOS tube MN5 connection; Described second CMOS inverter 4 is formed by PMOS MP11 and NMOS tube MN6 connection.
As shown in Figure 4 A, be present pre-ferred embodiments remove switch-mode regulation threshold voltage time input and Output simulation curve, namely input when the drain electrode of drain electrode and described 5th PMOS MP5 that the drain electrode of described 4th PMOS MP4 is free of attachment to described first PMOS MP1 is free of attachment to the drain electrode of described second PMOS MP2 and curve of output, input signal Vinn remains unchanged, input signal Vinp be initially from low toward after promotion from high past sinking, output signal Vout3 input signal Vinp from low toward arrival threshold V T RP promotion process time from low transition to high level, output signal Vout3 jumps to low level when inputting signal Vinp and arriving threshold V T RP from height toward sinking process from high level, threshold V T RP shown in Fig. 4 A is 1.5V.
As shown in Figure 4 B, it is input and the Output simulation curve of present pre-ferred embodiments. input signal Vinn remains unchanged, input signal Vinp be initially from low toward after promotion from high past sinking, output signal Vout3 input signal Vinp from low toward arrival Second Threshold voltage VTRP+ promotion process time from low transition to high level, output signal Vout3 jumps to low level when inputting signal Vinp and arriving first threshold voltage VTRP-from height toward sinking process from high level, can be seen that, Second Threshold voltage VTRP+ is more than 1.5V, first threshold voltage VTRP-is less than 1.5V, a retarding window is defined between Second Threshold voltage VTRP+ and first threshold voltage VTRP-.
Above by specific embodiment, the present invention is described in detail, but these have not been construed as limiting the invention. Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improvement, and these also should be regarded as protection scope of the present invention.
Claims (4)
1. a hysteresis voltage comparator, it is characterised in that including:
First PMOS and the second PMOS, the source electrode of described first PMOS and described second PMOS links together and connects with the first current source; The grid of described first PMOS and described second PMOS is as the input of a pair differential signal;
The drain electrode of described first PMOS and the first load metal-oxide-semiconductor connect, and the drain electrode of described second PMOS and the second load metal-oxide-semiconductor connect;
3rd PMOS and the first NMOS tube, the electric current of described 3rd PMOS and described first load metal-oxide-semiconductor is mirror image relationship, and the electric current of described first NMOS tube and described second load metal-oxide-semiconductor is mirror image relationship; The drain electrode of described 3rd PMOS and the drain electrode of described first NMOS tube link together and as the first outfan, and the source electrode of described 3rd PMOS connects supply voltage, the source ground of described first NMOS tube;
First CMOS inverter and the second CMOS inverter, the input of described first CMOS inverter connects described first outfan, and the outfan of described first CMOS inverter is the second outfan; The input of described second CMOS inverter connects described second outfan, and the outfan of described second CMOS inverter is the 3rd outfan;
4th PMOS switch pipe is connected between the drain electrode of the second current source and described first PMOS, and the grid of described 4th PMOS switch pipe connects described second outfan;
5th PMOS switch pipe is connected between the drain electrode of the 3rd current source and described second PMOS, and the grid of described 5th PMOS switch pipe connects described 3rd outfan;
Described 4th PMOS switch pipe is opened when described first outfan output high level and increases the electric current of described first load metal-oxide-semiconductor and form positive feedback structure, and the electric current being input in described first load metal-oxide-semiconductor by regulating described 4th PMOS switch pipe regulates the output voltage of hysteresis voltage comparator by the first threshold voltage of high step-down;
Described 5th PMOS switch pipe is opened when described first outfan output low level and increases the electric current of described second load metal-oxide-semiconductor and form positive feedback structure, and the electric current being input in described second load metal-oxide-semiconductor by regulating described 5th PMOS switch pipe regulates the output voltage of described hysteresis voltage comparator by the low Second Threshold voltage uprised.
2. hysteresis voltage comparator as claimed in claim 1, it is characterised in that: described first load metal-oxide-semiconductor includes the second NMOS tube, the 3rd NMOS tube and the 6th PMOS; The drain electrode of described second NMOS tube connects with the drain electrode of described first PMOS, the source ground of described second NMOS tube;
The grid of described 3rd NMOS tube connects grid and drain electrode, the source ground of described 3rd NMOS tube of described second NMOS tube;
The drain and gate of described 6th PMOS connects the drain electrode of described 3rd NMOS tube and the grid of described 3rd PMOS, and the source electrode of described 6th PMOS connects supply voltage.
3. hysteresis voltage comparator as claimed in claim 1, it is characterized in that: described second load metal-oxide-semiconductor includes the 4th NMOS tube, the grid of described 4th NMOS tube and drain electrode connect the drain electrode of described second PMOS and the grid of described first NMOS tube, the source ground of described 4th NMOS tube.
4. hysteresis voltage comparator as claimed in claim 1, it is characterised in that: described second current source and described 3rd current source are for adopting same current source.
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| CN201410612343.3A CN105630054B (en) | 2014-11-04 | 2014-11-04 | Hysteresis voltage comparator |
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| CN201410612343.3A CN105630054B (en) | 2014-11-04 | 2014-11-04 | Hysteresis voltage comparator |
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| CN105630054B CN105630054B (en) | 2017-06-06 |
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Cited By (4)
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| CN107196629A (en) * | 2017-05-04 | 2017-09-22 | 深圳大学 | A kind of discrete threshold values voltage comparator of zero quiescent dissipation |
| CN108649934A (en) * | 2018-05-31 | 2018-10-12 | 成都锐成芯微科技股份有限公司 | A kind of hysteresis comparator circuit |
| CN110233612A (en) * | 2019-07-09 | 2019-09-13 | 中国电子科技集团公司第五十八研究所 | A kind of single input current mode hysteresis comparator |
| CN116886091A (en) * | 2023-06-28 | 2023-10-13 | 江苏帝奥微电子股份有限公司 | Logic threshold judging circuit and judging method thereof |
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| CN1949668A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Retarding comparator circuit of single terminal input |
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| CN107196629A (en) * | 2017-05-04 | 2017-09-22 | 深圳大学 | A kind of discrete threshold values voltage comparator of zero quiescent dissipation |
| CN107196629B (en) * | 2017-05-04 | 2020-10-23 | 深圳大学 | Discrete threshold voltage comparator with zero static power consumption |
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| CN116886091A (en) * | 2023-06-28 | 2023-10-13 | 江苏帝奥微电子股份有限公司 | Logic threshold judging circuit and judging method thereof |
| CN116886091B (en) * | 2023-06-28 | 2024-06-07 | 江苏帝奥微电子股份有限公司 | Logic threshold judging circuit and judging method thereof |
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