JP2005101696A - Hysteresis comparator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hysteresis comparator circuit in which the output voltage swings substantially fully over the entire power supply voltage range. <P>SOLUTION: The hysteresis comparator circuit comprises PMOS transistors 10, 11 where the source is connected with VCC and the gate is connected with the drain, NMOS transistors 18, 19 where the drain is connected with the drain of the transistors 10, 11 and the gate is connected with the inputs VIN, VIP, a constant current source 21 being connected with the source and VSS of the transistors 18, 19, PMOS transistors 12, 13 where the source is connected with VCC, the gate is connected with the drain of the transistors 10, 11 and the drain is connected with the outputs VON, VOP, constant current sources 20, 23 connected with the drain of the transistors 12, 13 and connected with the VSS, NMOS transistors 16, 17 where the drain is connected with the drain of the transistors 12, 13 and the gate is connected with the drain of the transistors 12, 13, and a constant current source 22 being connected with the source and VSS of the transistors 16, 17. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a hysteresis comparator circuit in which hysteresis characteristics are added to a differential input differential output comparator.

  As shown in FIG. 4, the basic circuit configuration of a conventional differential input differential output comparator is a pair of load resistors R1, R2 (R1 = R2), a pair of differential input NMOS transistors 1, 2, The constant current source 3 is used.

  When differential input signals with input voltages VIN and VIP are input to the gates of the differential input NMOS transistors 1 and 2, respectively, the differential output voltages VON and VOP are expressed by the following equation 1 depending on the magnitude of the input voltage. Will change. Here, VCC is a power supply voltage of the comparator, and I3 is a current flowing through the constant current source 3.

(Equation 1)
VIN> VIP: VON = VCC-R1 × I3, VOP = VCC
VIN <VIP: VON = VCC, VOP = VCC-R2 × I3

  However, if there is a minute differential input in the range of several mV of VIN≈VIP, the output voltage of the comparator fluctuates and the operation becomes unstable.

  As a technique for solving this, a hysteresis comparator in which a hysteresis characteristic is added to the basic configuration of FIG. As shown in FIG. 5, this hysteresis comparator has a circuit configuration in which a differential stage for positive feedback is connected in parallel to the comparison differential stage having the basic configuration shown in FIG.

  The differential stage for positive feedback includes an NMOS transistor 8 whose gate is connected to the inverted input terminal N8, an NMOS transistor 9 whose gate is connected to the inverted input terminal N9, and a constant current source 7 for passing a current I7 smaller than the current I6. It has. An inverted input terminal N8 on the gate side of the NMOS transistor 8 is connected to the positive output terminal VON, and its drain is connected to the negative output terminal VOP. Further, the inverting input terminal N9 on the gate side of the NMOS transistor 9 is connected to the negative output terminal VOP, and the drain thereof is connected to the positive output terminal VON. Furthermore, the sources of the NMOS transistors 8 and 9 are connected in common and connected to VSS (ground potential) via the second constant current source 7.

  Next, the operation of the hysteresis comparator shown in FIG. 5 will be described. For example, the comparison input voltage VIN input to the NMOS transistor 4 is lower than the comparison input voltage VIP input to the NMOS transistor 5, the positive side output voltage VON is the same level as VCC, and the negative side output voltage VOP is {VCC. When the level is −R4 × (I6 + I7)}, the comparison input voltage VIP applied to the gate side of the NMOS transistor 5 is higher than the comparison input voltage VIN applied to the gate side of the NMOS transistor 4. A current I6 flows through the NMOS transistor 5. Further, since the positive output voltage VON of the gate of the NMOS transistor 8 is higher than the negative output voltage VOP of the gate of the NMOS transistor 9, the current I7 of the constant current source 7 flows through the NMOS transistor 8. Therefore, the positive output voltage VON is fixed to the same level as VCC, and the negative output voltage VOP is fixed to the {VCC-R4 × (I6 + I7)} level.

  In order to invert the output voltages VON and VOP from this state, the sum of the current flowing through the NMOS transistor 4 and the current flowing through the NMOS transistor 9 is made larger than the sum of the current flowing through the NMOS transistor 5 and the current flowing through the NMOS transistor 8. There must be.

  Next, a voltage difference VHIS1 between the compared input voltage VIN1 and the comparison input voltage VIP, which is the upper limit threshold value of the comparator at this time, is calculated. In general, the drain current ID of the NMOS transistors 4 and 5 is expressed by the following formula 2.

(Equation 2)
ID = (W / L) × μn × Co × {(VG-VT) × VD-VD 2/2}
W: Gate width L: Gate length
μn: Electron mobility Co: Gate capacitance VG: Gate voltage VT: Threshold voltage VD: Drain voltage (drain-source voltage)

  The NMOS transistor 4 and the NMOS transistor 5 have the same characteristics, and their drain voltages VD are at the same level. Therefore, assuming that the source voltage of the NMOS transistor 4 and the NMOS transistor 5 is VS4, the drain voltage is VD4, the drain current of the NMOS transistor 4 is ID4, and the drain current of the NMOS transistor 5 is ID5, the current I6 of the constant current source 6 and the upper limit threshold value. VHIS1 is given by the following equations 3 and 4.

(Equation 3)
I6 = ID4-ID5
= (W / L) × μn × Co × {(VIN1-VS4-VT) × VD4
^{-VD4 2/2} - (W} / L) × μn × Co × {(VIP-VS4
^{-VT) × VD4-VD4 2/} 2}
= (W / L) × μn × Co × VD4 × (VIN1-VIP)

(Equation 4)
VHS1 = VIN1-VIP = I6 / {(W / L) × μn × Co × VD4}

  Further, when the compared input voltage VIN is higher than the compared input voltage VIP, the positive side output voltage VON is at {VCC-R3 × (I6 + I7)} level, and the negative side output voltage VOP is at the same level as VCC, Since the comparison input voltage VIP is lower than the comparison input voltage VIN, the current I6 flowing through the constant current source 6 flows through the NMOS transistor 4. Furthermore, since the positive output voltage VON of the inverted input terminal N8 connected to the gate of the NMOS transistor 8 is lower than the negative output voltage VOP of the inverting input terminal N9 connected to the gate of the NMOS transistor 9, the current of the constant current source 7 I7 flows through the NMOS transistor 9. Therefore, the positive output voltage VON is fixed at the {VCC-R3 × (I6 + I7)} level, and the negative output voltage VOP is fixed at the same level as VCC.

  In order to invert the output voltages VON and VOP from this state, the sum of the current flowing through the NMOS transistor 5 and the current flowing through the NMOS transistor 8 is made larger than the sum of the current flowing through the NMOS transistor 4 and the current flowing through the NMOS transistor 9. There must be.

  The voltage difference VHIS2 between the compared input voltage VIN2 and the comparison input voltage VIP, which is the lower limit threshold value of the comparator at this time, is given by Equation 6 using the current I6 of the constant current source 6 shown in Equation 5 below.

(Equation 5)
I6 = ID5-ID4
= (W / L) × μn × Co × {(VIP-VS4-VT) × VD4
^{-VD4 2/2} - (W} / L) × μn × Co × {(VIN2-VS4
^{-VT) × VD4-VD4 2/} 2}
= (W / L) × μn × Co × VD4 × (VIP−VIN2)

(Equation 6)
VHS2 = VIP−VIN2 = I6 / {(W / L) × μn × Co × VD4}

  Therefore, the hysteresis width VHIS of the input voltage to be compared VIN is expressed by the following formula 7, and hysteresis can be given by the circuit configuration shown in FIG.

(Equation 7)
VHIS = VHIS1 + VHIS2
= (VIN1-VIP) + (VIP-VIN2)
= VIN1-VIN2
= 2 × I6 / {(W / L) × μn × Co × VD4}

In the above description, the same symbols are used for the names corresponding to the input terminal name and input voltage, and the output terminal name and output voltage.
JP-A-6-13855

    However, in the case of the above-described conventional hysteresis comparator, the differential outputs VOP and VON are output only in the voltage range of VCC to {VCC-R3 × (I6 + I7)} with respect to the power supply voltage VCC, and the output amplitude is small. Therefore, there is a problem that it cannot be used unless an amplifying circuit or the like is added because it is necessary to maintain consistency with a circuit in the subsequent stage.

  The present invention has been made in view of the above-described problems, and the object thereof is to widen the output voltage amplitude to a voltage range between the power supply potential and the ground potential, and to simplify the circuit design of the subsequent stage. It is to provide a hysteresis comparator circuit.

  In order to achieve this object, a hysteresis comparator circuit according to the present invention includes a differential input circuit unit, a differential output circuit unit, and a positive feedback circuit unit, and the differential input circuit unit has a first source. A first PMOS transistor having a gate and a drain connected to a power supply potential, a source connected to the first power supply potential, a second PMOS transistor having a gate and a drain connected, and a drain connected to the drain of the first PMOS transistor. A first NMOS transistor having a gate connected to the first input terminal, a drain connected to the drain of the second PMOS transistor, a gate connected to the second input terminal, and one end connected to the first NMOS transistor The other end of the second NMOS transistor is commonly connected to the source of the second NMOS transistor. A first constant current circuit connected to a lower power supply potential, wherein the differential output circuit section has a source connected to the first power supply potential and a gate connected to the first PMOS transistor. A third PMOS transistor having a drain connected to the first output terminal, a source connected to the first power supply potential, a gate connected to the drain of the second PMOS transistor, and a drain connected to the second output terminal. A fourth PMOS transistor connected; a second constant current circuit having one end connected to the drain of the third PMOS transistor and the other end connected to the second power supply potential; and one end connected to the drain of the fourth PMOS transistor. And a third constant current circuit having the other end connected to the second power supply potential, and the positive feedback circuit section has a drain connected to the second power supply potential. A fourth NMOS transistor having a drain connected to the drain of the third PMOS transistor, a drain connected to the drain of the third PMOS transistor, and a gate connected to the drain of the fourth PMOS transistor; And a fourth constant current circuit having one end commonly connected to the sources of the third NMOS transistor and the fourth NMOS transistor and the other end connected to the second power supply potential. It is characterized by.

  According to the hysteresis comparator circuit of the first characteristic configuration, the differential input circuit unit forms a basic circuit configuration of the differential input differential output comparator, and the upper limit of the amplitude of the differential output of the differential input circuit unit is The differential output circuit has a voltage lower than the first power supply potential by the threshold voltage of the first and second PMOS transistors, and the differential outputs are input to the gates of the third and third PMOS transistors of the differential output circuit section, respectively. The lower limit of the differential output of the section is substantially lowered to the second power supply potential, and the upper limit depends on the lower limit level of the differential output of the differential input circuit section and the current values of the second and third constant current circuits. It can be raised to near the power supply potential. Furthermore, by providing the positive feedback circuit unit in parallel with the differential output circuit unit instead of the differential input circuit unit, the output amplitude of the differential output circuit unit is increased and the differential input to the differential output circuit unit, that is, Hysteresis is imparted to the differential output of the differential input circuit unit, and as a result, hysteresis can be imparted to the differential input of the differential input circuit unit, and the output voltage amplitude is substantially equal to the first power supply potential and the second power supply. It is possible to provide a hysteresis comparator circuit that can be expanded to a voltage range between potentials and that can simplify circuit design in the subsequent stage. Here, by setting the first or second power supply potential to the ground potential, it is possible to provide a hysteresis comparator circuit capable of extending the output voltage amplitude to a voltage range substantially between the power supply potential and the ground potential.

  Furthermore, the hysteresis comparator circuit according to the present invention includes a differential input circuit unit, a differential output circuit unit, and a positive feedback circuit unit, and the differential input circuit unit has a source connected to the second power supply potential. A first NMOS transistor having a gate and drain connected; a source connected to the second power supply potential; a second NMOS transistor having a gate and drain connected; and a drain connected to the drain of the first NMOS transistor; A first PMOS transistor connected to the input terminal; a drain connected to the drain of the second NMOS transistor; a gate connected to the second input terminal; and one end connected to a source of the first PMOS transistor and the second PMOS transistor. Are connected in common and the other end has a first potential higher than the second power supply potential. A first constant current circuit connected to a source potential, wherein the differential output circuit unit has a source connected to the second power supply potential, a gate connected to the drain of the first NMOS transistor, A third NMOS transistor having a drain connected to the first output terminal, a source connected to the second power supply potential, a gate connected to the drain of the second NMOS transistor, and a drain connected to the second output terminal; A second constant current circuit having one end connected to the drain of the third NMOS transistor and the other end connected to the first power supply potential; one end connected to the drain of the fourth NMOS transistor; A third constant current circuit connected to the first power supply potential, the positive feedback circuit section having a drain connected to the fourth NMOS transistor. A third PMOS transistor having a gate connected to a drain of the third NMOS transistor, a drain connected to a drain of the third NMOS transistor, and a gate connected to a drain of the fourth NMOS transistor; A fourth constant current circuit having one end connected in common to the sources of the third PMOS transistor and the fourth PMOS transistor and the other end connected to the first power supply potential. Features.

  In the hysteresis comparator circuit of the first characteristic configuration, the conductivity type of the PMOS transistor and the NMOS transistor is inverted, and the first power supply potential and the second power supply potential are switched, thereby the hysteresis comparator circuit of the first characteristic configuration A hysteresis comparator circuit having a symmetric second characteristic configuration is obtained. Accordingly, the circuit operation of the hysteresis comparator circuit having the second characteristic configuration is substantially the same as that of the hysteresis comparator circuit having the first characteristic configuration except that the voltage level is inverted, and the output voltage amplitude is substantially the same as that of the first characteristic configuration. It is possible to provide a hysteresis comparator circuit that can be expanded to a voltage range between the power supply potential and the second power supply potential, and can simplify the circuit design of the subsequent stage.

  An embodiment of a hysteresis comparator circuit according to the present invention (hereinafter referred to as “the present invention circuit” as appropriate) will be described with reference to the drawings. In the following description, the input terminal name and the input voltage, and the output terminal name and the output voltage will be described using the same symbols.

<First Embodiment>
FIG. 1 is a circuit diagram showing a first embodiment of the circuit of the present invention. As shown in FIG. 1, the circuit of the present invention is composed of three circuit parts, a differential input circuit part at the front stage, a differential output circuit part at the rear stage, and a positive feedback circuit part as follows.

  In the differential input circuit portion, the first and second PMOS transistors 10 and 11 are configured by a diode connection circuit in which the gate and the drain are connected at the same potential, and the sources of the first and second PMOS transistors 10 and 11 are the first. It is connected to a power supply potential VCC (hereinafter referred to as “VCC” as appropriate). The drains of the first and second PMOS transistors 10 and 11 are connected to the drains of the first and second NMOS transistors 18 and 19, respectively. The sources of the first and second NMOS transistors 18 and 19 are connected in common to one end of the first constant current circuit 21, and the other end of the first constant current circuit 21 is a ground potential VSS (hereinafter referred to as appropriate). ("VSS"). Here, the gates of the first and second NMOS transistors 18 and 19 are connected to the first input terminal VIN and the second input terminal VIP, respectively. Further, the first power supply potential VCC is higher than the ground potential VSS (0 V), and the first constant current circuit 21 functions as a constant current source that allows a substantially constant current to flow within the operating range. Further, the first and second PMOS transistors 10 and 11 are set to have the same transistor characteristics, and the first and second NMOS transistors 18 and 19 are set to have the same transistor characteristics.

  The differential input circuit unit is connected to the second-stage differential output circuit unit. Specifically, the drain N10 of the first PMOS transistor 10 is connected to the gate of the third PMOS transistor 12 of the differential output circuit unit, the source of the third PMOS transistor 12 is connected to VCC, and the drain of the third PMOS transistor 12 is the first drain. The second constant current circuit 20 is connected to one end, and the other end of the second constant current circuit 20 is connected to VSS. The drain N11 of the second PMOS transistor 11 is connected to the gate of the fourth PMOS transistor 13, the source of the fourth PMOS transistor 13 is connected to VCC, the drain of the fourth PMOS transistor 13 is connected to one end of the third constant current circuit 23, The other end of the third constant current circuit 23 is connected to VSS. Here, the drains of the third and fourth PMOS transistors 12 and 13 are connected to the first output terminal VON and the second output terminal VOP. The second and third constant current circuits 20 and 23 function as constant current sources that allow a substantially constant current to flow within the operating range, and the current values of both are set to be the same. Further, the third and fourth PMOS transistors 12 and 13 are set to have the same transistor characteristics.

  In the positive feedback circuit section, the first output terminal VON adjusts the offset potential of the differential output circuit section in proportion to the output voltage of the first output terminal VON, so that the first output terminal VON is the gate of the third NMOS transistor 16 and the drain of the fourth NMOS transistor 17. And the second output terminal VOP is connected to the drain of the third NMOS transistor 16 and the gate of the fourth NMOS transistor 17 in order to adjust the offset potential of the differential output circuit portion in proportion to the output voltage of the second output terminal VOP. The sources of the third and fourth NMOS transistors 16 and 17 provided for offset adjustment are connected to one end of the fourth constant current circuit 22, and the other end of the fourth constant current circuit 22 is connected to VSS. Yes. Here, the fourth constant current circuit 22 functions as a constant current source for supplying a substantially constant current within the operating range, and the third and fourth NMOS transistors 16 and 17 are set to have the same transistor characteristics.

  Next, the operation of the circuit of the present invention will be described. First, a case is assumed where the first input voltage (compared input voltage) VIN of the first input terminal VIN is VIN1, and VIN1> VIP with respect to the second output voltage (positive output voltage) VOP.

  The first input voltage VIN1 input to the gate of the first NMOS transistor 18 is higher than the second input voltage VIP input to the gate of the second NMOS transistor 19, and the first output voltage (negative output) of the first output terminal VON. Voltage) When VON is at the same level as VCC and the second output voltage (positive output voltage) VOP of the second output terminal VOP is at the ground potential VSS, the first input voltage VIN1 applied to the gate side of the first NMOS transistor 18 Since the second input voltage VIP applied to the gate side of the second NMOS transistor 19 is lower than that, the current I21 flowing through the first constant current circuit 21 flows through the first NMOS transistor 18. As a result, the potential level of the diode-connected drain N10 of the first PMOS transistor 10 decreases, and the state of the third PMOS transistor 12 changes in the direction in which the drain current flows. The differential output circuit unit is configured as a source grounded amplifier circuit. When the on-resistance of the third PMOS transistor 12 whose gate is connected to the drain N10 is r12 and the internal resistance of the second constant current circuit 20 is r20, the amplification is performed. Since the rate Av is as large as Av = −gm × (r20 // r12), the first output voltage VON is almost fixed at VCC. At this time, the fourth NMOS transistor 17 is not turned on because the second output voltage VOP is at the ground potential VSS, and does not affect the first output voltage VON.

Conversely, the potential level of the diode-connected drain N11 of the second PMOS transistor 11 rises, and the state of the fourth PMOS transistor 13 changes in a direction in which no drain current flows. The differential output circuit unit is configured as a source grounded amplifier circuit. When the on-resistance of the fourth PMOS transistor 13 whose gate is connected to the drain N11 is r13 and the internal resistance of the third constant current circuit 23 is r23, the amplification is performed. The rate Av is Av = −gm × (r13 // r23) as described above, and the second output voltage VOP is substantially fixed at the ground potential VSS. At this time, the first output voltage VON is almost at the potential level of VCC, and since the drain of the third NMOS transistor 16 is connected to the second output terminal VOP, the on-resistance of the third NMOS transistor 16 is r16. The offset level of the two output voltage VOP is lowered by V _OFFSET −r16 × I22. Here, I 22 is a current flowing through the fourth constant current circuit 22.

  Next, it is assumed that VIN = VIN2 and VIN2 <VIP. The second input voltage VIP input to the second NMOS transistor 19 is higher than the first input voltage VIN2 input to the first NMOS transistor 18, the second output voltage VOP is the same level as VCC, and the first output voltage VON is the ground potential. In the case of VSS, since the first input voltage VIN2 applied to the gate side of the first NMOS transistor 18 is lower than the second input voltage VIP applied to the gate side of the second NMOS transistor 19, the current flowing through the first constant current circuit 21 I 21 flows through the second NMOS transistor 19. As a result, the potential level of the diode-connected drain N11 of the second PMOS transistor 11 decreases, and the state of the fourth PMOS transistor 13 changes in the direction in which the drain current flows. The differential output circuit section is configured as a common-source amplifier circuit, and the amplification factor Av is Av = −gm × (r13 // r23). Therefore, the second output voltage VOP is almost fixed at the potential level of VCC. Is done. At this time, the third NMOS transistor 16 does not turn on because the first output voltage VON is at the ground potential VSS, and does not affect the second output voltage VOP.

Conversely, the potential level of the diode-connected drain N10 of the first PMOS transistor 10 rises, and the state of the third PMOS transistor 12 changes in a direction in which no current flows. The differential output circuit unit is configured as a source-grounded amplifier circuit. The amplification factor Av is Av = −gm × (r20 // r12), and the first output voltage VON is substantially fixed at the ground potential VSS. At this time, the second output voltage VOP is almost at the potential level of VCC, and the drain of the fourth NMOS transistor 17 is connected to the first output terminal VON. The offset level of one output voltage VON is lowered by V _OFFSET −r17 × I22.

  Further, since the on-resistances r16 and r17 of the third and fourth NMOS transistors 16 and 17 use transistors of the same size and have the same characteristics, the hysteresis width VHIS of the circuit of the present invention is expressed by the following equation (8). Expressed and can have hysteresis characteristics.

(Equation 8)
VHIS = VHIS1-VHIS2
= (V _OFFSET −r16 × I22) − (V _OFFSET −r17 × I22)
= 2 × r16 × I22

  Next, FIG. 2 shows a transient analysis result by the circuit simulator SPICE in the conventional hysteresis comparator shown in FIG. 5 and the circuit of the present invention shown in FIG. In FIG. 2, only the voltage waveform of one differential output terminal is shown for comparison of output amplitude. In the transient analysis, the first power supply potential VCC is 3.3 V, and the second power supply potential VSS is the ground potential 0 V.

  As is clear from FIG. 2, in the conventional hysteresis comparator, the output amplitude is 1.9 V to 3.2 V (that is, {VCC−R4 × (I6 + I7)} to VCC). In the circuit of the present invention, it can be seen that the amplitude is from 0 V to 3.1 V (≈VCC). As a supplement, the upper limit voltage of the output amplitude in the circuit of the present invention is 3.1 V which is about 0.2 V lower than the first power supply potential level of 3.3 V. The second or third constant current circuit 20 This is because there is a voltage drop corresponding to the drain voltage Vds of the third or fourth PMOS transistors 12 and 13 corresponding to the current of.

Second Embodiment
FIG. 3 is a circuit diagram showing a second embodiment of the circuit of the present invention. The difference from the first embodiment shown in FIG. 1 is that the differential signal input is input to the NMOS transistor in the first embodiment, whereas the differential signal input is different in the second embodiment. Input to the PMOS transistor. For this reason, in the second embodiment, all NMOS transistors in the first embodiment are converted to PMOS transistors, all PMOS transistors in the first embodiment are converted to NMOS transistors, and the first power supply potential VCC is converted to the second power supply potential VSS. In addition, the second power supply potential VSS is replaced with the first power supply potential VCC.

  The circuit of the present invention according to the second embodiment is configured as follows, as shown in FIG.

  In the differential input circuit section, the first and second NMOS transistors 24 and 25 are configured by a diode connection circuit in which the gate and the drain are connected at the same potential, and the sources of the first and second NMOS transistors 24 and 25 are the second. It is connected to the power supply potential VSS. The drains of the first and second NMOS transistors 24 and 25 are connected to the drains of the first and second PMOS transistors 30 and 31, respectively. The sources of the first and second PMOS transistors 30 and 31 are commonly connected to one end of the first constant current circuit 33, and the other end of the first constant current circuit 33 is connected to the first power supply potential VCC. Here, the gates of the first and second PMOS transistors 30 and 31 are connected to the first input terminal VIN and the second input terminal VIP, respectively. Further, the first power supply potential VCC is higher than the ground potential VSS (0 V), and the first constant current circuit 33 functions as a constant current source that allows a substantially constant current to flow within the operating range. Further, the first and second NMOS transistors 24 and 25 are set to have the same transistor characteristics, and the first and second PMOS transistors 30 and 31 are set to have the same transistor characteristics.

  The differential input circuit unit is connected to the second-stage differential output circuit unit. Specifically, the drain N24 of the first NMOS transistor 24 is connected to the gate of the third NMOS transistor 26 of the differential output circuit section, the source of the third NMOS transistor 26 is connected to VSS, and the drain of the third NMOS transistor 26 is the second drain. The second constant current circuit 32 is connected to one end, and the other end of the second constant current circuit 32 is connected to VCC. The drain N25 of the second NMOS transistor 25 is connected to the gate of the fourth NMOS transistor 27, the source of the fourth NMOS transistor 27 is connected to VSS, the drain of the fourth NMOS transistor 27 is connected to one end of the third constant current circuit 35, The other end of the third constant current circuit 35 is connected to VCC. Here, the drains of the third and fourth NMOS transistors 26 and 27 are connected to the first output terminal VON and the second output terminal VOP. The second and third constant current circuits 32 and 35 function as constant current sources that flow a substantially constant current within the operating range, and the current values of both are set to be the same. Further, the third and fourth NMOS transistors 26 and 27 are set to have the same transistor characteristics.

  In the positive feedback circuit section, the first output terminal VON adjusts the offset potential of the differential output circuit section in proportion to the output voltage of the first output terminal VON, so that the first output terminal VON is the gate of the third PMOS transistor 28 and the drain of the fourth PMOS transistor 29. And the second output terminal VOP is connected to the drain of the third PMOS transistor 28 and the gate of the fourth PMOS transistor 29 in order to adjust the offset potential of the differential output circuit portion in proportion to the output voltage of the second output terminal VOP. The sources of the third and fourth PMOS transistors 28 and 29 provided for offset adjustment are connected to one end of the fourth constant current circuit 34, and the other end of the fourth constant current circuit 34 is connected to VCC. Yes. Here, the fourth constant current circuit 34 functions as a constant current source for supplying a substantially constant current within the operating range, and the third and fourth PMOS transistors 28 and 29 are set to have the same transistor characteristics.

  The operation of the inventive circuit of the second embodiment shown in FIG. 3 is the same as that of the inventive circuit of the first embodiment shown in FIG. 1, and the voltage level is between the first power supply potential VCC and the second power supply potential VSS. Is exactly the same except that it is flipped upside down.

1 is a circuit diagram of a first embodiment of a hysteresis comparator circuit according to the present invention. FIG. 6 is a voltage waveform diagram for comparing and displaying output amplitudes in the hysteresis comparator circuit according to the present invention shown in FIG. 1 and the conventional hysteresis comparator shown in FIG. 5. The circuit diagram in 2nd Embodiment of the hysteresis comparator circuit which concerns on this invention. The circuit diagram which shows the basic circuit structure of the conventional comparator. The circuit diagram which shows an example of the conventional hysteresis comparator.

Explanation of symbols

10, 30: First PMOS transistor (first embodiment, second embodiment)
11, 31: Second PMOS transistor (first embodiment, second embodiment)
12, 28: Third PMOS transistor (first embodiment, second embodiment)
13, 29: Fourth PMOS transistor (first embodiment, second embodiment)
18, 24: first NMOS transistor (first embodiment, second embodiment)
19, 25: second NMOS transistor (first embodiment, second embodiment)
16, 26: third NMOS transistor (first embodiment, second embodiment)
17, 27: Fourth NMOS transistor (first embodiment, second embodiment)
21, 33: First constant current circuit (first embodiment, second embodiment)
20, 32: second constant current circuit (first embodiment, second embodiment)
23, 35: Third constant current circuit (first embodiment, second embodiment)
22, 34: Fourth constant current circuit (first embodiment, second embodiment)
N10: drain of the first PMOS transistor (first embodiment)
N11: drain of the second PMOS transistor (first embodiment)
N24: Drain of the first NMOS transistor (first embodiment)
N25: drain of the second NMOS transistor (first embodiment)
VIN: First input terminal or first input voltage (compared input voltage)
VIP: Second input terminal or second input voltage (comparison input voltage)
VON: First output terminal or first output voltage (negative output voltage)
VOP: Second output terminal or second output voltage (positive output voltage)
VCC: first power supply potential VSS: second power supply potential (ground potential)

Claims (3)

A differential input circuit unit, a differential output circuit unit, and a positive feedback circuit unit;
The differential input circuit section is
A first PMOS transistor having a source connected to a first power supply potential and a gate and a drain connected;
A second PMOS transistor having a source connected to the first power supply potential and a gate and drain connected;
A first NMOS transistor having a drain connected to the drain of the first PMOS transistor and a gate connected to the first input terminal;
A second NMOS transistor having a drain connected to the drain of the second PMOS transistor and a gate connected to a second input terminal;
A first constant current circuit having one end connected in common to the sources of the first NMOS transistor and the second NMOS transistor and the other end connected to a second power supply potential lower than the first power supply potential. And
The differential output circuit section is
A third PMOS transistor having a source connected to the first power supply potential, a gate connected to the drain of the first PMOS transistor, and a drain connected to the first output terminal;
A fourth PMOS transistor having a source connected to the first power supply potential, a gate connected to the drain of the second PMOS transistor, and a drain connected to the second output terminal;
A second constant current circuit having one end connected to the drain of the third PMOS transistor and the other end connected to the second power supply potential;
A third constant current circuit having one end connected to the drain of the fourth PMOS transistor and the other end connected to the second power supply potential;
The positive feedback circuit section is
A third NMOS transistor having a drain connected to the drain of the fourth PMOS transistor and a gate connected to the drain of the third PMOS transistor;
A fourth NMOS transistor having a drain connected to the drain of the third PMOS transistor and a gate connected to the drain of the fourth PMOS transistor;
A fourth constant current circuit having one end connected in common to the sources of the third NMOS transistor and the fourth NMOS transistor and the other end connected to the second power supply potential. Comparator circuit. A differential input circuit unit, a differential output circuit unit, and a positive feedback circuit unit;
The differential input circuit section is
A first NMOS transistor having a source connected to the second power supply potential and a gate and drain connected;
A second NMOS transistor having a source connected to the second power supply potential and a gate and a drain connected;
A first PMOS transistor having a drain connected to the drain of the first NMOS transistor and a gate connected to the first input terminal;
A second PMOS transistor having a drain connected to the drain of the second NMOS transistor and a gate connected to the second input terminal;
A first constant current circuit having one end connected in common to the sources of the first PMOS transistor and the second PMOS transistor and the other end connected to a first power supply potential higher than the second power supply potential. And
The differential output circuit section is
A third NMOS transistor having a source connected to the second power supply potential, a gate connected to the drain of the first NMOS transistor, and a drain connected to the first output terminal;
A fourth NMOS transistor having a source connected to the second power supply potential, a gate connected to the drain of the second NMOS transistor, and a drain connected to the second output terminal;
A second constant current circuit having one end connected to the drain of the third NMOS transistor and the other end connected to the first power supply potential;
A third constant current circuit having one end connected to the drain of the fourth NMOS transistor and the other end connected to the first power supply potential;
The positive feedback circuit section is
A third PMOS transistor having a drain connected to the drain of the fourth NMOS transistor and a gate connected to the drain of the third NMOS transistor;
A fourth PMOS transistor having a drain connected to the drain of the third NMOS transistor and a gate connected to the drain of the fourth NMOS transistor;
And a fourth constant current circuit having one end connected in common to the sources of the third PMOS transistor and the fourth PMOS transistor and the other end connected to the first power supply potential. Comparator circuit.   3. The hysteresis comparator circuit according to claim 1, wherein one of the first power supply potential and the second power supply potential is a ground potential. 4.

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