CN104253410B - Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit - Google Patents
Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit Download PDFInfo
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- CN104253410B CN104253410B CN201410461278.9A CN201410461278A CN104253410B CN 104253410 B CN104253410 B CN 104253410B CN 201410461278 A CN201410461278 A CN 201410461278A CN 104253410 B CN104253410 B CN 104253410B
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Abstract
The invention discloses an overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit. The overvoltage breakdown preventing type input-stage ESD protection circuit comprises a diode module, a power clamp ESD protection circuit, a ballast module, a transmission gate module and a direct-current voltage detection module. The overvoltage breakdown preventing type input-stage ESD protection circuit disclosed by the invention has the advantages that since an input overvoltage phenomenon on a pad is effectively detected, the electrical connection between the pad and input-stage inverter gate oxide is disconnected when an ESD event occurs, the input end of an input-stage inverter is forcibly biased to zero and a dynamic resistor connecting method is adopted between the input-stage inverter and a power line, the safety of a functional circuit of a chip under the worst EDS impact situation is guaranteed and data transmission attenuation is guaranteed not to occur during normal operation of the chip.
Description
Technical field
The present invention relates to integrated circuit electrostatic discharge resist technology field, is more particularly to a kind of anti-over-voltage breakdown type input
Level esd protection circuit.
Background technology
Static discharge (Electronic Static Discharge, ESD) is a large amount of electrostatic charges at short notice not
There is the process for shifting between iso-electric object, when esd event occurs between the different pins of chip, usually cause phase
The over-voltage events between pin are answered, is a big important sources of chip failure by the over-voltage breakdown that esd event causes.
On piece, ESD design protections are emphasis and difficult point of semi-conductor industry circle with regard to reliability consideration all the time, input
Level esd protection circuit is the important composition of full chip ESD Preservation tactics, and its effect is mainly to ensure that input stage phase inverter gate oxidation
The safety of layer.
Circuit shown in Fig. 1 is a kind of common input stage esd protection circuit under traditional handicraft, in the circuit shown in Fig. 1,
Input pressure welding point is betided to ground wire VSSBetween positive ESD impact due to its equivalent resistance on path of releasing it is maximum, so
It is to design the worst case for facing.In the worst cases, traditional design utilizes resistance RbBallasting effect, it is ensured that electrostatic charge
By diode D1Ground is released to power clamp ESD protective circuit, electrostatic charge is prevented effectively to chip input stage phase inverter
With the infringement of inner function circuit.Meanwhile, under traditional technique, the gate oxide of MOS transistor is thicker, in worst case
When esd event occurs, even if occurring over-pressed phenomenon in short-term in input pressure welding point, the gate oxide of input stage can't be caused
Puncture and cause failure.
With the continuous progress of integrated circuit technology, the thickness of gate oxide is constantly thinning, accordingly, its breakdown voltage
Constantly reduce, now, traditional input stage esd protection circuit no longer can effective protection input stage phase inverter gate oxidation
Layer.Resistance R in increase Fig. 1bThe gate oxide of input stage phase inverter can be effectively isolated and pressure welding point is input into, but the electricity of increase
Resistance RbMore chip areas can be consumed, meanwhile, in chip normal work, the resistance R of increasebBigger signal can be brought to decline
Subtract.
The content of the invention
(1) technical problem to be solved
The technical problem to be solved in the present invention is how design effectively input stage esd protection circuit, it is ensured that input stage is anti-phase
The gate oxide of device does not cause failure under the ESD impact of worst case because puncturing, and strengthens the potential of chip functions circuit
Breakdown weak points, while, it is ensured that during chip normal work, data can zero-decrement transmission.
(2) technical scheme
In order to solve above-mentioned technical problem, the invention provides a kind of anti-over-voltage breakdown type input stage esd protection circuit, bag
Include diode (led) module, power clamp ESD protective circuit, it is characterised in that also including ballasting module, transmission gate module and direct current
Voltage detection module；
When the diode (led) module is for occurring ESD impact between pressure welding point and other chip pins, effectively by electrostatic
Electric charge is directed to releasing on path of designing, in chip normal work, there is provided the isolation between data path and power line；
The power clamp ESD protective circuit is in power line VDDWith ground wire VSSBetween conduct the electricity that brings of ESD impact
Lotus, meanwhile, in chip normal work, power clamp ESD protective circuit is in strict off state；
The DC voltage detecting module whether occur in pressure welding point over-pressed phenomenon for detecting, when there is over-pressed phenomenon,
DC voltage detecting module sends drive signal to transmission gate module and ballasting module, makes between pressure welding point and input stage phase inverter
Electrical connection disconnect, and make input stage phase inverter and power line VDDBetween resistance become big, when not there is over-pressed phenomenon,
DC voltage detecting module sends the normal transmission that drive signal ensures data to transmission gate module and ballasting module；
The ballasting module, changes input stage phase inverter PMOS transistor M for dynamicpSource electrode and power line VDDIt
Between resistance, when an esd event occurs, increase input stage phase inverter PMOS transistor MpSource electrode and power line VDDBetween electricity
Resistance, it is ensured that electrostatic charge is released by the path of releasing for designing, in chip normal operating, significantly reduces input stage phase inverter
PMOS transistor MpSource electrode and power line VDDBetween resistance, it is ensured that voltage is unattenuated；
The transmission gate module, is broken when over-voltage events occur for the signal sent according to DC voltage detecting module
The electrical connection between the gate oxide of pressure welding point and input stage phase inverter is opened, meanwhile, force the input voltage input stage phase inverter
Zero is biased to, in chip normal operating, it is ensured that the normal transmission of data.
Preferably, the DC voltage detecting module includes PMOS transistor Mp2, resistance R2, resistance R3, it is diode string, anti-
Phase device INV1, INV2, INV3；PMOS transistor Mp2Source electrode connection pressure welding point, its grid pass through the resistance R2Connection
To pressure welding point, PMOS transistor Mp2Drain electrode pass through the resistance R3It is connected to ground, PMOS transistor Mp2Drain electrode
Voltage signal sequentially passes through output overvoltage detectable signal ESD after described phase inverter INV1, INV2 drive, the over-pressed detectable signal
Reversely overvoltage detectable signal ESDX is exported after the phase inverter INV3 logic reversals；PMOS transistor Mp2Grid connect
Connect the anode of the diode string of positive series connection successively, the minus earth of the diode string；The pressure welding point voltage is institute
State phase inverter INV1, INV2 to power, supply voltage VDDPower for the phase inverter INV3.
Preferably, the ballasting module includes resistance R1, PMOS transistor Mpb, nmos pass transistor Mnb；The NMOS crystal
Pipe MnbGrid driven by the reverse over-pressed detectable signal ESDX, PMOS transistor MpbGrid by it is described overvoltage detect
Signal ESD is driven；The nmos pass transistor MnbDrain electrode, PMOS transistor MpbSource electrode, the resistance R1One end
It is all connected with the power line VDD；The nmos pass transistor MnbSource electrode, PMOS transistor MpbDrain electrode, the resistance R1
The other end be all connected be input into pole phase inverter in PMOS transistor MpSource electrode.
Preferably, the transmission gate module includes PMOS transistor Mpt, nmos pass transistor Mnta, nmos pass transistor Mnt；Institute
State PMOS transistor Mpt, the nmos pass transistor MntaGrid driven by the over-pressed detectable signal ESD, the NMOS
Transistor MntGrid driven by the reverse over-pressed detectable signal ESDX；PMOS transistor MptSource electrode, described
Nmos pass transistor MntDrain electrode be all connected with the pressure welding point；PMOS transistor MptDrain electrode, the nmos pass transistor Mnt's
Source electrode, the nmos pass transistor MntaDrain electrode be all connected with the input of the input stage phase inverter；The nmos pass transistor Mnta
Source ground.
Preferably, the diode (led) module includes diode D1, diode D2.The diode D1Anode it is anti-with described
The pressure welding point of over-voltage breakdown type input stage esd protection circuit is connected, the diode D1Negative electrode and the anti-over-voltage breakdown type
The power line V of input stage esd protection circuitDDIt is connected；The diode D2Anode and anti-over-voltage breakdown type input stage ESD
The ground wire V of protection circuitSSIt is connected, the diode D2Negative electrode and the anti-over-voltage breakdown type input stage esd protection circuit
Pressure welding point is connected.
Preferably, the power clamp ESD protective circuit includes resistance R, electric capacity C, PMOS transistor Mp1, nmos pass transistor
Mn1、Mbig、Mfb；One end of the resistance R, PMOS transistor MP1Source electrode, the nmos pass transistor MbigDrain electrode connect
Meet the power line VDD；The other end of the resistance R, one end of the electric capacity C, the nmos pass transistor MfbDrain electrode, described
PMOS transistor Mp1Grid be all connected with the nmos pass transistor Mn1Grid；The nmos pass transistor MfbGrid, described
PMOS transistor Mp1Drain electrode, the nmos pass transistor Mn1Drain electrode be all connected to the nmos pass transistor MbigGrid；Institute
State the other end of electric capacity C, the nmos pass transistor MfbSource electrode, the nmos pass transistor Mn1Source electrode, the nmos pass transistor
MbigSource grounding.
Preferably, the number of diodes of the diode string in DC voltage detecting module is according to different technique feelings
Condition, selectable value are 3-5.
(3) beneficial effect
The invention provides a kind of anti-over-voltage breakdown type input stage esd protection circuit, the anti-over-voltage breakdown type input stage
Esd protection circuit by the over-pressed phenomenon in effectively detection input pressure welding point, when esd event occurs, disconnection pressure welding point with it is defeated
Enter the electrical connection between grade phase inverter gate oxide, and the input of input stage phase inverter is forced to be biased to zero, meanwhile, to defeated
Enter grade phase inverter to the connected mode between power line using dynamic electric resistor, it is ensured that chip functions circuit is in the worst ESD impact
In the case of safety, and ensure in chip normal operating, the zero-decrement transmission of data.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the structural representation of common input stage esd protection circuit in traditional handicraft；
Fig. 2 is the structural representation of the anti-over-voltage breakdown type input stage esd protection circuit of the present invention；
Fig. 3 is the circuit diagram of the anti-over-voltage breakdown type input stage esd protection circuit of the present invention；
Fig. 4 be the present invention anti-over-voltage breakdown type input stage esd protection circuit when IN ends carry out back stagnant dc sweeps,
IN1 ends, over-pressed detectable signal, the simulation result schematic diagram that reversely overvoltage detectable signal changes with time stagnant scanning voltage；
When Fig. 5 is chip normal work, IN ends, IN1 in the anti-over-voltage breakdown type input stage esd protection circuit of the present invention
The time dependent simulation result schematic diagram of voltage at end, INNER ends and over-pressed detectable signal ESD.
Specific embodiment
With reference to the accompanying drawings and examples the present invention is described in further detail.Following examples are used to illustrate this
It is bright, but can not be used for limiting the scope of the present invention.
Fig. 2 is the structural representation of the anti-over-voltage breakdown type input stage esd protection circuit of the present invention；The anti-over-voltage breakdown
Type input stage esd protection circuit includes diode (led) module, ballasting module, transmission gate module, DC voltage detecting module and electricity
Source clamp ESD protective circuit.
When the diode (led) module is for occurring ESD impact between pressure welding point and other chip pins, effectively by electrostatic
Electric charge is directed to releasing on path of designing, in chip normal work, there is provided the isolation between data path and power line.
The power clamp ESD protective circuit is in the power line VDDWith ground wire VSSBetween conduct ESD impact bring
Electric charge, meanwhile, in chip normal work, power clamp ESD protective circuit be in strict off state.
The DC voltage detecting module whether occur in pressure welding point over-pressed phenomenon for detecting, when there is over-pressed phenomenon,
DC voltage detecting module sends drive signal to transmission gate module and ballasting module, makes between pressure welding point and input stage phase inverter
Electrical connection disconnect, and make input stage phase inverter and power line VDDBetween resistance become big, when not there is over-pressed phenomenon,
DC voltage detecting module sends the normal transmission that drive signal ensures data to transmission gate module and ballasting module.
The ballasting module, changes input stage phase inverter PMOS transistor M for dynamicpSource electrode and power line VDDIt
Between resistance, when an esd event occurs, increase input stage phase inverter PMOS transistor MpSource electrode and power line VDDBetween electricity
Resistance, it is ensured that electrostatic charge is released by the path of releasing for designing, in chip normal operating, significantly reduces input stage phase inverter
PMOS transistor MpSource electrode and power line VDDBetween resistance, it is ensured that voltage is unattenuated.
The transmission gate module, is broken when over-voltage events occur for the signal sent according to DC voltage detecting module
The electrical connection between the gate oxide of pressure welding point and input stage phase inverter is opened, meanwhile, force the input voltage input stage phase inverter
Zero is biased to, in chip normal operating, it is ensured that the normal transmission of data.
Anti- over-voltage breakdown type input stage esd protection circuit proposed by the present invention is applied to advanced integrated circuit technology,
When the input of chip occurs the ESD impact of worst case, the electrical connection between input stage gate oxide and pressure welding point breaks
Open, and the grid voltage of input stage phase inverter is forced to be biased to zero level, meanwhile, the connection between input stage phase inverter and power line
Resistance becomes big, it is ensured that electrostatic charge is released from the path of releasing for designing, in chip normal operating, it is ensured that the normal biography of data
It is defeated.
Fig. 3 is the circuit diagram of the anti-over-voltage breakdown type input stage esd protection circuit of the present invention；The diode (led) module includes
Diode D1, diode D2.The diode D1Anode and the anti-over-voltage breakdown type input stage esd protection circuit pressure welding
Point is connected, the diode D1Negative electrode and the anti-over-voltage breakdown type input stage esd protection circuit power line VDDIt is connected；Institute
State diode D2Anode and the anti-over-voltage breakdown type input stage esd protection circuit ground wire VSSIt is connected, the diode D2
Negative electrode be connected with the pressure welding point of the anti-over-voltage breakdown type input stage esd protection circuit.
The power clamp ESD protective circuit includes resistance R, electric capacity C, PMOS transistor Mp1, nmos pass transistor Mn1、
Mbig、Mfb；One end of the resistance R, PMOS transistor MP1Source electrode, the nmos pass transistor MbigDrain electrode be all connected with
The power line VDD；The other end of the resistance R, one end of the electric capacity C, the nmos pass transistor MfbDrain electrode, described
PMOS transistor Mp1Grid be all connected with the nmos pass transistor Mn1Grid；The nmos pass transistor MfbGrid, described
PMOS transistor Mp1Drain electrode, the nmos pass transistor Mn1Drain electrode be all connected to the nmos pass transistor MbigGrid；Institute
State the other end of electric capacity C, the nmos pass transistor MfbSource electrode, the nmos pass transistor Mn1Source electrode, the nmos pass transistor
MbigSource grounding.
The DC voltage detecting module includes PMOS transistor Mp2, resistance R2, resistance R3, diode string, phase inverter
INV1、INV2、INV3；PMOS transistor Mp2Source electrode connect the pressure welding point, its grid passes through the resistance R2Connection
To the pressure welding point, PMOS transistor Mp2Drain electrode pass through the resistance R3It is connected to ground, PMOS transistor Mp2's
Drain electrode sequentially passes through output overvoltage detectable signal ESD after described phase inverter INV1, INV2 drive, and the over-pressed detectable signal is passed through
Reversely overvoltage detectable signal ESDX is exported after the phase inverter INV3 logic reversals；The company of described phase inverter INV1, INV2, INV3
The relation of connecing is：The input of the INV1 connects the drain electrode of PMOS transistor Mp2, and it is anti-phase that its outfan connects described second
The input of device INV2, the outfan of the second phase inverter INV2 connect the input of the 3rd phase inverter INV3, described
Pressure welding point voltage is powered for described phase inverter INV1, INV2, and the supply voltage is powered for the phase inverter INV3；The PMOS
Transistor Mp2The grid connection diode string of positive series connection successively anode, the minus earth of the diode string.
The ballasting module includes nmos pass transistor Mnb, PMOS transistor MpbAnd resistance R1；The nmos pass transistor Mnb
Grid driven by the reverse over-pressed detectable signal ESDX, PMOS transistor MpbGrid by it is described overvoltage detection letter
Number ESD is driven；The nmos pass transistor MnbDrain electrode, PMOS transistor MpbSource electrode, the resistance R1One end it is equal
Connect the power line VDD；The nmos pass transistor MnbSource electrode, PMOS transistor MpbDrain electrode, the resistance R1's
The other end is all connected with being input into PMOS transistor M in the phase inverter of polePSource electrode.Input pole phase inverter includes PMOS transistor Mp、
The nmos pass transistor Mn, PMOS transistor MpDrain electrode and the nmos pass transistor MnDrain electrode, internal circuit connection,
PMOS transistor MpGrid connect the nmos pass transistor MnGrid connection, the nmos pass transistor MnSource electrode connect
Meet the ground wire VSSConnection.
The transmission gate module includes PMOS transistor Mpt, nmos pass transistor Mnta, nmos pass transistor Mnt；The PMOS is brilliant
Body pipe Mpt, nmos pass transistor MntaGrid driven by the over-pressed detectable signal ESD, the nmos pass transistor MntGrid
Pole is driven by the reverse over-pressed detectable signal ESDX；PMOS transistor MptSource electrode, the nmos pass transistor Mnt's
Drain electrode is all connected with the pressure welding point；PMOS transistor MptDrain electrode, the nmos pass transistor MntSource electrode, the NMOS
Transistor MntaDrain electrode be all connected with the input of the input stage phase inverter；The nmos pass transistor MntaSource ground.
Preferably, the difference according to technique, the quantity of the diode of the diode string is 3-5.In Fig. 3, diode
String includes 4 diodes, i.e. D3、D4、D5、D6；The diode D3Anode connect PMOS transistor Mp2Grid, state
Diode D3Negative electrode connect the diode D4Anode, the diode D4Negative electrode connect the diode D5Anode,
The diode D5Negative electrode connect the diode D6Anode, the diode D6Minus earth.
Anti- over-voltage breakdown type input stage esd protection circuit proposed by the present invention is by the mistake in effectively detection input pressure welding point
Pressure phenomenon, when esd event occurs, disconnects the electrical connection between pressure welding point and input stage phase inverter gate oxide, and input
The input of level phase inverter is forced to be biased to zero, meanwhile, to input stage phase inverter to the company between power line using dynamic electric resistor
Connect mode, it is ensured that safety of the chip functions circuit in the case of the worst ESD impact, and ensure in chip normal operating, number
According to without decay.
By taking the integrated circuit technology of 65nm as an example, the normal working voltage of chip is 2.5V, and the gate oxide of transistor hits
Voltage is worn for 6.0V.When the esd event of worst case occurs, in Fig. 3, IN nodes can occur over-pressed phenomenon the very first time, this
When, in DC voltage detecting module, diode D3Anode be logic low with respect to the over-pressed signal at IN ends, this logic low electricity
After mean longitude crosses inverter drive, it is logic low that output signal ESD of final DC voltage detection circuit is logic high, ESDX, generation
Table has esd event in pressure welding point.The selection of the chain of inverters power supply signal in DC voltage detecting module is to ensure
Transistor M when esd event occurs, in transmission gate moduleptAnd MntCan complete switch off, in chip normal operating, transmission gate
Transistor M in moduleptAnd MntCan fully open.As shown in figure 3, when esd event occurs, transistor MptAnd MntIt is completely in
Off state, disconnects the electrical connection between the gate oxide and pressure welding point of input stage phase inverter, and now ESD impact is brought
Electric charge only by diode D1Release with power clamp ESD protective circuit, it is ensured that electrostatic charge does not enter the interior of chip
Portion.Meanwhile, transistor MntaInto conducting state, the input of input stage phase inverter is forced to be biased to zero, be further ensure that
The safety of input stage phase inverter gate oxide.
Further, when the esd event of worst case occurs, PMOS transistor M in input stage phase inverterpIn unlatching
State, now, if the direct power line V of its sourceDDIt is connected, then MpGate oxide can face over-voltage events, become and hit
The weakness worn.Anti- over-voltage breakdown type input stage esd protection circuit proposed by the present invention can effectively prevent the above-mentioned generation for puncturing, because
To be now placed in power line and MpBallasting module between source electrode is in big resistance states, in MpSource electrode and power line between shape
Into effective isolation.
In chip normal operating, ESD signals are logic low, ESDX signals are logic high, and now transmission gate module can be really
The normal transmission of data is protected, meanwhile, the transmission gate in ballasting module is also fully opened, itself and resistance R1Equivalent electric after parallel connection
Resistance very little, it is ensured that the decay of voltage transmission is less.
In the diagram, when IN signals are less than 4.9V, IN1 signals can follow the change of IN signals, and voltage signal is sent into core
Inside piece, when IN signals are more than 4.9V, ESD signal high jumps, ESDX signals jump low, and representative has over-voltage events to point out in pressure welding
Existing, now, IN1 signals are not followed by IN signal intensities, and are forced to be biased to zero, reached the effect that the present invention wants, together
When, in the descending reverse scan of IN signals, the low high jump critical voltage than before of jump of ESD signals is little, so can be with
After guaranteeing that electrostatic charge is more thoroughly released, data path is just reopened, and further ensures that the safety of chip functions circuit.
In addition, the respective element that the leaping voltage of ESD signals can change DC voltage detecting module according to different process requirements is big
It is little to be adjusted.
In Fig. 5, in chip normal work, ESD signals maintain very low level all the time, and IN signal energy normal transmissions are arrived
IN1 ends, while reverse transfer enters chip internal to INNER ends.
Embodiment of above is merely to illustrate the present invention, rather than limitation of the present invention.Although with reference to embodiment to this
It is bright to be described in detail, it will be understood by those within the art that, technical scheme is carried out various combinations,
Modification or equivalent, without departure from the spirit and scope of technical solution of the present invention, all should cover will in right of the invention
Ask in the middle of scope.
Claims (6)
1. a kind of anti-over-voltage breakdown type input stage esd protection circuit, including diode (led) module, power clamp ESD protective circuit, its
It is characterised by, also including ballasting module, transmission gate module and DC voltage detecting module；
When the diode (led) module is for occurring ESD impact between pressure welding point and other chip pins, effectively by electrostatic charge
Releasing on path of designing is directed to, it is in chip normal work, there is provided the isolation between data path and power line, described
Power line includes power line VDDWith ground wire VSS；
The power clamp ESD protective circuit is in power line VDDWith ground wire VSSBetween conduct the electric charge that brings of ESD impact, together
When, in chip normal work, power clamp ESD protective circuit is in strict off state；
The DC voltage detecting module whether occur in pressure welding point over-pressed phenomenon for detecting, when there is over-pressed phenomenon, direct current
Voltage detection module sends drive signal to transmission gate module and ballasting module, makes the electricity between pressure welding point and input stage phase inverter
Annexation disconnects, and makes input stage phase inverter and power line VDDBetween resistance become big, when not there is over-pressed phenomenon, direct current
Voltage detection module sends the normal transmission that drive signal ensures data to transmission gate module and ballasting module；The drive signal
Including over-pressed detectable signal ESD and anti-phase over-pressed detectable signal ESDX；
The ballasting module, changes input stage phase inverter PMOS transistor M for dynamicpSource electrode and power line VDDBetween
Resistance, when an esd event occurs, increases input stage phase inverter PMOS transistor MpSource electrode and power line VDDBetween resistance,
Guarantee that release path of the electrostatic charge by designing is released, in chip normal operating, significantly reduce input stage phase inverter
PMOS transistor MpSource electrode and power line VDDBetween resistance, it is ensured that voltage is unattenuated；
The transmission gate module, is broken when over-voltage events occur for the drive signal sent according to DC voltage detecting module
The electrical connection between the gate oxide of pressure welding point and input stage phase inverter is opened, meanwhile, force the input voltage input stage phase inverter
Zero is biased to, in chip normal operating, it is ensured that the normal transmission of data；
The ballasting module includes resistance R1, PMOS transistor Mpb, nmos pass transistor Mnb；The nmos pass transistor MnbGrid quilt
The anti-phase over-pressed detectable signal ESDX is driven, PMOS transistor MpbGrid driven by the over-pressed detectable signal ESD；
The nmos pass transistor MnbDrain electrode, PMOS transistor MpbSource electrode, the resistance R1One end be all connected with the power supply
Line VDD；The nmos pass transistor MnbSource electrode, PMOS transistor MpbDrain electrode, the resistance R1The other end be all connected with
PMOS transistor M in input stage phase inverterpSource electrode.
2. anti-over-voltage breakdown type input stage esd protection circuit according to claim 1, it is characterised in that the unidirectional current
Pressure detecting module includes PMOS transistor Mp2, resistance R2, resistance R3, diode string, phase inverter INV1, INV2, INV3；It is described
PMOS transistor Mp2Source electrode connection pressure welding point, its grid pass through the resistance R2It is connected to pressure welding point, the PMOS transistor
Mp2Drain electrode pass through the resistance R3It is connected to ground wire VSS, PMOS transistor Mp2The voltage signal of drain electrode sequentially passes through institute
Output overvoltage detectable signal ESD after phase inverter INV1, INV2 drive is stated, the over-pressed detectable signal ESD is through the phase inverter
Anti-phase over-pressed detectable signal ESDX is exported after INV3 logical inversions；The diode string includes the diode of positive series connection successively,
PMOS transistor Mp2Grid connect the anode of the diode string, the minus earth line V of the diode stringSS；It is described
Pressure welding point voltage is powered for described phase inverter INV1, INV2, power line VDDPower for the phase inverter INV3.
3. anti-over-voltage breakdown type input stage esd protection circuit according to claim 1, it is characterised in that the transmission gate
Module includes PMOS transistor Mpt, nmos pass transistor Mnta, nmos pass transistor Mnt；PMOS transistor Mpt, the NMOS it is brilliant
Body pipe MntaGrid driven by the over-pressed detectable signal ESD, the nmos pass transistor MntGrid by the anti-phase mistake
Pressure detectable signal ESDX is driven；PMOS transistor MptSource electrode, the nmos pass transistor MntDrain electrode be all connected with it is described
Pressure welding point；PMOS transistor MptDrain electrode, the nmos pass transistor MntSource electrode, the nmos pass transistor MntaDrain electrode
It is all connected with the input of the input stage phase inverter；The nmos pass transistor MntaSource ground line VSS。
4. anti-over-voltage breakdown type input stage esd protection circuit according to claim 1, it is characterised in that the diode
Module includes diode D1, diode D2；The diode D1Anode and anti-over-voltage breakdown type input stage ESD protection electricity
The pressure welding point on road is connected, the diode D1Negative electrode and the anti-over-voltage breakdown type input stage esd protection circuit power line
VDDIt is connected；The diode D2Anode and the anti-over-voltage breakdown type input stage esd protection circuit ground wire VSSIt is connected, it is described
Diode D2Negative electrode be connected with the pressure welding point of the anti-over-voltage breakdown type input stage esd protection circuit.
5. anti-over-voltage breakdown type input stage esd protection circuit according to claim 1, it is characterised in that the power supply pincers
Position esd protection circuit includes resistance R, electric capacity C, PMOS transistor Mp1, nmos pass transistor Mn1、Mbig、Mfb；The one of the resistance R
End, PMOS transistor MP1Source electrode, the nmos pass transistor MbigDrain electrode be all connected with the power line VDD；The resistance
The other end of R, one end of the electric capacity C, the nmos pass transistor MfbDrain electrode, PMOS transistor Mp1Grid connect
Meet the nmos pass transistor Mn1Grid；The nmos pass transistor MfbGrid, PMOS transistor Mp1Drain electrode, described
Nmos pass transistor Mn1Drain electrode be all connected to the nmos pass transistor MbigGrid；The other end of the electric capacity C, the NMOS
Transistor MfbSource electrode, the nmos pass transistor Mn1Source electrode, the nmos pass transistor MbigSource grounding line VSS。
6. anti-over-voltage breakdown type input stage esd protection circuit according to claim 2, it is characterised in that DC voltage is visited
According to different process conditions, selectable value is 3-5 to the number of diodes of the diode string surveyed in module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410461278.9A CN104253410B (en) | 2014-09-11 | 2014-09-11 | Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit |
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|---|---|---|---|
| CN201410461278.9A CN104253410B (en) | 2014-09-11 | 2014-09-11 | Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit |
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| Publication Number | Publication Date |
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| CN104253410A CN104253410A (en) | 2014-12-31 |
| CN104253410B true CN104253410B (en) | 2017-04-19 |
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| CN110311668B (en) * | 2019-07-05 | 2022-11-04 | 上海趣致网络科技有限公司 | Chip output pin forward overvoltage and reverse voltage protection circuit and method |
| CN112086946B (en) * | 2020-08-13 | 2024-03-19 | 珠海亿智电子科技有限公司 | High voltage resistant clamp circuit with alternating current detection and direct current detection |
| CN113761818B (en) * | 2021-11-09 | 2022-02-11 | 微龛(广州)半导体有限公司 | ESD simulation method and simulation circuit |
| CN114256825B (en) * | 2021-12-17 | 2023-09-19 | 中国科学院上海高等研究院 | Overvoltage protection circuit of energy autonomous wireless sensing node |
| CN116455371A (en) * | 2023-06-09 | 2023-07-18 | 深圳市锦锐科技股份有限公司 | Strengthen high anti-interference circuit of singlechip EFT |
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| JP3990352B2 (en) * | 2003-12-22 | 2007-10-10 | 株式会社東芝 | Semiconductor integrated circuit device |
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