CN116455371A - Strengthen high anti-interference circuit of singlechip EFT - Google Patents
Strengthen high anti-interference circuit of singlechip EFT Download PDFInfo
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- 238000007599 discharging Methods 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 32
- 238000001228 spectrum Methods 0.000 claims description 23
- 238000001514 detection method Methods 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- 238000001914 filtration Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 11
- 230000000737 periodic effect Effects 0.000 claims description 10
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- 230000006835 compression Effects 0.000 claims description 4
- 238000007906 compression Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 230000001052 transient effect Effects 0.000 abstract description 6
- 238000005728 strengthening Methods 0.000 abstract description 4
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- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
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- 230000002159 abnormal effect Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a high anti-interference circuit for strengthening the EFT of a singlechip, which comprises the following components: an input/output protection circuit, a power supply protection circuit and an EFT start control circuit; the power supply protection circuit is used for starting the input/output protection circuit and the power supply protection circuit according to the detected EFT interference event; the input/output protection circuit is used for protecting all input/output interfaces on the singlechip integrated circuit; the power supply protection circuit is used for carrying out grounding treatment on high-voltage or high-frequency interference signals on the working voltage of the single chip microcomputer integrated circuit through the low-resistance channel. The low-impedance discharging channel is adopted to safely discharge transient high current to prevent heat damage, and huge pulse voltage is clamped in a safe range to avoid damage to an internal working circuit due to voltage overload. Therefore, the physical failure and soft failure threshold of the microprocessor of the singlechip to EFT interference are improved.
Description
Technical Field
The invention relates to the technical field of single-chip microcomputer, in particular to an EFT (electronic flash) high-interference-resistance circuit for strengthening the single-chip microcomputer.
Background
With the continuous maturity of the internet of things technology, the idea of intelligent household appliances is gradually perceived by people, and under the catalysis of the large background of intelligent household appliances, product intellectualization has become the primary standard of the current household appliance industry development. Kitchen electric products and internet technology combine together, equipment in the kitchen links together, has become intelligent equipment with ordinary kitchen equipment, lets user experience high-tech life feel, and this kind of kitchen electric products with "intelligence+internet" as characteristics has overturned traditional house life theory, under the support of singlechip technique, can bring multiple intelligent kitchen solution for the family user of different demands, easily creates intelligent family quality life, satisfies people diversified demand.
However, in the process of applying the singlechip, there is an EFT interference event, and EFT (electrical fast transient pulse train) interference is a typical transient pulse interference, and EFT is a series of pulse trains, not a single pulse, and has the characteristics of large amplitude, short rise time, high repetition frequency and low energy. The influence on the circuit is larger, on one hand, pulse groups repeatedly appear, an accumulation effect can be generated at the input end of the circuit, and the amplitude of the disturbance level can finally exceed the noise margin of the circuit, so that the circuit is abnormal; on the other hand, the repetition frequency of the pulse group is high, the interval time of each interference pulse is shorter, when the first interference pulse is not disappeared yet, the second interference pulse is immediately followed, so that for the input capacitor in the circuit, the charge starts again when the discharge is not completed, thus the higher voltage is easy to reach, the normal operation of the circuit is influenced, and even the circuit is damaged.
Therefore, in the intelligent kitchen product, the influence of the EFT interference event on the control of the singlechip is considered, and the influence of the EFT interference event on the intelligent control system is reduced as much as possible.
Disclosure of Invention
The invention provides a high anti-interference circuit for enhancing the EFT of a singlechip, which solves the problems in the prior art.
The invention provides a high anti-interference circuit for strengthening the EFT of a singlechip, which comprises the following components: an input/output protection circuit, a power supply protection circuit and an EFT start control circuit;
the EFT starting control circuit is used for starting the input/output protection circuit and the power supply protection circuit according to the detected EFT interference event;
the input/output protection circuit is used for protecting all input/output interfaces on the singlechip integrated circuit; the power supply protection circuit is used for carrying out grounding treatment on high-voltage or high-frequency interference signals on the working voltage of the single chip microcomputer integrated circuit through the low-resistance channel.
Preferably, an input/output protection circuit and a power supply protection circuit are arranged on each input/output interface of the singlechip integrated circuit; all input and output protection circuits and power supply protection circuits are connected through an EFT starting control circuit;
when an EFT interference event occurs in one of the input/output interfaces, the EFT starting control circuit starts the input/output protection circuits and the power protection circuits which are connected to all the input/output interfaces, and anti-interference processing is carried out on the singlechip integrated circuit through all the input/output protection circuits and the power protection circuits.
Preferably, the input/output protection circuit includes: an input protection circuit, the input protection circuit comprising: diode D P1 、D N1 、D P2 And D N2 When in the normal operation mode D P1 、D N1 、D P2 And D N2 Reverse bias, which is equivalent to a large resistor, normally conducts signals on the input pins to the internal circuit;
diode D when positive disturbance pulse greater than VDD appears on input pin P1 And D P2 The method comprises the steps of conducting forward, discharging large current to VDD, clamping voltage on an input pin to voltage which is one diode forward conducting voltage larger than VDD, wherein the one diode forward conducting voltage is Von, and the value of a first clamping voltage is VDD+Von; VDD is the supply voltage;
d when negative voltage interference pulse smaller than VSS appears on the input pin N1 And D N2 Forward conduction, VSS is the voltage of the grounding terminal, high current is discharged to the grounding terminal, the voltage on the input pin is clamped to a voltage which is one diode forward conduction voltage smaller than VSS, and the formed second clamping voltage value is VSS-Von;
the gate voltage of the MOS tube in the input protection circuit is clamped between [ VSS-Von, VDD+Von ], so that the breakdown of a gate oxide layer of the input buffer caused by the overhigh gate-source voltage is prevented.
Preferably, the input-output protection circuit further includes an output protection circuit, and the output protection circuit includes: the primary voltage clamping output protection circuit discharges interference signal current by transmitting current smaller than a set current threshold value at an output part; no isolation resistor is provided between the output section and the output pin.
Preferably, the EFT start-up control circuit includes: an RC detection circuit, a POR latch circuit, an RC filter circuit, a Schmitt trigger and an NMOS clamping circuit;
the RC detection circuit is used for detecting a normal power-on process or an EFT interference event; the time constant of the RC detection circuit is larger than the normal power-on time and the time constant of the RC filter circuit, the RC detection circuit keeps a low level in the power-on process, the RC filter circuit and the Schmitt inverter are reset through the POR latch circuit, and the NMOS clamp circuit is locked to be in an off state until the normal power-on is completed; after normal power-on, the EFT starting control circuit detects an EFT interference event which occurs on a power supply, generates a direct-current IN signal through the RC filter circuit, and controls the on and off of the NMOS clamping circuit through comparison of the power supply voltage and the IN signal.
Preferably, the RC detection circuit includes: a first resistor, a first capacitor, a first NOT circuit and a second NOT circuit;
the first resistor is connected in series with the first capacitor, the input end of the first NOT gate circuit is connected between the first resistor and the first capacitor, the output end of the first NOT gate circuit is connected with the input end of the second NOT gate circuit, and the input end of the second NOT gate circuit is connected with the input end of the POR latch circuit.
Preferably, the POR latch circuit includes: the first NAND gate circuit, the second NAND gate circuit, the third NAND gate circuit, the second capacitor and the third capacitor;
the first input end of the first NAND gate circuit is connected with the output end of the second NAND gate circuit and the second capacitor, and the second input end of the first NAND gate circuit is connected with the output end of the RC detection circuit; the output end of the first NAND gate circuit is connected with the second input end of the second NAND gate circuit and the third capacitor, the first input end of the second NAND gate circuit is connected with the input end of the third NAND gate circuit, and the output end of the third NAND gate circuit is connected with the input end of the RC filter circuit.
Preferably, the RC filter circuit includes: the first field effect transistor, the second resistor and the fourth capacitor;
the output end of the POR latch circuit is connected with the grid electrode of the first field effect transistor, and the source electrode of the first field effect transistor is connected with the fourth capacitor and the input end of the Schmitt trigger; and the grid electrode of the second field effect tube is connected with a feedback node of the Schmidt trigger, the source electrode of the second field effect tube is connected with the second resistor, and the second resistor is connected with the fourth capacitor in series.
Preferably, the schmitt trigger includes: a flip-flop, a fourth NOT circuit and a fifth NOT circuit;
the output end of the trigger is connected with the input end of a fourth NOT gate circuit, the output end of the fourth NOT gate circuit is connected with the input end of a fifth NOT gate circuit, and the output end of the fifth NOT gate circuit is connected with the NMOS clamping circuit.
A feedback node of the schmitt trigger between the fourth and fifth not gates; the output end of the RC filter circuit is used for generating a direct-current IN signal, and the Schmidt trigger is used for controlling the on and off of the NMOS clamping circuit through the comparison of the power supply voltage of the feedback node and the IN signal.
Preferably, the system further comprises a digital filter for filtering the EFT interference signal, the digital filter comprising:
the frequency domain expansion module is used for carrying out frequency domain expansion on the EFT interference signal to obtain a frequency spectrum;
the spectrum compression module is used for squaring each frequency spectrum, and the original frequency spectrum is compressed;
the high-frequency band-stop filter setting module is used for multiplying the compressed frequency spectrum by a constant, compressing the EFT interference signal and moving the EFT interference signal to a high-frequency end at the same time, and setting a high-frequency band-stop filter;
and the filtering module is used for dividing the signal which normally passes through the high-frequency band-stop filter by a constant in the frequency domain, squaring the signal to obtain the frequency of the recovered signal, and filtering the periodic interference signal in the signal.
Compared with the prior art, the invention has the following advantages:
the invention provides a high anti-interference circuit for strengthening the EFT of a singlechip, which comprises the following components: an input/output protection circuit, a power supply protection circuit and an EFT start control circuit; the EFT starting control circuit is used for starting the input/output protection circuit and the power supply protection circuit according to the detected EFT interference event; the input/output protection circuit is used for protecting all input/output interfaces on the singlechip integrated circuit; the power supply protection circuit is used for carrying out grounding treatment on high-voltage or high-frequency interference signals on the working voltage of the single chip microcomputer integrated circuit through the low-resistance channel. The low-impedance discharging channel is adopted to safely discharge transient high current to prevent heat damage, and huge pulse voltage is clamped in a safe range to avoid damage to an internal working circuit due to voltage overload. The physical failure and soft failure threshold values of the microprocessor of the singlechip on EFT interference are improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a schematic diagram of an EFT-enhanced high-immunity circuit of a single-chip microcomputer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an input/output protection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an EFT boot control circuit according to an embodiment of the invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
Referring to fig. 1, the embodiment of the invention provides a reinforced single-chip microcomputer EFT high anti-interference circuit, which comprises: an input/output protection circuit, a power supply protection circuit and an EFT start control circuit;
the EFT starting control circuit is used for starting the input/output protection circuit and the power supply protection circuit according to the detected EFT interference event;
the input/output protection circuit is used for protecting all input/output interfaces on the singlechip integrated circuit; the power supply protection circuit is used for carrying out grounding treatment on high-voltage or high-frequency interference signals on the working voltage of the single chip microcomputer integrated circuit through the low-resistance channel.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is an input/output protection circuit, a power supply protection circuit and an EFT starting control circuit; the power supply protection circuit is used for starting the input/output protection circuit and the power supply protection circuit according to the detected EFT interference event; the input/output protection circuit is used for protecting all input/output interfaces on the singlechip integrated circuit; the power supply protection circuit is used for carrying out grounding treatment on high-voltage or high-frequency interference signals on the working voltage of the single chip microcomputer integrated circuit through the low-resistance channel.
The EFT interference eventually bleeds out to ground through the capacitance of the circuit board or chassis to ground, and if there are many signal connections to the device and the outside, these signal ports can be paths for the EFT interference bleeds out.
The solution adopted in this embodiment is to ensure that there is a suitable low-resistance bypass to introduce EFT current into the power or ground line. Specifically, the pre-stage I/O protection prevents most of interference current from flowing into the I/O and the internal circuit by limiting the PAD voltage to a fixed value, so that the I/O or the internal circuit is disabled; the power protection is mainly to rapidly detect high voltage or high frequency interference signals on VDD, so that a low-resistance path from VDD to VSS is provided before the circuit is damaged by high voltage generated by EFT, and large current is rapidly discharged to the ground. VDD denotes a power supply voltage, and VSS denotes a ground terminal voltage.
The beneficial effects of the technical scheme are as follows: the scheme provided by the embodiment adopts a low-impedance discharging channel to safely discharge transient high current so as to prevent heat damage, and clamps huge pulse voltage in a safe range so as to prevent an internal working circuit from being damaged due to voltage overload. The physical failure and soft failure threshold values of the microprocessor of the singlechip on EFT interference are improved.
In another embodiment, an input/output protection circuit and a power supply protection circuit are arranged on each input/output interface of the singlechip integrated circuit; all input and output protection circuits and power supply protection circuits are connected through an EFT starting control circuit;
when an EFT interference event occurs in one of the input/output interfaces, the EFT starting control circuit starts the input/output protection circuits and the power protection circuits which are connected to all the input/output interfaces, and anti-interference processing is carried out on the singlechip integrated circuit through all the input/output protection circuits and the power protection circuits.
The working principle and the beneficial effects of the technical scheme are as follows: the scheme adopted by the embodiment is that an input/output protection circuit and a power supply protection circuit are arranged on each input/output interface of a singlechip integrated circuit; all input and output protection circuits and power supply protection circuits are connected through an EFT starting control circuit; when an EFT interference event occurs in one of the input/output interfaces, the EFT starting control circuit starts the input/output protection circuits and the power protection circuits which are connected to all the input/output interfaces, and anti-interference processing is carried out on the singlechip integrated circuit through all the input/output protection circuits and the power protection circuits.
The unidirectional I/O protection is combined with the power supply protection, so that the transient pulse protection of the I/O unit can be realized. While such a single circuit may already provide EFT protection for the entire chip, the large resistance parasitic on the power bus may cause non-uniform distribution of the voltage. Since the current in the EFT event can reach several amperes, a large voltage drop occurs across the parasitic resistance of even a few ohms, which does not provide enough bias for the NMOS, and thus does not function as a protection for the circuit. Therefore, it is practical to split the circuit into a number of circuits, distributed across each I/O cell, and only one start-up circuit is required. The total area of the plurality of small clamping circuits is equal to that of a single large clamping circuit, so that the area of the protection circuit can be greatly reduced under the condition of not reducing the EFT protection performance, and the consistency of all ports can be obtained.
The I/O units are located on the periphery of the whole chip, and the ring formed by all peripheral I/O units is called PARING. All protection circuits and devices are distributed in each I/O unit and are connected through four buses of the whole chip. When an EFT event occurs on a PAD of a chip, not only the EFT protection unit in the PAD is active, but all the protection units of the whole chip are co-active, so that the protection of the whole chip is realized, and the protection is smaller with the distance from the PAD.
In another embodiment, referring to fig. 2, the input/output protection circuit includes: an input protection circuit, the input protection circuit comprising: diode D P1 、D N1 、D P2 And D N2 When in the normal operation mode D P1 、D N1 、D P2 And D N2 Reverse bias, which is equivalent to a very large resistor, normally conducts signals on the input pins to the internal circuit;
diode D when positive disturbance pulse greater than VDD appears on input pin P1 And D P2 The method comprises the steps of conducting forward, discharging large current to VDD, clamping voltage on an input pin to voltage which is one diode forward conducting voltage larger than VDD, wherein the one diode forward conducting voltage is Von, and the value of a first clamping voltage is VDD+Von; VDD is the supply voltage;
when the input pinD when negative voltage interference pulse smaller than VSS appears N1 And D N2 Forward conduction, VSS is the voltage of the grounding terminal, high current is discharged to the grounding terminal, the voltage on the input pin is clamped to a voltage which is one diode forward conduction voltage smaller than VSS, and the formed second clamping voltage value is VSS-Von; the grid voltage of the MOS tube in the input protection circuit is clamped at [ VSS-Von, VDD+Von ]]And prevents breakdown of the gate oxide layer of the input buffer due to an excessively high gate-source voltage.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that the input/output protection circuit comprises: an input protection circuit, the input protection circuit comprising: diode D P1 、D N1 、D P2 And D N2 When in the normal operation mode D P1 、D N1 、D P2 And D N2 Reverse bias, which is equivalent to a very large resistor, normally conducts signals on the input pins to the internal circuit; diode D when positive disturbance pulse greater than VDD appears on input pin P1 And D P2 The forward conduction is carried out, large current is discharged to the VDD, the voltage on the input pin is clamped to a voltage which is one diode forward conduction voltage larger than the VDD, the value of the formed first clamping voltage is VDD+Von, the upper limit value of clamping is the upper limit value, and overvoltage or large current is prevented from entering an internal circuit; d when negative voltage interference pulse smaller than VSS appears on the input pin N1 And D N2 Forward conduction, namely discharging large current to VSS, clamping the voltage on an input pin to a diode forward conduction voltage smaller than VSS, and forming a second clamping voltage value which is VSS-Von and is a value bit clamping lower limit value; the gate voltage of the MOS transistor in the input protection circuit is clamped at [ VSS-Von, VDD+Von ]]And prevents breakdown of the gate oxide layer of the input buffer due to an excessively high gate-source voltage.
The beneficial effects of the technical scheme are as follows: the scheme provided by the embodiment is used for the I/O protection circuit, the most industrially used diode is a diode working in a Non-snap back region, the diode is the simplest but very effective protection device, and the diode is used as the protection device, so that the obvious advantages are achieved: the diode normally works in a forward bias area, has small on resistance and can discharge larger current; the circuit is in a reverse cut-off state in a normal working mode, so that the normal working of the circuit is not influenced; only the junction capacitance of the diode, the response speed is the fastest; the trigger voltage can be changed in series; the discharge capacity of the diode in unit area is relatively strong; any process is supported without the need for additional reticles.
In another embodiment, the input-output protection circuit further includes an output protection circuit, the output protection circuit including: the voltage clamping output protection circuit of the first stage discharges most of current when the output part transmits the current as small as possible; no isolation resistor of any form is provided between the output section and the output pin.
In another embodiment, referring to fig. 3, the EFT start-up control circuit includes: an RC detection circuit, a POR latch circuit, an RC filter circuit, a Schmitt trigger and an NMOS clamping circuit;
the RC detection circuit is used for detecting a normal power-on process or an EFT interference event; the time constant of the RC detection circuit is larger than the normal power-on time and the time constant of the RC filter circuit, the RC detection circuit keeps a low level in the power-on process, the RC filter circuit and the Schmitt inverter are reset through the POR latch circuit, and the NMOS clamp circuit is locked to be in an off state until the normal power-on is completed; after normal power-on, the EFT starting control circuit detects an EFT interference event which occurs on a power supply, generates a direct-current IN signal through the RC filter circuit, and controls the on and off of the NMOS clamping circuit through comparison of the power supply voltage and the IN signal.
In another embodiment, referring to fig. 3, the RC detection circuit includes: a first resistor R1, a first capacitor C1, a first not gate T1 and a second not gate T2;
the first resistor R1 is connected with the first capacitor in series with the first capacitor C1, the input end of the first NOT gate circuit T1 is connected between the first resistor R1 and the first capacitor C1, the output end of the first NOT gate circuit T1 is connected with the input end of the second NOT gate circuit T2, and the input end of the second NOT gate circuit T2 is connected with the input end of the POR latch circuit.
In another embodiment, referring to fig. 3, the POR latch circuit includes: the first NAND gate circuit P1, the second NAND gate circuit P2, the third NAND gate circuit T3, the second capacitor C4 and the third capacitor C3;
the first input end of the first NAND gate circuit P1 is connected with the output end of the second NAND gate circuit P2 and the second capacitor C4, and the second input end of the first NAND gate circuit P1 is connected with the output end of the RC detection circuit; the output end of the first NAND gate circuit P1 is connected with the second input end of the second NAND gate circuit P2 and the third capacitor C3, the first input end of the second NAND gate circuit P2 is connected with the input end of the third NAND gate circuit T3, and the output end of the third NAND gate circuit T3 is connected with the input end of the RC filter circuit.
In another embodiment, referring to fig. 3, the RC filter circuit includes: the first field effect transistor M1, the second field effect transistor M2, the second resistor R2 and the fourth capacitor C2;
the output end of the POR latch circuit is connected with the grid electrode of the first field effect transistor M1, and the source electrode of the first field effect transistor M1 is connected with the fourth capacitor and the input end of the Schmitt trigger; the grid electrode of the second field effect tube M2 is connected with a feedback node of the Schmitt trigger, the source electrode of the second field effect tube M2 is connected with the second resistor R2, and the second resistor R2 is connected with the fourth capacitor C2 in series.
In another embodiment, referring to fig. 3, the schmitt trigger includes: a flip-flop, a fourth not gate T4 and a fifth not gate T5;
the output end of the trigger is connected with the input end of a fourth NOT circuit T4, the output end of the fourth NOT circuit T4 is connected with the input end of a fifth NOT circuit T5, and the output end of the fifth NOT circuit T5 is connected with the NMOS clamping circuit.
A feedback node of the schmitt trigger between the fourth and fifth not gates; the output end of the RC filter circuit is used for generating a direct-current IN signal, and the Schmidt trigger is used for controlling the on and off of the NMOS clamping circuit through the comparison of the power supply voltage of the feedback node and the IN signal.
It should be noted that, the normal power supply is powered up from 0V to 5.5V, the rising time is 3.4us, and the rising time is 10us after a period of time from 5.5V to 11.6V, so as to embody the normal power-up process and the EFT interference event.
When the power is normally on, the RC detection circuit detects the power-on edge, the POR latch circuit latches the state at the moment, the grid electrode of the first field effect transistor M1 is a POR node, the signal of the POR node is low level, the source electrode of the first field effect transistor M1 is an RC_EN node, and the RC_EN node follows the power supply voltage at the moment. When the power supply voltage VDD is stabilized, the signal of the POR node is high, the node rc_en becomes a high-resistance node, and the RC filter circuit becomes a low-pass filter, which functions to convert the interference signal into a constant reference level value. At this time, IN is VDD level, the output of the flip-flop is inv_out node, the inv_out node is still low level, the output of the fifth not gate T5 is trigger node, the trigger node is low level, and the NMOS transistor IN the NMOS clamp circuit is turned off.
When there is a jump IN the voltage on the power supply VDD, the schmitt will flip if the voltage level on VDD is sufficiently higher than the constant voltage level at the IN point (this value is the flip-level of the schmitt trigger design, here about 8.6V). When VDD reaches 8.6V, the trigger node becomes high level, and the load NMOS is turned on, thereby providing a low-impedance high-current bleed path from VDD to VSS and having a voltage clamping effect on VDD and VSS inside, thereby effectively protecting the internal circuit. When the VDD is reduced to a certain value, the inv_out node is also reduced along with the VDD, so that the trigger node is pulled down, the load NMOS tube is turned off, the VDD is gradually increased, and the process is repeated. That is, as soon as the VDD voltage exceeds 8.6v, the nmos transistor is turned on, and the VDD voltage is pulled down, thereby protecting the internal circuit.
The EFT protection circuit has strong protection capability for EFT pulse interference signals.
In another embodiment, the method further includes a digital filter for filtering the EFT interference signal, the digital filter including:
the frequency domain expansion module is used for carrying out frequency domain expansion on the EFT interference signal to obtain a frequency spectrum;
the spectrum compression module is used for squaring each frequency spectrum, and the original frequency spectrum is compressed;
the high-frequency band-stop filter setting module is used for multiplying the compressed frequency spectrum by a constant, compressing the EFT interference signal and moving the EFT interference signal to a high-frequency end at a long distance, and setting a high-frequency band-stop filter;
and the filtering module is used for dividing the signal which normally passes through the high-frequency band-stop filter by a constant in a frequency domain, squaring the signal, recovering the signal frequency and filtering the periodic interference signal in the signal.
The working principle and the beneficial effects of the technical scheme are as follows: the scheme adopted by the embodiment further comprises a digital filter, wherein the digital filter is used for filtering the EFT interference signal and comprises: the frequency domain expansion module is used for carrying out frequency domain expansion on the EFT interference signal to obtain a frequency spectrum; the spectrum compression module is used for squaring each frequency spectrum, and the original frequency spectrum is compressed; the high-frequency band-stop filter setting module is used for multiplying the compressed frequency spectrum by a constant, compressing the EFT interference signal and moving the EFT interference signal to a high-frequency end at a long distance, and setting a high-frequency band-stop filter; and the filtering module is used for dividing the signal which normally passes through the high-frequency band-stop filter by a constant in a frequency domain, squaring the signal, recovering the signal frequency and filtering the periodic interference signal in the signal.
Electromagnetic pulse interference can make the singlechip unable to execute a given program, and cause the phenomena of singlechip dead halt and the like in severe cases. Electromagnetic pulse interference can be divided into periodic interference and aperiodic interference in form, and the traditional electromagnetic interference protection method generally adopts hardware protection, namely adopts hardware shielding and circuit structure change to improve anti-interference capability, can effectively inhibit periodic conduction interference of electromagnetic pulse and radiation interference from the outside, and is a main means of electromagnetic protection; however, the hardware protection measures have higher cost and complex structure and process, and although the shielding box outside the common single-chip microcomputer control system can shield part of interference after being coated with conductive paint and additionally provided with a conductive rubber pad, some frequency components are coupled into the shielding box to interfere the working operation of the single-chip microcomputer control system. Especially for non-periodic disturbances, the entrance locations of the interference coupling into the device are also highly random due to the randomness of the location and spectral distribution of the interference sources.
For periodic signals, digital filtering may be used for interference protection. Because the frequency spectrum of the periodic interference signal is generally located at the high-frequency end and is very wide, aliasing is likely to be generated between the frequency spectrum and the signal frequency, the bandwidth is reduced by moving and compressing the frequency spectrum of the periodic interference signal in the frequency domain, so that the design of the high-frequency band-stop filter is facilitated, and the quality factor of the high-frequency band-stop filter can be improved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. The utility model provides a strengthen singlechip EFT high anti-interference circuit which characterized in that includes: an input/output protection circuit, a power supply protection circuit and an EFT start control circuit;
the EFT starting control circuit is used for starting the input/output protection circuit and the power supply protection circuit according to the detected EFT interference event;
the input/output protection circuit is used for protecting all input/output interfaces on the singlechip integrated circuit; the power supply protection circuit is used for carrying out grounding treatment on high-voltage or high-frequency interference signals on the working voltage of the single chip microcomputer integrated circuit through the low-resistance channel.
2. The EFT-enhanced high-immunity circuit of claim 1, wherein,
an input/output protection circuit and a power supply protection circuit are arranged on each input/output interface of the singlechip integrated circuit; all input and output protection circuits and power supply protection circuits are connected through an EFT starting control circuit;
when an EFT interference event occurs in one of the input/output interfaces, the EFT starting control circuit starts the input/output protection circuits and the power protection circuits which are connected to all the input/output interfaces, and anti-interference processing is carried out on the singlechip integrated circuit through all the input/output protection circuits and the power protection circuits.
3. The high anti-interference circuit of claim 1, wherein the input/output protection circuit comprises: an input protection circuit, the input protection circuit comprising: diode D P1 、D N1 、D P2 And D N2 When in the normal operation mode D P1 、D N1 、D P2 And D N2 Reverse bias, which is equivalent to a large resistor, normally conducts signals on the input pins to the internal circuit;
diode D when positive disturbance pulse greater than VDD appears on input pin P1 And D P2 The method comprises the steps of conducting forward, discharging large current to VDD, clamping voltage on an input pin to voltage which is one diode forward conducting voltage larger than VDD, wherein the one diode forward conducting voltage is Von, and the value of a first clamping voltage is VDD+Von; VDD is the supply voltage;
d when negative voltage interference pulse smaller than VSS appears on the input pin N1 And D N2 Forward conduction, VSS is the voltage of the grounding terminal, high current is discharged to the grounding terminal, the voltage on the input pin is clamped to a voltage which is one diode forward conduction voltage smaller than VSS, and the formed second clamping voltage value is VSS-Von;
the gate voltage of the MOS transistor in the input protection circuit is clamped between [ VSS-Von, VDD+Von ].
4. The circuit of claim 1, wherein the input/output protection circuit further comprises an output protection circuit, the output protection circuit comprising: the primary voltage clamping output protection circuit discharges interference signal current by transmitting current smaller than a set current threshold value at an output part; no isolation resistor is provided between the output section and the output pin.
5. The EFT high anti-interference circuit of claim 1, wherein the EFT start control circuit comprises: an RC detection circuit, a POR latch circuit, an RC filter circuit, a Schmitt trigger and an NMOS clamping circuit;
the RC detection circuit is used for detecting a normal power-on process or an EFT interference event; the time constant of the RC detection circuit is larger than the normal power-on time and the time constant of the RC filter circuit, the RC detection circuit keeps a low level in the power-on process, the RC filter circuit and the Schmitt inverter are reset through the POR latch circuit, and the NMOS clamp circuit is locked to be in an off state until the normal power-on is completed; after normal power-on, the EFT starting control circuit detects an EFT interference event which occurs on a power supply, generates a direct-current IN signal through the RC filter circuit, and controls the on and off of the NMOS clamping circuit through comparison of the power supply voltage and the IN signal.
6. The reinforced single-chip EFT high anti-interference circuit as claimed in claim 5, wherein said RC detection circuit comprises: a first resistor, a first capacitor, a first NOT circuit and a second NOT circuit;
the first resistor is connected in series with the first capacitor, the input end of the first NOT gate circuit is connected between the first resistor and the first capacitor, the output end of the first NOT gate circuit is connected with the input end of the second NOT gate circuit, and the input end of the second NOT gate circuit is connected with the input end of the POR latch circuit.
7. The EFT high anti-interference circuit of claim 5, wherein said POR latch circuit comprises: the first NAND gate circuit, the second NAND gate circuit, the third NAND gate circuit, the second capacitor and the third capacitor;
the first input end of the first NAND gate circuit is connected with the output end of the second NAND gate circuit and the second capacitor, and the second input end of the first NAND gate circuit is connected with the output end of the RC detection circuit; the output end of the first NAND gate circuit is connected with the second input end of the second NAND gate circuit and the third capacitor, the first input end of the second NAND gate circuit is connected with the input end of the third NAND gate circuit, and the output end of the third NAND gate circuit is connected with the input end of the RC filter circuit.
8. The reinforced single-chip EFT high anti-interference circuit as claimed in claim 5, wherein said RC filter circuit comprises: the first field effect transistor, the second resistor and the fourth capacitor;
the output end of the POR latch circuit is connected with the grid electrode of the first field effect transistor, and the source electrode of the first field effect transistor is connected with the fourth capacitor and the input end of the Schmitt trigger; and the grid electrode of the second field effect tube is connected with a feedback node of the Schmidt trigger, the source electrode of the second field effect tube is connected with the second resistor, and the second resistor is connected with the fourth capacitor in series.
9. The reinforced single-chip EFT high anti-interference circuit as claimed in claim 5, wherein said Schmitt trigger comprises: a flip-flop, a fourth NOT circuit and a fifth NOT circuit;
the output end of the trigger is connected with the input end of a fourth NOT circuit, the output end of the fourth NOT circuit is connected with the input end of a fifth NOT circuit, and the output end of the fifth NOT circuit is connected with the NMOS clamping circuit;
a feedback node of the schmitt trigger between the fourth and fifth not gates; the output end of the RC filter circuit is used for generating a direct-current IN signal, and the Schmidt trigger is used for controlling the on and off of the NMOS clamping circuit through the comparison of the power supply voltage of the feedback node and the IN signal.
10. The EFT high anti-interference circuit of claim 1 further comprising a digital filter for filtering EFT interference signals, the digital filter comprising:
the frequency domain expansion module is used for carrying out frequency domain expansion on the EFT interference signal to obtain a frequency spectrum;
the spectrum compression module is used for squaring each frequency spectrum, and the original frequency spectrum is compressed;
the high-frequency band-stop filter setting module is used for multiplying the compressed frequency spectrum by a constant, compressing the EFT interference signal and moving the EFT interference signal to a high-frequency end at the same time, and setting a high-frequency band-stop filter;
and the filtering module is used for dividing the signal which normally passes through the high-frequency band-stop filter by a constant in the frequency domain, squaring the signal to obtain the frequency of the recovered signal, and filtering the periodic interference signal in the signal.
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