CN220544988U - Interference signal filtering circuit, fault protection circuit and battery management system - Google Patents

Abstract

The utility model discloses an interference signal filtering circuit, a fault protection circuit and a battery management system, wherein the interference signal filtering circuit comprises an RC network, a discharging circuit, a first signal input end for inputting a first signal and a first signal output end for outputting a second signal; the RC network comprises a first capacitor and a first resistor, and the first capacitor and the first resistor are connected in series between a first power end and a first grounding end of the interference signal filtering circuit; the discharging circuit comprises a first switch, a first end of the discharging circuit is connected with a first signal input end, a first potential point between the first capacitor and the first resistor is connected with a first signal output end, a second end of the discharging circuit is also connected with the first potential point, and a third end of the discharging circuit is connected with a first grounding end; the first signal is used for controlling the switching state of the first switch; when the first switch is turned on, the first capacitor discharges to the first ground terminal through the discharge circuit.

Description

Interference signal filtering circuit, fault protection circuit and battery management system

Technical Field

The utility model relates to the technical field of circuit design, in particular to an interference signal filtering circuit, a fault protection circuit and a battery management system.

Background

In the prior art, the mode of filtering the interference signals is to split the harmonic current with corresponding frequency through a passive filter or an active filter combining RC and operational amplifier, and the behavior mode is to provide a passive harmonic current bypass channel, namely to provide a bypass channel for pre-filtered harmonic waves, so as to realize purification filtering.

However, passive filters have the disadvantages of energy loss of signals in the passband, relatively obvious loading effect, and easy induction when using inductive elements, and active filters have the disadvantage that the passband range is limited by the bandwidth of the active devices (e.g., integrated operational amplifiers) and reliability is not as high as passive filters.

Disclosure of Invention

It is an object of the present utility model to provide an interference signal filtering circuit.

According to one aspect of the present utility model, there is provided an interference signal filtering circuit including an RC network, a discharging circuit, a first signal input terminal for inputting a first signal, and a first signal output terminal for outputting a second signal;

the RC network comprises a first capacitor and a first resistor, and the first capacitor and the first resistor are connected in series between a first power end and a first grounding end of the interference signal filtering circuit;

the discharging circuit comprises a first switch, a first end of the discharging circuit is connected with the first signal input end, a first potential point between the first capacitor and the first resistor is connected with the first signal output end, a second end of the discharging circuit is also connected with the first potential point, and a third end of the discharging circuit is connected with the first grounding end;

the first signal is used for controlling the switching state of the first switch; under the condition that the first switch is conducted, the first capacitor discharges to the first grounding end through the discharging circuit; and under the condition that the first switch is disconnected, the first power supply terminal charges the first capacitor, so that the second signal is a signal obtained by filtering interference signals in the first signal.

Optionally, the first end of the first resistor is connected to the first power supply end, the second end of the first resistor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first ground end.

Optionally, the discharging circuit is provided by a 555 timer, an input pin of the 555 timer is connected with the first signal input end, a discharging pin of the 555 timer is connected with the first potential point, and a grounding pin of the 555 timer is connected with the first grounding end.

Optionally, the circuit further comprises a logic or gate,

the threshold pin of the 555 timer is connected with the first potential point;

the first input end of the logic OR gate is connected with the first potential point, the second input end of the logic OR gate is connected with the output pin of the 555 timer, and the output end of the logic OR gate is connected with the first signal output end.

Optionally, the RC network further includes a second resistor, a first end of the second resistor is connected to the first potential point, and a second end of the second resistor is connected to a discharge pin of the 555 timer.

Optionally, the discharging circuit includes an inverter and an NPN triode, an input pin of the inverter is connected with the first signal input end, an output pin of the inverter is connected with a base electrode of the NPN triode, a collector electrode of the NPN triode is connected with the first potential point, and an emitter electrode of the NPN triode is connected with the first grounding end.

Optionally, the discharging circuit further includes a third resistor and a fourth resistor, the third resistor is connected between the base of the NPN triode and the output pin of the inverter, and the fourth resistor is connected between the base of the NPN triode and the first ground terminal.

According to a third aspect of the present disclosure, there is provided a fault protection circuit comprising a second capacitor, a rectifying circuit, an RS flip-flop, a reset signal input for receiving a reset signal, a fault signal input for inputting a first fault signal, a fault signal output for outputting a second fault signal, and an interference signal filtering circuit as described in the first aspect of the present disclosure;

the first end of the second capacitor is connected with the fault signal input end, the second end of the second capacitor is connected with the input end of the rectifying circuit, the output end of the rectifying circuit is connected with the first signal input end of the interference signal filtering circuit, the first signal output end of the interference signal filtering circuit is connected with the setting pin of the RS trigger, the reset signal input end is connected with the reset pin of the RS trigger, and the output pin of the RS trigger is connected with the fault signal output end.

Optionally, the fault protection circuit further comprises a delay circuit,

the input end of the delay circuit is connected with the reset signal input end, and the output end of the delay circuit is connected with the reset pin of the RS trigger.

According to a third aspect of the present disclosure, there is provided a battery management system comprising a first processing module, a second processing module, and a fault protection circuit according to the second aspect of the present disclosure,

the first processing module is connected with the fault signal input end of the fault protection circuit, and the second processing module is connected with the fault signal output end of the fault protection circuit;

the first processing module is configured to output a first fault signal to the fault signal input of the fault protection circuit, the first fault signal being an ac signal in case of a normal battery arrangement, being a dc signal in case of a fault of the battery arrangement,

the second processing module is configured to shut down if the second fault signal indicates a fault in the battery device.

The utility model has the technical effect that the interference signal of which the time width is lower than the set time in the first signal can be filtered by the interference signal filtering circuit. Furthermore, the bandwidth limitation of the active filtering is not limited, and the electromagnetic induction can be avoided without providing an inductance element.

Other features of the present utility model and its advantages will become apparent from the following detailed description of exemplary embodiments of the utility model, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description, serve to explain the principles of the utility model.

Fig. 1 is a schematic block diagram of an interference signal filtering circuit according to a first embodiment of the present utility model;

FIG. 2 is a schematic circuit diagram of an interference signal filtering circuit according to a second embodiment of the present utility model;

FIG. 3 is a schematic circuit diagram of an interference signal filtering circuit according to a third embodiment of the present utility model;

fig. 4 is a functional block diagram of a fault protection circuit according to a first embodiment of the present utility model;

fig. 5 is a functional block diagram of a fault protection circuit according to a second embodiment of the present utility model;

fig. 6 is a circuit schematic of a fault protection circuit according to a third embodiment of the present utility model;

fig. 7 is a functional block diagram of a battery management system according to an embodiment of the present utility model.

Detailed Description

Various exemplary embodiments of the present utility model will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present utility model unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the utility model, its application, or uses.

Techniques and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

< interference Signal Filter Circuit >

The present disclosure provides an interference signal filtering circuit. Fig. 1 is a schematic block diagram of an interference signal filtering circuit according to an embodiment of the present utility model.

As shown IN fig. 1, the interference signal filtering circuit 1000 may include an RC network 1100, a discharging circuit 1200, a first signal input terminal IN1 for inputting a first signal, and a first signal output terminal OUT1 for outputting a second signal.

The RC network 1100 may include a first capacitor 1110 and a first resistor 1120, where the first capacitor 1110 and the first resistor 1120 are connected in series between the first power supply terminal VCC1 and the first ground terminal GND1 of the interference signal filtering circuit 1000.

Specifically, a first end of the first resistor 1120 is connected to the first power source terminal VCC1, a second end of the first resistor 1120 is connected to a first end of the first capacitor 1110, and a second end of the first capacitor 1110 is connected to the first ground terminal GND 1. Alternatively, the first end of the first capacitor 1110 may be connected to the first power source end, the second end of the first capacitor 1110 may be connected to the first end of the first resistor 1120, and the second end of the first resistor 1120 may be connected to the first ground GND 1.

The interference signal filtering circuit is described below by taking the connection of the first end of the first resistor 1120 to the first power supply end VCC1, the connection of the second end of the first resistor 1120 to the first end of the first capacitor 1110, and the connection of the second end of the first capacitor 1110 to the first ground end GND1 as an example.

The discharging circuit 1200 may include a first switch, a first terminal of the discharging circuit 1200 may be connected to the first signal input terminal IN1, a first potential point P1 between the first resistor 1120 and the first capacitor 1110 may be connected to the first signal output terminal OUT1, a second terminal of the discharging circuit 1200 may be also connected to the first potential point P1, and a third terminal of the discharging circuit 1200 may be connected to the first ground terminal GND 1.

The first signal is used for controlling the switching state of the first switch. When the first switch is turned on, the first capacitor 1110 discharges to the first ground GND1 through the discharging circuit, and when the first switch is turned off, the first power supply VCC1 charges the first capacitor 1110, so that the second signal is a signal obtained by filtering the interference signal in the first signal.

The interference signal may be a low-level signal less than the set time in the case where the first signal is normally a high-level signal, and may be a high-level signal less than the set time in the case where the first signal is normally a high-level signal.

In this embodiment, the charging duration and the discharging duration of the first capacitor may be greater than or equal to the set duration.

In one embodiment of the present disclosure, in the case where the first signal is normally a high level signal, at this time, the first switch may be turned off, the first power supply terminal VCC1 charges the first capacitor 1110, and in the case where the first capacitor 1110 is fully charged, the second signal output by the signal output terminal OUT1 is also a high level signal. In the case that the low-level interference signal exists in the first signal, the first switch may be turned on, the first capacitor 1110 discharges to the first ground GND1 through the discharging circuit, and when the low-level interference signal disappears, the first capacitor 1110 is not yet discharged, and then, during the discharging process of the first capacitor 1110, the second signal output by the signal output terminal OUT1 is still a high-level signal.

In another embodiment of the present disclosure, in the case where the first signal is normally a low level signal, at this time, the first switch may be closed, the first capacitor 1110 discharges to the first ground GND1 through the discharging circuit, and in the case where the discharging of the first capacitor 1110 is completed, the second signal output from the signal output terminal OUT1 is also a low level signal. In the case where there is a high-level interference signal in the first signal, the first switch may be turned off, the first power supply terminal VCC1 charges the first capacitor 1110, and when the high-level interference signal disappears, the first capacitor 1110 is not yet charged, and then, during the charging process of the first capacitor 1110, the second signal output by the signal output terminal OUT1 is still a low-level signal.

By the interference signal filtering circuit of the embodiment, the interference signal with the time width lower than the set time in the first signal can be filtered. Furthermore, the bandwidth limitation of the active filtering is not limited, and the electromagnetic induction can be avoided without providing an inductance element.

In one embodiment of the present disclosure, as shown in fig. 2, the discharge circuit 1200 may be provided by a 555 timer 1210. The input pin TRIG of the 555 timer is connected to the first signal input terminal IN1, the discharge pin DIS of the 555 timer is connected to the first potential point P1, and the ground pin GND11 of the 555 timer is connected to the first ground terminal GND 1.

Further, the interference signal filtering circuit 1000 may further include a logic or gate 1300, 555, and a threshold pin THR of the timer 1210 is connected to the first potential point P1;

a first input terminal of the or gate 130 is connected to the first potential point P1, a second input terminal of the or gate 1300 is connected to the output pin OUT of the 555 timer 1210, and an output terminal of the or gate 1300 is connected to the first signal output terminal OUT1.

Still further, the power supply pin VCC of the 555 timer 1210 is connected to the first power supply terminal VCC1, the reset pin RST of the 555 timer 1210 is suspended, and the control pin CTRL of the 555 timer 1210 is connected to the first power supply terminal VCC 1.

On this basis, the RC network further comprises a second resistor 1130, a first end of the second resistor 1130 is connected to the first potential point P1, and a second end of the second resistor 1130 is connected to the discharge pin DIS of the 555 timer.

In the present embodiment, under normal conditions, the voltage of the first power supply terminal VCC1 is U0, and the voltage UI1 > 2/3U of the threshold pin THR of the 555 timer 1210 ₀ Voltage UI2 of input pin TRIG of 555 timer 1210<1/3U ₀ The output pin OUT of the 555 timer 1210 outputs a high level, so that the first input terminal of the or gate 130 inputs a logic high level, the NPN transistor inside is turned off, and the first power supply terminal VCC1 charges the first capacitor 1110 through the first resistor 1120 until the voltage across the first capacitor 1110 is equal to the voltage U0 of the first power supply terminal VCC1, so that the second input terminal of the or gate 1300 inputs a logic high level, and the output terminal of the or gate 1300 outputs a high level.

When the first signal changes from high level to low level or when there is an interference signal in the first signal which is normally high level, the first signal changes to low level, the voltage UI2 of the input pin TRIG of the 555 timer 1210 is more than 1/3U ₀ The output pin OUT of the 555 timer 1210 outputs a low level, the first input end of the logic or gate 1300 inputs a low level, at this time, the internal NPN triode is turned on, the first capacitor 1110 discharges through the NPN triode, and the voltage at two ends of the first capacitor 1110 drops, which is divided into two cases:

in the first case, the discharging time of the first capacitor 1110 is shorter than the set time, the voltage has not fallen to the TTL circuit input low level, which is equivalent to the logic or gate 1300 still inputting the logic high level, and finally the interference signal filtering circuit outputs the second signal with high level (in this case, the time length of the low level signal is shorter than the set time, which is the interference signal and should be filtered).

In the second case, the discharging time of the first capacitor 1110 exceeds the set time, and the capacitor voltage is low to TTL low level, so this corresponds to the logic or gate 1300 still inputting logic low level, and finally the interference signal filtering circuit outputs the second signal with low level (in this case, the time length of the low level signal is longer than the set time, and is not the interference signal).

In one embodiment, the voltage of the first power supply terminal VCC1 is U ₀ The capacitance of the first capacitor 1110 is C, the resistance of the first resistor 1120 is R1, the resistance of the second resistor 1130 is R2, the low level voltage of the logic OR gate 1300 is less than 0.8V, when the NPN triode in the 555 timer is turned on, the capacitor discharges the final voltage U _CS Is that

When the first capacitor 1110 is charged, the voltage Uc across the first capacitor 1110 isWhere t1 is the charging duration of the first capacitor 1110. When the first capacitor 1110 is discharged, the voltage Uc across the first capacitor 1110 isWhere t2 is the discharge duration of the first capacitor 1110. In order to obtain a set time t _d The voltage drop across the front capacitor 1110 is less than 0.8V, so +.>And U is _CS ≤0.8V。

The values of R1, R2 and C are calculated by the two inequalities, and then the values are calculated according to the requirement. It can be seen that the set time is set by changing the capacitance and resistance in RC discharge, i.e. the capacitance voltage is changed from U ₀ Time to TTL logic low.

In this embodiment, the signal is the or gate output TTL gate level at the time of final transfer, so the final output second signal has no energy loss relative to the first signal, and is not greatly delayed by the first capacitor.

In one example, for signal processing, logic correctness is ensured, the conduction condition of the switch tube has a margin, the value design of the resistor and the capacitor has a certain reserved amount,the threshold value is ensured to be larger than the critical value, and logic error conduction cannot occur. Therefore, the voltage U of the first power supply terminal VCC1 can be made ₀ Setting the time length t to be 5V _d =2μs, and the final voltage of capacitor discharge U _CS ＝0.5V≤0.8V。

On the basis, when the first capacitor 1110 is discharged, the voltage Uc across the first capacitor 1110 isThe range of values of R1, R2 and C can be calculated to meet the following conditions: r is R ₁ C＝3.3×10 ^-5 ，/>

IN another embodiment of the present disclosure, as shown IN fig. 3, the discharging circuit 1200 includes an inverter 1220 and an NPNNPN triode 1230, an input pin of the inverter 1220 is connected to the first signal input terminal IN1, an output pin of the inverter 1220 is connected to a base of the NPN triode 1230, a collector of the NPN triode 1230 is connected to the first potential point P1, and an emitter of the NPN triode 1230 is connected to the first ground terminal GND 1.

Further, the discharging circuit 1200 further includes a third resistor 1240 and a fourth resistor 1250, wherein the third resistor 1240 is connected between the base of the NPN transistor 1230 and the output pin of the inverter 1220, and the fourth resistor 1250 is connected between the base of the NPN transistor 1230 and the first ground GND.

By the circuit structure of the discharging circuit in this embodiment, the interference signal with the time width lower than the set time in the first signal can be filtered.

< Fault protection Circuit >

The present disclosure provides a fault protection circuit, as shown IN fig. 4, the fault protection circuit 4000 may include a second capacitor 4100, a rectifying circuit 4200, an RS flip-flop 4300, a RESET signal input terminal RESET1 for receiving a RESET signal, a fault signal input terminal IN2 for inputting a first fault signal, a fault signal output terminal OUT2 for outputting a second fault signal, and the interference signal filtering circuit 1000 according to any of the foregoing embodiments.

The first end of the second capacitor 4100 is connected to the fault signal input terminal IN2, the second end of the second capacitor 4100 is connected to the input terminal of the rectifying circuit 4200, the output terminal of the rectifying circuit 4200 is connected to the first signal input terminal IN1 of the interference signal filtering circuit 1000, the first signal output terminal OUT1 of the interference signal filtering circuit 1000 is connected to the set pin S of the RS flip-flop, the RESET signal input terminal RESET1 is connected to the RESET pin R of the RS flip-flop, and the output pin Q of the RS flip-flop is connected to the fault signal output terminal OUT2.

Further, as shown in fig. 5, the fault protection circuit 4000 further includes a delay circuit 4400. An input end of the delay circuit 4400 is connected with a RESET signal input end RESET1, and an output end of the delay circuit 4400 is connected with a RESET pin R of the RS flip-flop 4300.

IN one embodiment of the present disclosure, the fault signal input terminal IN2 is configured to be connected to the first processing module, such that the first processing module inputs the first fault signal to the fault signal input terminal IN 2. The first fault signal is an ac signal when the battery device is normal, and is a dc signal when the battery device is faulty.

Specifically, the dc signal may be a logic high level signal or a logic low level signal, and the ac signal may be a square wave signal, for example.

The level state in the case of the battery device being normal is opposite to the level state in the case of the battery device being failed by the second failure signal output from the failure protection circuit failure signal output terminal OUT2 of the present embodiment.

In one example, as shown in fig. 6, the rectifying circuit 4200 may include resistors 4201, 4202, 4204, 4208, 4211, npn transistors 4203, 4210, capacitors 4205, 4207, 4209, and diode 4206. Resistor 4201 is connected between the second terminal of second capacitor 4100 and the base of NPN transistor 4203, resistor 4202 is connected between the base of NPN transistor 4203 and second ground GND2 of fault protection circuit 4000, resistor 4204 is connected between the collector of N PN transistor 4203 and second power supply terminal VCC2 of fault protection circuit 4000, and the emitter of NPN transistor 4203 is connected to second ground GND 2. An anode of the diode 4206 is connected to a collector of the NPN transistor 4203, a resistor 4208 is connected between a cathode of the diode 4206 and a base of the NPN transistor 4210, a capacitor 4205 is connected between the anode of the diode 4206 and the second ground GND2, a resistor 4207 is connected between the cathode of the diode 4206 and the second ground GND2, and a capacitor 4209 is connected between the base of the NPN transistor 4210 and the second ground GND 2. The resistor 4211 is connected between the collector of the NPN transistor 4210 and the second power supply terminal VCC2, and the emitter of the NPN transistor 4210 is connected to the second ground terminal GND 2. An emitter of NPN transistor 4210 is connected to first signal input IN1 of interference signal filtering circuit 1000.

The RS flip-flop 4300 may include a logic nand gate 4301 and a logic nand gate 4302, where a first input terminal of the logic nand gate 4301 is used as a set pin S and connected to a first signal output terminal OUT1 of the interference signal filtering circuit 1000, a second input terminal of the logic nand gate 4301 is connected to an output terminal of the logic nand gate 4302, an output terminal of the logic nand gate 4301 is used as an output pin and connected to a first input terminal of the logic nand gate 4302, and a second input terminal of the logic nand gate 4302 is used as a RESET pin R and connected to a RESET signal input terminal RESET 1.

The delay circuit 4400 may include resistors 4401, 4402, 4404, 4405, 4407, 4408, capacitors 4409, 4410, an NPN transistor 4406, a logic nand gate 4403, the resistor 4401 connected between the RESET signal input terminal RESET1 and the second power supply terminal VCC2, the resistor 4402 connected between the RESET signal input terminal RESET1 and the first input terminal of the logic nand gate 4403, the first input terminal and the second input terminal of the logic nand gate 4403, the resistor 4405 connected between the output terminal of the logic nand gate 4403 and the base of the NPN transistor 4406, the resistor 4404 connected between the output terminal of the logic nand gate 4403 and the second ground terminal GND2, the resistor 4407 connected between the collector of the NPN transistor 4406 and the second power supply terminal VCC2, the emitter of the NPN transistor 4406 connected between the collector of the NPN transistor 4406 and the second ground terminal GND2, and the capacitor 4409 connected between the output terminal of the NPN transistor 4406 and the second ground terminal GND2 of the delay circuit 4400.

Further, the fault protection circuit 4000 may further include a resistor 4500, a capacitor 4600, a light emitting diode 4700, and a logic nand gate 4800, the resistor 4500 and the light emitting diode being connected in parallel between the output pin of the RS flip-flop 4300 and the second ground GND2, the capacitor 4600 being connected between the output pin of the RS flip-flop 4300 and the second ground GND2, the first input terminal and the second input terminal of the logic nand gate 4800 being connected, the first input terminal of the logic nand gate 4800 being further connected to the output pin of the RS flip-flop 4300, the output terminal of the logic nand gate 4800 being the fault signal output terminal OUT2 of the fault protection circuit 4000.

< Battery management System >

The present embodiment also provides a battery management system, as shown in fig. 7, the battery management system 7000 may include a first processing module 7100, a second processing module 7200, and a fault protection circuit 4000 according to any embodiment of the present disclosure.

The first processing module 7100 is connected to the fault signal input terminal IN2 of the fault protection circuit 4000, and the second processing module 7200 is connected to the fault signal output terminal OUT2 of the fault protection circuit 4000.

In one example, the first processing module 7100 can be an ARM processor and the second processing module 7200 can be a Digital Signal Processor (DSP).

The first processing module 7100 is configured to output a first fault signal, which is an ac signal in the case of a normal battery device and a dc signal in the case of a fault of the battery device, to the fault signal input terminal of the fault protection circuit 4000. In one example, the first fault signal is a square wave signal of a fixed frequency in the case of a normal battery device and other signals in the case of a fault in the battery device.

The second processing module 7200 is configured to be powered off if the second fault signal indicates a fault in the battery device.

Further, the second processing module 7200 may output a RESET signal to the RESET signal input terminal RESET1 of the fault protection circuit 4000 to RESET the RS flip-flop 4300 of the fault protection circuit 4000 in case of an abnormality of its own program operation.

Further, the second processing module 7200 may output a RESET signal to the RESET signal input terminal RESET1 of the fault protection circuit 4000 to RESET the RS flip-flop 4300 of the fault protection circuit 4000 in each start-up.

The embodiments described above mainly focus on differences from other embodiments, but it should be clear to a person skilled in the art that the embodiments described above may be used alone or in combination with each other as desired.

While certain specific embodiments of the utility model have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the utility model. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the utility model. The scope of the utility model is defined by the appended claims.

Claims (10)

1. The interference signal filtering circuit is characterized by comprising an RC network, a discharging circuit, a first signal input end and a first signal output end, wherein the first signal input end is used for inputting a first signal, and the first signal output end is used for outputting a second signal;

the RC network comprises a first capacitor and a first resistor, and the first capacitor and the first resistor are connected in series between a first power end and a first grounding end of the interference signal filtering circuit;

the discharging circuit comprises a first switch, a first end of the discharging circuit is connected with the first signal input end, a first potential point between the first capacitor and the first resistor is connected with the first signal output end, a second end of the discharging circuit is also connected with the first potential point, and a third end of the discharging circuit is connected with the first grounding end;

the first signal is used for controlling the switching state of the first switch; under the condition that the first switch is conducted, the first capacitor discharges to the first grounding end through the discharging circuit; and under the condition that the first switch is disconnected, the first power supply terminal charges the first capacitor, so that the second signal is a signal obtained by filtering interference signals in the first signal.

2. The jammer rejection circuit of claim 1, wherein a first end of the first resistor is connected to the first power supply terminal, a second end of the first resistor is connected to a first end of the first capacitor, and a second end of the first capacitor is connected to the first ground terminal.

3. The jammer rejection circuit of claim 2 wherein the discharge circuit is provided by a 555 timer, an input pin of the 555 timer is connected to the first signal input, a discharge pin of the 555 timer is connected to the first potential point, and a ground pin of the 555 timer is connected to the first ground.

4. The interference signal filtering circuit of claim 3, wherein the circuit further comprises a logic OR gate,

the threshold pin of the 555 timer is connected with the first potential point;

the first input end of the logic OR gate is connected with the first potential point, the second input end of the logic OR gate is connected with the output pin of the 555 timer, and the output end of the logic OR gate is connected with the first signal output end.

5. The jammer rejection circuit of claim 4, wherein the RC network further comprises a second resistor, a first end of the second resistor being connected to the first potential point, and a second end of the second resistor being connected to a discharge pin of the 555 timer.

6. The interference signal filtering circuit according to claim 2, wherein the discharging circuit comprises an inverter and an NPN triode, an input pin of the inverter is connected to the first signal input terminal, an output pin of the inverter is connected to a base of the NPN triode, a collector of the NPN triode is connected to the first potential point, and an emitter of the NPN triode is connected to the first ground terminal.

7. The jammer rejection circuit of claim 6, the discharge circuit further comprising a third resistor connected between the base of the NPN transistor and the output pin of the inverter and a fourth resistor connected between the base of the NPN transistor and the first ground.

8. A fault protection circuit comprising a second capacitor, a rectifying circuit, an RS flip-flop, a reset signal input for receiving a reset signal, a fault signal input for inputting a first fault signal, a fault signal output for outputting a second fault signal, and an interference signal filtering circuit according to any one of claims 1 to 7;

the first end of the second capacitor is connected with the fault signal input end, the second end of the second capacitor is connected with the input end of the rectifying circuit, the output end of the rectifying circuit is connected with the first signal input end of the interference signal filtering circuit, the first signal output end of the interference signal filtering circuit is connected with the setting pin of the RS trigger, the reset signal input end is connected with the reset pin of the RS trigger, and the output pin of the RS trigger is connected with the fault signal output end.

9. The fault protection circuit of claim 8, further comprising a delay circuit,

the input end of the delay circuit is connected with the reset signal input end, and the output end of the delay circuit is connected with the reset pin of the RS trigger.

10. A battery management system comprising a first processing module, a second processing module, and a fault protection circuit according to claim 8 or 9,

the first processing module is connected with the fault signal input end of the fault protection circuit, and the second processing module is connected with the fault signal output end of the fault protection circuit;

the first processing module is configured to output a first fault signal to the fault signal input of the fault protection circuit, the first fault signal being an ac signal in case of a normal battery arrangement, being a dc signal in case of a fault of the battery arrangement,

the second processing module is configured to shut down if the second fault signal indicates a fault in the battery device.