CN112086946B - High voltage resistant clamp circuit with alternating current detection and direct current detection - Google Patents
High voltage resistant clamp circuit with alternating current detection and direct current detection Download PDFInfo
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- CN112086946B CN112086946B CN202010812754.2A CN202010812754A CN112086946B CN 112086946 B CN112086946 B CN 112086946B CN 202010812754 A CN202010812754 A CN 202010812754A CN 112086946 B CN112086946 B CN 112086946B
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- 238000001514 detection method Methods 0.000 title claims abstract description 86
- 230000005669 field effect Effects 0.000 claims description 152
- 230000003068 static effect Effects 0.000 claims description 23
- 230000005611 electricity Effects 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 12
- 101150021503 Mesd gene Proteins 0.000 claims 10
- 238000010248 power generation Methods 0.000 claims 1
- 230000001960 triggered effect Effects 0.000 abstract description 6
- 238000007599 discharging Methods 0.000 abstract description 2
- 101150110971 CIN7 gene Proteins 0.000 description 10
- 101150110298 INV1 gene Proteins 0.000 description 10
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 10
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 8
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- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 7
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- 230000002159 abnormal effect Effects 0.000 description 1
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- 230000001066 destructive effect Effects 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
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- 238000004377 microelectronic Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
- G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
Abstract
The invention discloses a high-voltage-resistant clamping circuit with alternating current detection and direct current detection, which comprises a voltage division module, an alternating current detection module, a direct current detection module, a logic control module and an electrostatic discharge module. When the electrostatic discharge occurs, the voltage of the node ac_out is low, and the dc detection module is turned on and performs dc detection on the voltage on the PAD. If the voltage of PAD is higher than the set value V H Mesd1 and Mesd2 are turned on and bleed ESD current. During the discharging ESD, when the voltage of PAD is lower than the set safety value V L At this time, mesd2 is turned off, ending the discharge of ESD. The clamping circuit has a direct current detection function and has the advantage of being not easy to be triggered by the non-ESD condition. In addition, when the ESD triggers the circuit, the voltage of the PAD is not discharged too low, so that the circuit can still keep a normal working state when the PAD is attacked by the ESD, and besides, the circuit has the characteristic of high voltage resistance, realizes the working voltage resistance of 3.3V by using a 1.8V device, and has more flexible and wide application.
Description
Technical Field
The invention relates to the technical field of electrostatic protection circuits, in particular to a high-voltage-resistant clamping circuit with alternating current detection and direct current detection.
Background
When electronic components are manufactured, produced, assembled, tested, stored, handled, etc., static electricity can accumulate in the human body, instruments, storage equipment, etc., and even the electronic components themselves can accumulate electric charges. When an electrostatic source is in contact with other objects, there is a charge flow that creates potentially damaging voltages, currents and electromagnetic fields, as the instantaneous voltage of electrostatic discharge is very high, typically greater than a few kilovolts, so that such damage is destructive and permanent, causing the circuit to burn directly, which is an electrostatic discharge (ESD: electrostatic Discharge). Prevention of electrostatic damage is a first challenge in all IC designs and fabrication.
The clamp circuit plays a crucial role in the electrostatic protection circuit, with the continuous progress of the integrated circuit technology and the technological level, the smaller the transistor and the device size on the chip, the higher the integration level of the chip, the lower the working voltage of the device, and the voltage requirements of many applications are fixed, for example, the device of the 28nm technology can only bear 1.8V voltage, and many peripheral applications are still 3.3V, in the prior art, the invention patent with publication number CN110994574A proposes a high-voltage-resistant power supply clamp circuit, as shown in figure 1, the voltage-resistant problem is well solved, but the RC time constant of the clamp circuit is generally set to be hundreds of nanoseconds, and the disadvantage is that the clamp circuit is easy to be triggered by non-ESD events (for example, hundreds of nanoseconds of power-on speeds) by mistake; in addition, once the ESD bleeder fet is triggered, the voltage of the PAD is easily pulled very low. Therefore, in some special applications or special chip pins, such as special application requirements for a fast power supply power-up speed or open drain (open drain) pins, the clamp circuit is easily triggered by mistake to affect the normal working state or function of the chip. In the prior art, the patent publication No. CN107465180A proposes a clamping circuit with alternating current detection and direct current detection, as shown in fig. 2, the problem of easy false triggering is well solved, but the working voltage of the circuit cannot exceed the withstand voltage of a device, and the application is limited to a certain extent. Therefore, the design of the clamping circuit with more flexibility and wider application is of great significance to the development of the whole microelectronics.
Disclosure of Invention
In view of the above problems, the present invention provides a high voltage-resistant clamp circuit with ac detection and dc detection, where the clamp circuit structure not only can resist high voltage, but also can effectively prevent false triggering of non-ESD and excessive discharge after ESD triggering by using a method of ac detection and dc detection, so that the clamp circuit has more flexibility and wider application.
In order to solve the technical problems, the technical scheme of the invention is as follows:
the utility model provides a high voltage resistant clamp circuit with exchange detection and direct current detection, includes bleeder module, exchange detection module, direct current detection module, logic control module, static electricity discharge module, bleeder module connects PAD, ground, exchange detection module, direct current detection module and logic control module respectively, exchange detection module connects PAD, bleeder module and direct current detection module respectively, direct current detection module connects PAD, ground, bleeder module, exchange detection module and logic control module respectively, logic control module connects PAD, ground, bleeder module, direct current detection module and static electricity discharge module respectively, static electricity discharge module connects PAD, ground and logic control module respectively.
In some embodiments, the voltage dividing module includes a first field effect transistor and a second field effect transistor, where a source electrode of the first field effect transistor is connected to a PAD, a drain electrode of the second field effect transistor is connected to ground, a gate electrode of the first field effect transistor is shorted to the drain electrode, a gate electrode of the second field effect transistor is shorted to the drain electrode, a drain electrode of the first field effect transistor is connected to the source electrode of the second field effect transistor and connected to a 0.5VPAD line, and the voltage dividing module is connected to the ac detection module, the dc detection module, and the logic control module through the 0.5VPAD line.
In some embodiments, the AC detection module includes a first resistor and a first capacitor, where one end of the first resistor is connected to the PAD, the other end of the first resistor is connected to the first capacitor, the other end of the first capacitor is connected to the 0.5VPAD line, and a line ac_out is connected between the first resistor and the first capacitor and is connected to the dc detection module.
In some embodiments, the direct current detection module includes a third field effect tube, a fourth field effect tube, a fifth field effect tube, a sixth field effect tube, a seventh field effect tube, a second resistor, a third resistor, a fourth resistor and a fifth resistor, where a source of the third field effect tube is connected to a PAD, a gate of the third field effect tube is connected to the ac_out line, a drain of the third field effect tube is connected to a source of the fourth field effect tube, a gate of the fourth field effect tube is connected to the 0.5VPAD line, a drain of the fourth field effect tube is connected to one end of the second resistor, another end of the second resistor is connected to a drain of the fifth field effect tube and one end of the third resistor, another end of the third resistor is connected to a source of the fifth field effect tube, a gate of the sixth field effect tube and one end of the fourth resistor, another end of the fourth resistor is connected to another end of the PAD, a drain of the fifth field effect tube is connected to the control circuit, a drain of the seventh field effect tube is connected to the seventh field effect tube, another end of the seventh field effect tube is connected to the seventh field effect tube, and another end of the seventh field effect tube is connected to the seventh field effect tube.
In some embodiments, the logic control module includes a first inverter, a second inverter, a third inverter, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, and a voltage dividing submodule, where a power source terminal of the first inverter, a power source terminal of the second inverter, and a source terminal of the eighth field effect transistor are connected to the PAD, a ground terminal of the third inverter and a source terminal of the eleventh field effect transistor are grounded, a ground terminal of the first inverter, a ground terminal of the second inverter, a gate terminal of the ninth field effect transistor, a power source terminal of the third inverter, and a gate terminal of the tenth field effect transistor are connected to the 0.5VPAD line, an input terminal of the first inverter is connected to the input terminal of the second inverter, a source terminal of the tenth field effect transistor, and a source terminal of the electrostatic discharge module, an output terminal of the second inverter is connected to a gate terminal of the eighth field effect transistor, a drain terminal of the eighth field effect transistor is connected to a drain terminal of the ninth field effect transistor, a drain terminal of the ninth field effect transistor is connected to a drain terminal of the eighth field effect transistor, and a drain terminal of the tenth field effect transistor is connected to the drain terminal of the eighth field effect transistor.
In some embodiments, the voltage dividing submodule includes a sixth resistor and a seventh resistor, one end of the sixth resistor is connected with the drain electrode of the ninth field effect transistor, the other end of the sixth resistor is connected with the seventh resistor, the other end of the seventh resistor is connected with ground, and the input end of the third inverter is connected between the sixth resistor and the seventh resistor.
In some embodiments, the static discharge module includes a first static discharge tube and a second static discharge tube, the drain of the first static discharge tube is connected to the PAD, the source of the first static discharge tube is connected to the drain of the second static discharge tube, the source of the second static discharge tube is connected to ground, the gate of the first static discharge tube is connected to the output of the first inverter and the source of the tenth field effect tube, and the gate of the second static discharge tube is connected between the drain of the tenth field effect tube and the drain of the eleventh field effect tube.
In some embodiments, the first, second, third, fourth, eighth, ninth, and tenth field effect transistors are P-type field effect transistors, and the fifth, sixth, seventh, eleventh, first and second static discharge transistors are N-type field effect transistors.
In some embodiments, the voltage dividing module is two resistors connected in series or two field effect transistors connected in series.
In some embodiments, the voltage dividing sub-module is two resistors connected in series or two field effect transistors connected in series.
The beneficial effects of the invention are as follows: the clamping circuit has the characteristic of high voltage resistance, and can support the working voltage of 3.3V by using the 1.8V voltage-resistant device, and meanwhile, the clamping circuit also has a direct current detection function, and has the advantages of being not easy to trigger by mistake under the condition of non-ESD.
Drawings
The invention is further described below with reference to the drawings and examples.
FIG. 1 is a schematic diagram of a conventional high voltage tolerant power clamp circuit;
FIG. 2 is a schematic diagram of a prior art clamp circuit with AC detection and DC detection;
fig. 3 is a schematic diagram illustrating connection of a high voltage clamp circuit with ac detection and dc detection according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and the detailed description below, in order to make the objects, technical solutions and advantages of the present invention more clear and distinct. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the matters related to the present invention are shown in the accompanying drawings.
As shown in fig. 3, the embodiment provides a high voltage clamping circuit with ac detection and dc detection, which includes a voltage division module 100, an ac detection module 200, a dc detection module 300, a logic control module 400, and an electrostatic discharge module 500, wherein the voltage division module 100 is respectively connected with a PAD, a ground GND, the ac detection module 200, the dc detection module 300, and the logic control module 400, the ac detection module 200 is respectively connected with the PAD, the voltage division module 100, and the dc detection module 300, the dc detection module 300 is respectively connected with the PAD, the ground GND, the voltage division module 100, the ac detection module 200, and the logic control module 400, the logic control module 400 is respectively connected with the PAD, the ground GND, the voltage division module 100, the dc detection module 300, and the electrostatic discharge module 500 is respectively connected with the PAD, the ground GND, and the logic control module 400.
The voltage dividing module 100 includes a first fet M1 and a second fet M2, where a source of the first fet M1 is connected to a PAD, a drain of the second fet M2 is connected to a ground GND, a gate of the first fet M1 is shorted to the drain, a gate of the second fet M2 is shorted to the drain, a drain of the first fet M1 is connected to the source of the second fet M2, and a 0.5VPAD line is connected to the ac detection module 200, the dc detection module 300, and the logic control module 400 through the 0.5VPAD line.
In a preferred embodiment, the AC detection module 200 includes a first resistor R1 and a first capacitor C1, where one end of the first resistor R1 is connected to the PAD, the other end of the first resistor R1 is connected to the first capacitor C1, the other end of the first capacitor C1 is connected to the 0.5VPAD line, and a line ac_out is connected between the first resistor R1 and the first capacitor C1 and is connected to the dc detection module 300.
The preferred embodiment is provided, the DC detection module 300 includes a third fet M3, a fourth fet M4, a fifth fet M5, a sixth fet M6, a seventh fet M7, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5, where the source of the third fet M3 is connected to the PAD, the gate of the third fet M3 is connected to the ac_out line, the drain of the third fet M3 is connected to the source of the fourth fet M4, the gate of the fourth fet M4 is connected to the 0.5VPAD line, the drain of the fourth fet M4 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the drain of the fifth fet M5 and one end of the third resistor R3, the other end of the third resistor R3 is connected to the PAD, the other end of the third resistor R3 is connected to the fifth resistor M5, the drain of the seventh resistor R5 is connected to the fifth resistor M5, the drain of the seventh fet M7 is connected to the other end of the fifth resistor R5, the seventh resistor R5 is connected to the drain of the fifth fet M4, the seventh fet M5 is connected to the other end of the fifth resistor R5, and the fifth resistor R5 is connected to the other end of the fifth fet M7 is connected to the drain of the fifth fet M4, and the fifth fet M4 is connected to the fifth resistor R5 is connected to the other end of the fifth resistor R2.
The logic control module 400 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, and a voltage division sub-module 401, wherein the power source terminal of the first inverter INV1, the power source terminal of the second inverter INV2, and the source terminal of the eighth field effect transistor M8 are connected to the PAD, the ground terminal of the third inverter INV3, and the source terminal of the eleventh field effect transistor M11 are grounded GND, the ground terminal of the first inverter INV1, the ground terminal of the second inverter INV2, the gate terminal of the ninth field effect transistor M9, the power source terminal of the third inverter INV3, and the gate terminal of the tenth field effect transistor M10 are connected to the 0.5VPAD line, the input terminal of the first inverter INV1 is connected to the dc_out line, the output terminal of the first inverter INV1 is connected to the drain terminal of the second inverter INV2, the drain terminal of the tenth field effect transistor M10 is connected to the drain terminal of the eighth field effect transistor M11, the drain terminal of the eighth field effect transistor M10 is connected to the drain terminal of the eighth field effect transistor M3, the drain terminal of the eighth field effect transistor M10 is connected to the drain terminal of the eighth field effect transistor M11, and the drain terminal of the eighth field effect transistor M10 is connected to the drain terminal of the eighth field effect transistor M3.
In a preferred embodiment, the voltage dividing submodule 401 includes a sixth resistor R6 and a seventh resistor R7, one end of the sixth resistor R6 is connected to the drain of the ninth field effect transistor M9, the other end of the sixth resistor R6 is connected to the seventh resistor R7, the other end of the seventh resistor R7 is connected to the ground GND, and the input end of the third inverter INV3 is connected between the sixth resistor R6 and the seventh resistor R7.
There is provided a preferred embodiment, the electrostatic discharge module 500 includes a first electrostatic discharge tube Mesd1 and a second electrostatic discharge tube Mesd2, the drain electrode of the first electrostatic discharge tube Mesd1 is connected to the PAD, the source electrode of the first electrostatic discharge tube Mesd1 is connected to the drain electrode of the second electrostatic discharge tube Mesd2, the source electrode of the second electrostatic discharge tube Mesd2 is connected to the ground GND, the gate electrode of the first electrostatic discharge tube Mesd1 is connected to the output end of the first inverter INV1 and the source electrode of the tenth fet M10, and the gate electrode of the second electrostatic discharge tube Mesd2 is connected between the drain electrode of the tenth fet M10 and the drain electrode of the eleventh fet M11.
In a preferred embodiment, the first fet M1, the second fet M2, the third fet M3, the fourth fet M4, the eighth fet M8, the ninth fet M9, and the tenth fet M10 are P-type fets, and the fifth fet M5, the sixth fet M6, the seventh fet M7, the eleventh fet M11, the first electrostatic discharge tube Mesd1, and the second electrostatic discharge tube Mesd2 are N-type fets.
In the above embodiment, the voltage dividing module 100 may be two resistors connected in series or two field effect transistors connected in series, besides two field effect transistors of P type.
In the above embodiment, the voltage dividing submodule 401 may be two N-type field effect transistors connected in series or two P-type field effect transistors connected in series, in addition to two resistors connected in series.
Working principle: when the circuit works normally, if the voltage on the PAD is constant power supply voltage VDD, the output voltage of the voltage division module 100 is 0.5VDD, the voltage of the node AC_OUT is the voltage VDD on the PAD, the third field effect transistor M3 is cut off, the fourth resistor R4 pulls the gate voltage of the sixth field effect transistor M6 to a low level GND, the sixth field effect transistor M6 is cut off, the node DC_OUT of the direct current detection module 300 is pulled to a high level VDD by the fifth resistor R5, the input end voltage of the first inverter INV1 is the high level VDD, the output end is the low level 0.5VDD, the gate voltage of the first electrostatic discharge tube Mesd1 is 0.5VDD, the source and gate voltages of the tenth field effect transistor M10 are both 0.5VDD, and the tenth field effect transistor M10 is cut off; the input end of the second inverter INV2 is at a low level 0.5VDD, the output end is at a high level VDD, and the eighth fet M8 is turned off, so that the voltage at the series connection point of the sixth resistor R6 and the seventh resistor R7 is at a low level GND; the input end of the third inverter INV3 is at a low level GND, the output end of the third inverter INV3 is at a high level 0.5VDD, the eleventh field effect transistor M11 is turned on, the gate voltage of the second electrostatic discharge tube Mesd2 is pulled to be at the low level GND, and the second electrostatic discharge tube Mesd2 is turned off; in terms of voltage resistance, the gate voltage of the fourth field effect transistor M4 and the gate voltage of the ninth field effect transistor M9 are both 0.5VDD, so that low voltage GND is prevented from being transmitted to the drain electrode of the third field effect transistor M3 and the drain electrode of the eighth field effect transistor M8 respectively, and the voltage resistance risk of the third field effect transistor M3 and the eighth field effect transistor M8 is eliminated. The grid voltage of the seventh field effect tube M7 and the grid voltage of the first electrostatic discharge tube Mesd1 are both 0.5VDD, so that the high voltage VDD is prevented from being transmitted to the drain electrode of the sixth field effect tube M6 and the drain electrode of the second electrostatic discharge tube Mesd2, and the withstand voltage risk of the sixth field effect tube M6 and the second electrostatic discharge tube Mesd2 is eliminated. If the PAD is normally operated and a flipped digital logic signal or a power supply with a higher power-up speed is transmitted on the PAD, when the PAD is raised from 0V to VDD, the AC detection module 200 detects an AC voltage, the voltage of the node ac_out is 0.5VDD, the third fet M3 in the DC detection module 300 is turned on, the voltage division value of the fourth resistor R4 is about vdd×r4/(r2+r3+r4), but the voltage division value of the fourth resistor R4 is insufficient to turn on the sixth fet M6 because the voltage peak of the PAD is not large enough, the output node dc_out of the DC detection module is still high, the gate voltage of the first electrostatic discharge tube Mesd1 is 0.5VDD, the gate voltage of the second electrostatic discharge tube Mesd2 is low level GND, and the second electrostatic discharge tube Mesd2 is turned off, thereby effectively avoiding the abnormal situation caused by false triggering of the electrostatic discharge module 500.
When the electrostatic discharge occurs, the AC detection module 200 detects the ESD voltage on the PAD, the voltage of the node ac_out is low relative to the PAD, the third fet M3 in the dc detection module 300 is turned on, the voltage division value of the fourth resistor R4 is vesd×r4/(r2+r3+r4), where Vesd is the voltage on the PAD when the ESD occurs, the peak value of Vesd can reach tens of V generally, and if the Vesd voltage of the PAD is higher than the set value V H The voltage division value of the fourth resistor R4 is larger than the starting voltage of the sixth field effect transistor M6, the sixth field effect transistor M6 is started, the voltage of the node DC_OUT is low, so that the input end of the first inverter INV1 is low, the output end of the first inverter INV1 is high Vesd, the grid voltage of the first electrostatic discharge tube Mesd1 is high Vesd, the grid voltage of the tenth field effect transistor M10 is 0.5Vesd, and the tenth field effect transistor M10 is conducted; meanwhile, the input end of the second inverter INV2 is high level Vesd, the output end is low level 0.5Vesd, and the eighth field effect transistor M8 is conductive, so that the voltage of the serial connection point of the sixth resistor R6 and the seventh resistor R7 is about 0.5Vesd; the input end of the third inverter INV3 is at a high level 0.5Vesd, the output is at a low level GND, the eleventh fet M11 is turned off, and the gate voltage of the second electrostatic discharge tube Mesd2 is pulled to a high level Vesd by the drain of the tenth fet M10. At this time, the gate voltages of the first electrostatic discharge tube Mesd1 and the second electrostatic discharge tube Mesd2 are both at the high level Vesd, so that both electrostatic discharge tubes are turned on to discharge electrostatic current. Meanwhile, the drain electrode of the tenth field effect transistor M10 is connected to the gate electrode of the fifth field effect transistor M5, the fifth field effect transistor M5 is turned on, and the resistor R3 is shorted, so that the voltage division value vesd×r4/(r2+r4) of the fourth resistor R4 is further increased, and the turning on of the sixth field effect transistor M6 is promoted. The dc detection module 300 has a hysteresis function, i.e. when the second electrostatic discharge tube Mesd2 is turned on to discharge the ESD current, the voltage Vesd of the PAD gradually decreases, and when the voltage Vesd of the PAD is lower than the set safety value V L (V L <V H ) When the voltage division value vesdxr 4/(r2+r4) of the fourth resistor R4 is lower than the on voltage of the sixth fet M6, the logic of the node dc_out is changed from low to high, ending the discharging of ESD. On the other hand, after the AC detection module 200 detects the AC voltage, the voltage of the node ac_out gradually increases from low to high, when the voltage of the node ac_out increases to turn off the third fet M3, the fourth resistor R4 pulls the gate voltage of the sixth fet M6 to the low level GND, so that the sixth fet M6 is turned off, the node dc_out of the DC detection module 300 is pulled to high VDD by the fifth resistor R5, at this time, the output of the first inverter INV1 becomes the low level GND, the tenth fet M10 is turned off, the output of the second inverter INV2 becomes the high level GND, the eighth fet M8 is turned off, the input of the third inverter INV3 becomes the low level GND, the output becomes the high level 0.5VDD, the eleventh fet M11 turns on, and turns off the second electrostatic discharge tube Mesd2, and the discharge of ESD is terminated.
According to the working principle, the clamp circuit has the characteristic of high voltage resistance, the 1.8V voltage-resistant device can support the 3.3V working voltage, and meanwhile, the clamp circuit also has a direct current detection function, and has the advantages that the clamp circuit is not easily triggered by the condition of non-ESD, in addition, when the circuit is triggered by the ESD, the potential of the PAD is not pulled too low, so that the PAD can still work normally when the circuit is attacked by the ESD.
The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, and are not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the essence of the present invention are intended to be included within the scope of the present invention.
Claims (5)
1. The high-voltage-resistant clamping circuit with the alternating current detection and the direct current detection is characterized by comprising a voltage division module (100), an alternating current detection module (200), a direct current detection module (300), a logic control module (400) and an electrostatic discharge module (500), wherein the voltage division module (100) is respectively connected with a PAD (power generation device), a Ground (GND), the alternating current detection module (200), the direct current detection module (300) and the logic control module (400), the alternating current detection module (200) is respectively connected with the PAD, the Ground (GND), the voltage division module (100), the alternating current detection module (200) and the logic control module (400), the logic control module (400) is respectively connected with the PAD, the Ground (GND), the voltage division module (100), the direct current detection module (300) and the electrostatic discharge module (500), and the electrostatic discharge module (500) are respectively connected with the PAD, the Ground (GND) and the logic control module (400);
the voltage dividing module (100) comprises a first field effect tube (M1) and a second field effect tube (M2), wherein a source electrode of the first field effect tube (M1) is connected with PAD, a drain electrode of the second field effect tube (M2) is connected with Ground (GND), a grid electrode of the first field effect tube (M1) is in short circuit with the drain electrode, a grid electrode of the second field effect tube (M2) is in short circuit with the drain electrode, the drain electrode of the first field effect tube (M1) is connected with the source electrode of the second field effect tube (M2) and is connected with a 0.5VPAD circuit, and the voltage dividing module is connected with the alternating current detection module (200), the direct current detection module (300) and the logic control module (400) through the 0.5VPAD circuit;
the alternating current detection module (200) comprises a first resistor (R1) and a first capacitor (C1), one end of the first resistor (R1) is connected with a PAD, the other end of the first resistor is connected with the first capacitor (C1), the other end of the first capacitor (C1) is connected with the 0.5VPAD circuit, a circuit AC_OUT is connected between the first resistor (R1) and the first capacitor (C1), and the first resistor is connected with the direct current detection module (300);
the DC detection module (300) comprises a third field effect tube (M3), a fourth field effect tube (M4), a fifth field effect tube (M5), a sixth field effect tube (M6), a seventh field effect tube (M7), a second resistor (R2), a third resistor (R3), a fourth resistor (R4) and a fifth resistor (R5), wherein the source electrode of the third field effect tube (M3) is connected with a PAD, the grid electrode of the third field effect tube (M3) is connected with the AC_OUT circuit, the drain electrode of the third field effect tube (M3) is connected with the source electrode of the fourth field effect tube (M4), the grid electrode of the fourth field effect tube (M4) is connected with one end of the second resistor (R2), the other end of the second resistor (R2) is connected with the drain electrode of the fifth field effect tube (M5) and the grid electrode of the third resistor (R4), the other end of the fourth field effect tube (M4) is connected with the grid electrode of the fourth resistor (R4), the grid electrode of the fourth field effect tube (M4) is connected with the grid electrode of the fourth field effect tube (M4), the grid electrode of the fourth field effect tube (M4) is connected with the fourth field effect tube (R4) is connected with the grid electrode of the fourth field effect tube (R4), the drain electrode of the sixth field effect tube (M6) is connected with the source electrode of the seventh field effect tube (M7), the grid electrode of the seventh field effect tube (M7) is connected with the 0.5VPAD circuit, the drain electrode of the seventh field effect tube (M7) is connected with one end of the fifth resistor (R5), the other end of the fifth resistor (R5) is connected with a PAD, and a circuit DC_OUT is connected between the seventh field effect tube (M7) and the fifth resistor (R5) and is connected with the logic control module (400);
the logic control module (400) comprises a first inverter (INV 1), a second inverter (INV 2), a third inverter (INV 3), an eighth field effect transistor (M8), a ninth field effect transistor (M9), a tenth field effect transistor (M10), an eleventh field effect transistor (M11) and a voltage dividing submodule (401), wherein the power supply end of the first inverter (INV 1), the power supply end of the second inverter (INV 2) and the source of the eighth field effect transistor (M8) are connected to PAD, the ground end of the third inverter (INV 3) and the source of the eleventh field effect transistor (M11) are Grounded (GND), the gate of the first inverter (INV 1), the ground end of the second inverter (INV 2), the power supply end of the ninth field effect transistor (M9), and the gate of the tenth field effect transistor (M10) are connected to the 0.5VPAD line, the input end of the first inverter (INV 1) and the drain of the eighth field effect transistor (INV 2) are connected to the drain end of the eighth field effect transistor (M9), and the drain end of the output of the first inverter (INV 1) is connected to the drain of the eighth field effect transistor (M9), and the drain end of the eighth field effect transistor (M2) is connected to the drain end of the eighth field effect transistor (M9) The input end of the third inverter (INV 3) and the Ground (GND) are connected with the voltage dividing submodule (401), the output end of the third inverter (INV 3) is connected with the grid electrode of the eleventh field effect transistor (M11), and the drain electrode of the tenth field effect transistor (M10) and the drain electrode of the eleventh field effect transistor (M11) are connected to the grid electrode of the fifth field effect transistor (M5) in the direct current detection module (300);
the static electricity discharge module (500) comprises a first static electricity discharge tube (Mesd 1) and a second static electricity discharge tube (Mesd 2), wherein the drain electrode of the first static electricity discharge tube (Mesd 1) is connected with the PAD, the source electrode of the first static electricity discharge tube (Mesd 1) is connected with the drain electrode of the second static electricity discharge tube (Mesd 2), the source electrode of the second static electricity discharge tube (Mesd 2) is connected with the Ground (GND), the grid electrode of the first static electricity discharge tube (Mesd 1) is connected with the output end of the first inverter (INV 1) and the source electrode of the tenth field effect tube (M10), and the grid electrode of the second static electricity discharge tube (Mesd 2) is connected between the drain electrode of the tenth field effect tube (M10) and the drain electrode of the eleventh field effect tube (M11).
2. The high voltage clamping circuit with ac detection and dc detection according to claim 1, wherein the voltage dividing submodule (401) includes a sixth resistor (R6) and a seventh resistor (R7), one end of the sixth resistor (R6) is connected to the drain of the ninth field effect transistor (M9), the other end of the sixth resistor (R6) is connected to the seventh resistor (R7), the other end of the seventh resistor (R7) is connected to Ground (GND), and the input end of the third inverter (INV 3) is connected between the sixth resistor (R6) and the seventh resistor (R7).
3. The high voltage clamp circuit with ac and dc detection according to claim 1, wherein the first fet (M1), the second fet (M2), the third fet (M3), the fourth fet (M4), the eighth fet (M8), the ninth fet (M9) and the tenth fet (M10) are P-type fets, and the fifth fet (M5), the sixth fet (M6), the seventh fet (M7), the eleventh fet (M11), the first electrostatic discharge (Mesd 1) and the second electrostatic discharge (Mesd 2) are N-type fets.
4. The high voltage clamp with ac and dc detection of claim 1, wherein the voltage divider module (100) is two resistors connected in series or two field effect transistors connected in series.
5. The high voltage clamp circuit with ac and dc detection according to claim 1, wherein the voltage dividing submodule (401) is two resistors connected in series or two field effect transistors connected in series.
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| TWI779942B (en) * | 2021-11-30 | 2022-10-01 | 瑞昱半導體股份有限公司 | Electrical discharge circuit having stable discharging mechanism |
| CN114582282B (en) * | 2022-03-30 | 2023-07-25 | 武汉华星光电半导体显示技术有限公司 | ESD protection circuit and display device |
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