CN110994574A

CN110994574A - High-voltage-resistant power supply clamping circuit

Info

Publication number: CN110994574A
Application number: CN201910980009.6A
Authority: CN
Inventors: 李天柱
Original assignee: Zhuhai Eeasy Electronic Tech Co ltd
Current assignee: Zhuhai Eeasy Electronic Tech Co ltd
Priority date: 2019-10-15
Filing date: 2019-10-15
Publication date: 2020-04-10
Anticipated expiration: 2039-10-15
Also published as: CN110994574B

Abstract

The invention discloses a high-voltage-resistant power supply clamping circuit which comprises a voltage dividing module, an electrostatic detection module, a logic control module and an electrostatic discharge module, wherein the voltage dividing module is respectively connected with a power supply, a ground, the electrostatic detection module and the logic control module, the electrostatic detection module is respectively connected with the power supply and the logic control module, the logic control module is respectively connected with the power supply, the ground and the electrostatic discharge module, the electrostatic discharge module is respectively connected with the power supply and the ground, and the logic control module comprises a first phase inverter, a second phase inverter, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor and a voltage dividing submodule. The invention has the beneficial effects that: when the static leakage happens, through the logic signal transmission of the circuit, the grid voltage of the static leakage tube in the static leakage module can reach the voltage on the power line and can maintain the leakage time of the RC time constant set by the static detection module, thereby ensuring the static leakage protection effect.

Description

High-voltage-resistant power supply clamping circuit

Technical Field

The invention relates to the field of electrostatic protection circuits, in particular to a high-voltage-resistant power supply clamping circuit.

Background

When electronic components are manufactured, produced, assembled, tested, stored, transported, etc., static electricity is accumulated in human bodies, instruments, storage equipment, etc., and even the electronic components themselves accumulate electric charges. When an Electrostatic source comes into contact with other objects, there is a flow of charge, which generates potentially damaging voltages, currents and electromagnetic fields, and because the instantaneous voltage of Electrostatic Discharge is very high, usually more than several kilovolts, the damage is destructive and permanent, which causes direct circuit burn-out, i.e. Electrostatic Discharge (ESD), so preventing Electrostatic damage is the first problem in all IC design and manufacture. With the continuous progress of the integrated circuit technology and the process level, the transistor and the device on the chip are made smaller, the integration level of the chip is higher and higher, the working voltage of the device is lower and lower, and the voltage requirement of many applications is fixed, for example, a 28nm process device can only bear 1.8V, and many peripheral applications are still 3.3V. Therefore, it is urgently required to design an electrostatic protection circuit with high voltage resistance using a device with low voltage resistance.

The power supply clamping circuit plays a crucial role in the electrostatic protection circuit, and the conventional power supply clamping circuit cannot meet the requirement of advanced process due to the problem of voltage resistance. In the prior art (patent number: CN 107565533 a), an electrostatic protection circuit with resistance to 3.3V high voltage is designed by using a low-voltage device with resistance to 1.8V, but after electrostatic discharge occurs, the node N1 of the electrostatic protection circuit gradually rises to turn on MN1, and at this time, the node N3 is pulled down, thereby greatly reducing the electrostatic protection capability.

Disclosure of Invention

In view of the above problems, the present invention provides a high voltage resistant power clamp circuit, which mainly solves the problem of low electrostatic protection capability of the existing electrostatic protection circuit.

In order to solve the technical problems, the technical scheme of the invention is as follows:

the utility model provides a high voltage resistant power supply clamping circuit, includes partial pressure module, static detection module, logic control module and static leakage module, the partial pressure module is connected power, ground, static detection module and logic control module respectively, static detection module connects power, partial pressure module and logic control module respectively, logic control module connects power, ground, static detection module and static leakage module respectively, static leakage module connects power, ground and logic control module respectively.

Preferably, the voltage division module comprises a first field effect transistor and a second field effect transistor, a source electrode of the first field effect transistor is connected with the power supply, a grid electrode of the second field effect transistor is connected with the ground, a grid electrode of the first field effect transistor is in short circuit with a drain electrode, a grid electrode of the second field effect transistor is in short circuit with the drain electrode, and a 0.5VDD circuit is connected between the first field effect transistor and the second field effect transistor and is connected with the static detection module and the logic control module.

Preferably, the static electricity detection module includes a first resistor and a first capacitor, one end of the first resistor is connected to the power supply, the other end of the first resistor is connected to the first capacitor, the other end of the first capacitor is connected to the 0.5VDD line, and a line is connected between the first resistor and the first capacitor and connected to the logic control module.

Preferably, the logic control module comprises a first inverter, a second inverter, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor and a voltage division submodule, wherein a power supply end of the first inverter, a power supply end of the second inverter and a source electrode of the third field effect transistor are connected to a power supply, a ground end of the third inverter and a source electrode of the sixth field effect transistor are grounded, a ground end of the first inverter, a ground end of the second inverter, a gate electrode of the fourth field effect transistor, a power supply end of the third inverter and a gate electrode of the fifth field effect transistor are connected to the 0.5VDD line, an input end of the first inverter is connected between the first resistor and the first capacitor, an output end of the first inverter is connected to an input end of the second inverter, a source electrode of the fifth field effect transistor and the electrostatic discharge module, an output end of the second inverter is connected to a gate electrode of the third field, the drain electrode of the third field effect transistor is connected with the source electrode of the fourth field effect transistor, the drain electrode of the fourth field effect transistor, the input end of the third phase inverter and the ground are connected with the voltage division submodule, and the output end of the third phase inverter is connected with the grid electrode of the sixth field effect transistor.

Preferably, the voltage division submodule includes a second resistor and a third resistor, one end of the second resistor is connected to the drain of the fourth field effect transistor, the other end of the second resistor is connected to the third resistor, the other end of the third resistor is connected to ground, and the input end of the third inverter is connected between the second resistor and the third resistor.

Preferably, the electrostatic discharge module includes a first electrostatic discharge tube and a second electrostatic discharge tube, a drain of the first electrostatic discharge tube is connected to the power supply, a source of the first electrostatic discharge tube is connected to a drain of the second electrostatic discharge tube, a source of the second electrostatic discharge tube is connected to ground, a gate of the first electrostatic discharge tube is connected to the output end of the first inverter and the source of the fifth field effect tube, and a gate of the second electrostatic discharge tube is connected between the drain of the fifth field effect tube and the drain of the sixth field effect tube.

Preferably, the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor and the fifth field effect transistor are P-type field effect transistors, and the sixth field effect transistor, the first electrostatic discharge tube and the second electrostatic discharge tube are N-type field effect transistors.

Preferably, the voltage dividing module is two resistors connected in series or two field effect transistors connected in series.

Preferably, the voltage division submodule is two resistors connected in series or two field effect transistors connected in series.

The invention has the beneficial effects that:

1. the clamping circuit is set to be a voltage dividing module, a static detection module, a logic control module and a static discharge module, when static discharge occurs, through logic signal transmission of the circuit, grid voltage of a static discharge tube in the static discharge module can reach voltage on a power line, discharge time of an RC time constant set by the static detection module can be maintained, and the static discharge protection effect is guaranteed.

2. The grid of the third field effect transistor is driven by the second phase inverter, and when the circuit works normally, the grid voltage of the third field effect transistor follows the power supply voltage, so that the problem of electric leakage caused by large power supply ripple waves is solved.

3. The power supply clamping circuit only has one capacitor, and is beneficial to saving the occupied area of the circuit.

Drawings

FIG. 1 is a schematic circuit diagram of a high voltage tolerant power clamp according to the present invention;

FIG. 2 is a circuit diagram according to a first embodiment of the present invention;

fig. 3 is a circuit diagram of the voltage divider module and the voltage divider submodule according to the present invention.

Wherein: the circuit comprises a VDD-power supply, a GND-ground, a 100-voltage division module, a 200-static detection module, a 300-logic control module, a 301-voltage division submodule, a 400-static discharge module, a R1-first resistor, a R2-second resistor, a R3-third resistor, a C1-first capacitor, an INV 1-first inverter, an INV 2-second inverter, an INV 3-third inverter, an M1-first field effect transistor, an M2-second field effect transistor, an M3-third field effect transistor, an M4-fourth field effect transistor, an M5-fifth field effect transistor, an M6-sixth field effect transistor, a Mesd 1-first static discharge transistor and a Mesd 2-second static discharge transistor.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the following detailed description of the present invention is provided with reference to the accompanying drawings and detailed description. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings.

The first embodiment is as follows: as shown in fig. 1 and 2, the present embodiment provides a high voltage tolerant power clamp circuit, which includes a voltage dividing module 100, a static electricity detecting module 200, a logic control module 300, and a static electricity discharging module 400, wherein the voltage dividing module 100 is respectively connected to a power VDD, a ground GND, the static electricity detecting module 200, and the logic control module 300, the static electricity detecting module 200 is respectively connected to the power VDD, the voltage dividing module 100, and the logic control module 300, the logic control module 300 is respectively connected to the power VDD, the ground GND, the static electricity detecting module 200, and the static electricity discharging module 400 is respectively connected to the power VDD, the ground GND, and the logic control module 300.

In a preferred embodiment, the voltage divider module 100 includes a first fet M1 and a second fet M2, the source of the first fet M1 is connected to the power VDD, the gate of the second fet M2 is connected to ground GND, the gate of the first fet M1 is shorted to the drain, the gate of the second fet M2 is shorted to the drain, and a 0.5VDD line is connected between the first fet M1 and the second fet M2, and is connected to the electrostatic detection module 200 and the logic control module 300.

In a preferred embodiment, the static electricity detection module 200 includes a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is connected to a power supply VDD, the other end of the first resistor R1 is connected to the first capacitor C1, the other end of the first capacitor C1 is connected to the 0.5VDD line, and a line is connected between the first resistor R1 and the first capacitor C1, and is connected to the logic control module 300.

In a preferred embodiment, the logic control module 300 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a third fet M3, a fourth fet M4, a fifth fet M5, a sixth fet M6 and a voltage divider module 301, the power terminal of the first inverter INV1, the power terminal of the second inverter INV 92 and the source of the third fet M3 are connected to a power source VDD, the ground terminal of the third inverter INV3 and the source of the sixth fet M6 are connected to the ground GND, the ground terminal of the first inverter INV1, the ground terminal of the second inverter INV2, the gate of the fourth fet M4, the power terminal of the third inverter INV3 and the gate of the fifth fet M5 are connected to the 0.5VDD line, the input terminal of the first inverter INV1 is connected between the first resistor R1 and the first capacitor C1, and the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, The source of the fifth field effect transistor M5 and the electrostatic discharge module 400, the output end of the second inverter INV2 is connected to the gate of the third field effect transistor M3, the drain of the third field effect transistor M3 is connected to the source of the fourth field effect transistor M4, the drain of the fourth field effect transistor M4, the input end of the third inverter INV3 and the ground GND are connected to the voltage divider submodule 301, and the output end of the third inverter INV3 is connected to the gate of the sixth field effect transistor M6. Since the current leakage is usually caused by the ripple on VDD in the prior art, the gate of the third fet M3 is driven by the second inverter INV2, and thus there is no current leakage problem.

In a preferred embodiment, the voltage divider submodule 301 includes a second resistor R2 and a third resistor R3, one end of the second resistor R2 is connected to the drain of the fourth fet M4, the other end of the second resistor R2 is connected to the third resistor R3, the other end of the third resistor R3 is connected to ground GND, and an input end of a third inverter INV3 is connected between the second resistor R2 and the third resistor R3.

In a preferred embodiment, the electrostatic discharge module 400 includes a first electrostatic discharge tube Mesd1 and a second electrostatic discharge tube Mesd2, a drain of the first electrostatic discharge tube Mesd1 is connected to the power supply VDD, a source of the first electrostatic discharge tube Mesd1 is connected to a drain of the second electrostatic discharge tube Mesd2, a source of the second electrostatic discharge tube Mesd2 is connected to the ground GND, a gate of the first electrostatic discharge tube Mesd1 is connected to an output terminal of the first inverter INV1 and a source of the fifth field effect tube M5, and a gate of the second electrostatic discharge tube Mesd2 is connected between a drain of the fifth field effect tube M5 and a drain of the sixth field effect tube M6.

In a preferred embodiment, the first fet M1, the second fet M2, the third fet M3, the fourth fet M4 and the fifth fet M5 are P-type fets, and the sixth fet M6, the first electrostatic discharge tube Mesd1 and the second electrostatic discharge tube Mesd2 are N-type fets.

Example two: as shown in fig. 3, on the basis of the first embodiment, the voltage dividing module 100 may be two P-type fets, two serially connected resistors, or two serially connected N-type fets, wherein when the voltage dividing module 100 is two serially connected N-type fets, the drains and gates of the two N-type fets are shorted, and the line from between M1 and M2 is connected to the 0.5VDD line, and similarly, when the voltage dividing module 100 is two serially connected resistors, the line from between Rx and Ry is connected to the 0.5VDD line.

Example three: as shown in fig. 3, on the basis of the first embodiment, the voltage divider sub-module 301 may be two resistors connected in series, or two N-type fets or two P-type fets connected in series, and the specific connection is as in the second embodiment or fig. 3.

The voltage dividing module 100 according to the second embodiment and the voltage dividing submodule 301 according to the third embodiment both adopt the principle of serial voltage division, and the resistances of Rx and Ry are equal or close to each other, and are much larger than the on-resistances of the third field effect transistor M3 and the fourth field effect transistor M4. When M3, M4 are turned on, the voltage division result is about half of the power supply VDD, and when the voltage division is performed by the fets, it is necessary to ensure that the two fets are the same parameter or similar parameter. It should be noted that Rx, Ry, Mx, and My in fig. 3 are only used to represent different devices, and are not inconsistent with the description of the first embodiment, and similarly, V1 and V2 are only used to represent voltages across the devices, and Vout represents the output voltage.

The working principle is as follows: when the circuit normally works, the output voltage of the voltage division module 100 is 0.5VDD, the voltage of the input end of the first inverter INV1 is high level VDD, the voltage of the output end is low level 0.5VDD, the gate voltage of the first electrostatic discharge tube Mesd1 is 0.5VDD, the source and gate voltages of the fifth field-effect tube M5 are both 0.5VDD, and the fifth field-effect tube M5 is turned off; the input end of the second inverter INV2 is at low level 0.5VDD, the output end is at high level VDD, and the third fet M3 is turned off, so the voltage at the serial connection point of the second resistor R2 and the third resistor R3 is at low GND; the input end of the third inverter INV3 is at low level GND, the output end is at high level 0.5VDD, the sixth field effect transistor M6 is turned on, the gate voltage of the second electrostatic discharge tube Mesd2 is pulled to GND, and the second electrostatic discharge tube Mesd2 is turned off; the grid voltage of the fourth field effect transistor M4 is 0.5VDD, the low voltage GND is prevented from being transmitted to the drain electrode of the third field effect transistor M3, and the voltage-resistant risk of the third field effect transistor M3 is eliminated.

When the static electricity leakage occurs, the power supply VDD rapidly rises, and due to the time delay function of the static electricity detection module 200, the voltage at the input end of the first inverter INV1 is at a low level relative to the power supply VDD, so the input end of the first inverter INV1 is at a low level, the output end is at a high VDD, the gate voltage of the first static electricity leakage tube Mesd1 is at a high VDD, the gate voltage of the fifth field effect tube M5 is 0.5VDD, and the fifth field effect tube M5 is turned on; meanwhile, the input end of the second inverter INV2 is at high level VDD, the output end is at low level 0.5VDD, and the third fet M3 is turned on, so the voltage at the serial connection point of the second resistor R2 and the third resistor R3 is about 0.5 VDD; the input end of the third inverter INV3 is at high level 0.5VDD, the output is at low level GND, the sixth fet M6 is turned off, and the gate voltage of the second electrostatic discharge tube Mesd2 is pulled to high level VDD through the fifth fet M5. At this time, the gate voltages of the first electrostatic discharge tube Mesd1 and the second electrostatic discharge tube Mesd2 are both at the high level VDD, so that the two electrostatic discharge tubes are turned on to discharge electrostatic current. After the time constant R1 × C1 elapses, the voltage at the input terminal of the first inverter INV1 gradually rises to cross the threshold of the first inverter INV1, at this time, the output of the first inverter INV1 becomes low GND, the fifth fet M5 is turned off, the output terminal of the second inverter INV2 becomes high, the third fet M3 is turned off, the input terminal of the third inverter INV3 becomes low GND, the output terminal becomes high 0.5VDD, the sixth fet M6 is turned on to turn off the second electrostatic discharge tube Mesd2, and the electrostatic discharge is terminated. The leakage time is an RC time constant, and in the existing clamp circuit technology, the leakage time is much shorter than the RC time; the grid voltage of the static discharge tube is higher and has stronger conducting capability, and when the static discharge occurs, the grid voltage of the two static discharge tubes follows VDD to reach the voltage of VDD, so the static discharge tube is stronger in opening and stronger in discharge. In summary, the invention has longer electrostatic discharge time, higher gate voltage of the discharge tube of the electrostatic discharge tube, and stronger on-state discharge capability, and the power supply clamp circuit of the invention has only one capacitor, which is beneficial to saving the area occupied by the circuit.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention accordingly, and not to limit the protection scope of the present invention accordingly. All equivalent changes or modifications made in accordance with the spirit of the present disclosure are intended to be covered by the scope of the present disclosure.

Claims

1. The utility model provides a high voltage resistant power supply clamp circuit, its characterized in that, includes partial pressure module (100), static electricity detection module (200), logic control module (300) and static leakage module (400), power (VDD), Ground (GND), static electricity detection module (200) and logic control module (300) are connected respectively to partial pressure module (100), static electricity detection module (200) connect power (VDD), partial pressure module (100) and logic control module (300) respectively, logic control module (300) connect power (VDD), Ground (GND), static electricity detection module (200) and static leakage module (400) respectively, power (VDD), Ground (GND) and logic control module (300) are connected respectively to static leakage module (400).

2. The high voltage tolerant power clamp circuit of claim 1, wherein the voltage divider module (100) comprises a first fet (M1) and a second fet (M2), wherein the source of the first fet (M1) is connected to the power supply (VDD), the gate of the second fet (M2) is connected to Ground (GND), the gate of the first fet (M1) is shorted to the drain, the gate of the second fet (M2) is shorted to the drain, and a 0.5VDD line is connected between the first fet (M1) and the second fet (M2) and is connected to the electrostatic detection module (200) and the logic control module (300).

3. The high voltage tolerant power clamp circuit of claim 2, wherein the static detection module (200) comprises a first resistor (R1) and a first capacitor (C1), one end of the first resistor (R1) is connected to the power supply (VDD), the other end of the first resistor (R3526) is connected to the first capacitor (C1), the other end of the first capacitor (C1) is connected to the 0.5VDD line, and a line is connected between the first resistor (R1) and the first capacitor (C1) and is connected to the logic control module (300).

4. The high voltage tolerant power clamp circuit as claimed in claim 3, wherein the logic control module (300) comprises a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a third field effect transistor (M3), a fourth field effect transistor (M4), a fifth field effect transistor (M5), a sixth field effect transistor (M6), and a voltage divider submodule (301), wherein a power supply terminal of the first inverter (INV1), a power supply terminal of the second inverter (INV2), and a source of the third field effect transistor (M3) are connected to a power supply (VDD), a ground terminal of the third inverter (INV3) and a source of the sixth field effect transistor (M6) are connected to a Ground (GND), a ground terminal of the first inverter (INV1), a ground terminal of the second inverter (INV2), a gate of the fourth field effect transistor (M4), a ground terminal of the third inverter (INV3), and a gate of the fifth field effect transistor (M5) are connected to the VDD 670.675 line, the input end of the first inverter (INV1) is connected between the first resistor (R1) and the first capacitor (C1), the output end of the first inverter (INV1) is connected to the input end of the second inverter (INV2), the source of the fifth field effect transistor (M5) and the electrostatic discharge module (400), the output end of the second inverter (INV2) is connected with the gate of the third field effect transistor (M3), the drain of the third field effect transistor (M3) is connected with the source of the fourth field effect transistor (M4), the drain of the fourth field effect transistor (M4), the input end of the third inverter (INV3) and the Ground (GND) are connected with the voltage division submodule (301), and the output end of the third inverter (INV3) is connected with the gate of the sixth field effect transistor (M6).

5. The high voltage tolerant power clamp circuit of claim 4, wherein the voltage divider submodule (301) comprises a second resistor (R2) and a third resistor (R3), one end of the second resistor (R2) is connected to the drain of the fourth FET (M4), the other end of the second resistor (R2) is connected to the third resistor (R3), the other end of the third resistor (R3) is connected to Ground (GND), and an input end of a third inverter (INV3) is connected between the second resistor (R2) and the third resistor (R3).

6. The high voltage tolerant power clamp circuit as claimed in claim 5, wherein the electrostatic discharge module (400) comprises a first electrostatic discharge (Mesd1) and a second electrostatic discharge (Mesd2), wherein the drain of the first electrostatic discharge (Mesd1) is connected to the power supply (VDD), the source of the first electrostatic discharge (Mesd1) is connected to the drain of the second electrostatic discharge (Mesd2), the source of the second electrostatic discharge (Mesd2) is connected to Ground (GND), the gate of the first electrostatic discharge (Mesd1) is connected to the output of the first inverter (INV1) and the source of the fifth field effect (M5), and the gate of the second electrostatic discharge (Mesd2) is connected between the drain of the fifth field effect (M5) and the drain of the sixth field effect (M6).

7. The high voltage tolerant power clamp circuit as claimed in claim 6, wherein the first fet (M1), the second fet (M2), the third fet (M3), the fourth fet (M4), and the fifth fet (M5) are P-type fets, and the sixth fet (M6), the first electrostatic discharge (Mesd1), and the second electrostatic discharge (Mesd2) are N-type fets.

8. The high voltage tolerant power clamp circuit of claim 1, wherein the voltage divider block (100) is two resistors connected in series or two fets connected in series.

9. The high voltage tolerant power clamp circuit of claim 4, wherein the voltage divider submodule (301) is two resistors connected in series or two field effect transistors connected in series.