TWI739629B

TWI739629B - Integrated circuit with electrostatic discharge protection

Info

Publication number: TWI739629B
Application number: TW109135417A
Authority: TW
Inventors: 趙傳珍; 白景堯
Original assignee: 立積電子股份有限公司
Priority date: 2019-11-01
Filing date: 2020-10-14
Publication date: 2021-09-11
Also published as: TW202119722A

Abstract

An integrated circuit includes a signal pad, configured to receive an input signal during a normal mode, and receive an ESD signal during an ESD mode; an internal circuit, configured to process the input signal during the normal mode; a variable impedance circuit, comprising a first end coupled to the signal pad, a second end coupled to the internal circuit, wherein the variable impedance circuit provides a low impedance path between the signal pad and the internal circuit during the normal mode, and provides a high impedance path between the signal pad and the internal circuit during the ESD mode; and a switch circuit, comprising a first end coupled to the control end of the variable impedance circuit, a second end coupled to the reference voltage terminal, and a control end configured to receive a node voltage, wherein the switch circuit is configured to switch the control end of the variable impedance circuit to have a first specific voltage during the normal mode, and to switch the control end of the variable impedance circuit to be electrically floating during the ESD mode.

Description

Integrated circuit with electrostatic discharge protection mechanism

本發明係指一種具有靜電放電（electrostatic discharge，ESD）保護機制的積體電路（integrated circuit，IC），尤指一種具有靜電放電保護機制及較小電路面積與寄生電容的積體電路。The present invention refers to an integrated circuit (IC) with an electrostatic discharge (ESD) protection mechanism, in particular to an integrated circuit (IC) with an electrostatic discharge protection mechanism and a smaller circuit area and parasitic capacitance.

靜電放電（electrostatic discharge，ESD）防護能力測試是用於評估積體電路（integrated circuit，IC）之可靠度（reliability）。為避免過大的靜電放電訊號（ESD signal）進入IC的內部電路而造成損壞，在IC中，通常會設置靜電放電保護裝置（ESD protection device）以對ESD訊號提供放電路徑。然而，ESD保護裝置的導通電阻與ESD訊號所產生的電壓恐會超過內部電路可承受的最大電壓，進而損壞內部電路。因此，習知技術通常透過增加ESD保護裝置的電路尺寸（如增加為原尺寸的3倍），以降低ESD保護裝置的導通電阻並提升ESD保護裝置的ESD訊號放電能力。Electrostatic discharge (ESD) protection capability test is used to evaluate the reliability of integrated circuits (IC). In order to prevent excessive ESD signals from entering the internal circuit of the IC and causing damage, an ESD protection device is usually provided in the IC to provide a discharge path for the ESD signal. However, the voltage generated by the on-resistance of the ESD protection device and the ESD signal may exceed the maximum voltage that the internal circuit can withstand, thereby damaging the internal circuit. Therefore, the conventional technology generally increases the circuit size of the ESD protection device (for example, increasing it to three times the original size) to reduce the on-resistance of the ESD protection device and improve the ESD signal discharge capability of the ESD protection device.

但是，增加ESD保護裝置的電路尺寸不但會佔據IC更多的電路面積，且也需較高的生產成本。此外，較大電路尺寸的ESD保護裝置相對存在較大的寄生電容，導致內部電路的切換速度降低。有鑑於此，習知技術實有改進之必要。However, increasing the circuit size of the ESD protection device not only occupies more circuit area of the IC, but also requires higher production costs. In addition, ESD protection devices with larger circuit sizes have relatively larger parasitic capacitances, which reduces the switching speed of internal circuits. In view of this, it is necessary to improve the conventional technology.

因此，本發明之主要目的即在於提供一種可具有靜電放電保護機制及較小電路面積與寄生電容的積體電路。Therefore, the main purpose of the present invention is to provide an integrated circuit with an electrostatic discharge protection mechanism and a smaller circuit area and parasitic capacitance.

本發明揭露一種積體電路，具有靜電放電保護機制，包括一訊號焊墊，用以在一正常模式接收一輸入訊號，以及用以在一靜電放電模式接收一靜電放電訊號；一內部電路，用以在該正常模式處理該輸入訊號；一可變阻抗電路，具有一第一端耦接該訊號焊墊，一第二端耦接該內部電路，以及一控制端，該可變阻抗電路用以在該正常模式於該訊號焊墊與該內部電路之間提供一低阻抗路徑，以及用以在該靜電放電模式於該訊號焊墊與該內部電路之間提供一高阻抗路徑；以及一開關電路，具有一第一端耦接該可變阻抗電路的該控制端，一第二端耦接一參考電壓端，以及一控制端用以接收一節點電壓，該開關電路用以在該正常模式使該可變阻抗電路的該控制端具有一第一特定電壓，以及用以在該靜電放電模式使該可變阻抗電路的該控制端為電性浮接。The present invention discloses an integrated circuit with an electrostatic discharge protection mechanism, including a signal pad for receiving an input signal in a normal mode, and for receiving an electrostatic discharge signal in an electrostatic discharge mode; an internal circuit with To process the input signal in the normal mode; a variable impedance circuit having a first end coupled to the signal pad, a second end coupled to the internal circuit, and a control end, the variable impedance circuit is used for Provide a low impedance path between the signal pad and the internal circuit in the normal mode, and provide a high impedance path between the signal pad and the internal circuit in the electrostatic discharge mode; and a switch circuit , Having a first terminal coupled to the control terminal of the variable impedance circuit, a second terminal coupled to a reference voltage terminal, and a control terminal for receiving a node voltage, and the switch circuit is used for operating in the normal mode The control terminal of the variable impedance circuit has a first specific voltage, and is used to electrically float the control terminal of the variable impedance circuit in the electrostatic discharge mode.

請參考第1圖，第1圖為本發明實施例一積體電路（integrated circuit，IC）10之示意圖。IC 10具有靜電放電（electrostatic discharge，ESD）保護機制，IC 10包括訊號焊墊100、內部電路102、可變阻抗電路104以及開關電路106。訊號焊墊100可用以在正常模式（normal mode）接收輸入訊號，以及可用以在靜電放電模式（ESD mode）接收靜電放電訊號（ESD signal）。輸入訊號可以是直流電壓或交流電壓，ESD訊號可以是ESD電流或ESD電壓。內部電路102可用以在正常模式處理輸入訊號。可變阻抗電路104具有第一端耦接訊號焊墊100，第二端耦接內部電路102，以及控制端。可變阻抗電路104可用以在正常模式於訊號焊墊100與內部電路102之間提供低阻抗路徑，以及可用以在ESD模式於訊號焊墊100與內部電路102之間提供高阻抗路徑。開關電路106具有第一端耦接可變阻抗電路104的控制端，第二端耦接參考電壓端，以及控制端用以接收節點電壓Vn。開關電路106可用以在正常模式使可變阻抗電路104的控制端具有第一特定電壓，以及可用以在ESD模式使可變阻抗電路106的控制端為電性浮接（electrically floating）。此外，參考電壓Vref可施加於參考電壓端，參考電壓Vref可為接地電壓（如0伏特）或其它具有低電壓準位的固定電壓。Please refer to FIG. 1, which is a schematic diagram of an integrated circuit (IC) 10 according to an embodiment of the present invention. The IC 10 has an electrostatic discharge (ESD) protection mechanism. The IC 10 includes a signal pad 100, an internal circuit 102, a variable impedance circuit 104, and a switch circuit 106. The signal pad 100 can be used to receive an input signal in a normal mode and can be used to receive an ESD signal in an ESD mode. The input signal can be a DC voltage or an AC voltage, and the ESD signal can be an ESD current or an ESD voltage. The internal circuit 102 can be used to process the input signal in the normal mode. The variable impedance circuit 104 has a first end coupled to the signal pad 100, a second end coupled to the internal circuit 102, and a control end. The variable impedance circuit 104 can be used to provide a low impedance path between the signal pad 100 and the internal circuit 102 in the normal mode, and can be used to provide a high impedance path between the signal pad 100 and the internal circuit 102 in the ESD mode. The switch circuit 106 has a first terminal coupled to a control terminal of the variable impedance circuit 104, a second terminal coupled to a reference voltage terminal, and a control terminal for receiving the node voltage Vn. The switch circuit 106 can be used to make the control terminal of the variable impedance circuit 104 have the first specific voltage in the normal mode, and can be used to make the control terminal of the variable impedance circuit 106 electrically floating in the ESD mode. In addition, the reference voltage Vref can be applied to the reference voltage terminal, and the reference voltage Vref can be a ground voltage (such as 0 volts) or other fixed voltages with a low voltage level.

節點A可形成於訊號焊墊100與可變阻抗電路104的第一端之間。節點B可形成於可變阻抗電路104的第二端與內部電路102之間。換句話說，在正常模式下，可變阻抗電路104於節點A與節點B之間提供的低阻抗路徑相當於是對輸入訊號提供從訊號焊墊100至內部電路102的傳輸路徑，以使內部電路102可正常接收並處理輸入訊號。另一方面，在ESD模式下，可變阻抗電路104於節點A與節點B之間提供的高阻抗路徑相當於是增加ESD訊號從訊號焊墊100傳輸至內部電路102的難度（如高阻抗路徑相當於是用以為內部電路102提供額外的承受ESD訊號之能力，進而阻擋ESD訊號進入內部電路102），使得ESD訊號在節點A到節點B之間大幅降低，因此ESD訊號將不易直接進入內部電路102，從而避免內部電路102被損壞。如此一來，本發明可適當設計電路以在正常模式下不影響內部電路102的運作，且在ESD模式下能降低ESD訊號對內部電路102的影響。此外，本發明還可透過適當設計可變阻抗電路104的電路尺寸，以具有較小電路面積（如可變阻抗電路104在IC 10的整體電路面積中所佔比例為小於0.5%）及寄生電容。較小的寄生電容有利於在正常模式下維持輸入訊號的完整性以及可改善對內部電路102的切換速度的影響。The node A can be formed between the signal pad 100 and the first end of the variable impedance circuit 104. The node B may be formed between the second end of the variable impedance circuit 104 and the internal circuit 102. In other words, in the normal mode, the low impedance path provided by the variable impedance circuit 104 between node A and node B is equivalent to providing a transmission path from the signal pad 100 to the internal circuit 102 for the input signal, so that the internal circuit 102 can receive and process the input signal normally. On the other hand, in the ESD mode, the high impedance path provided by the variable impedance circuit 104 between node A and node B is equivalent to increasing the difficulty of ESD signal transmission from the signal pad 100 to the internal circuit 102 (for example, the high impedance path is equivalent to Therefore, it is used to provide the internal circuit 102 with additional ability to withstand the ESD signal, thereby blocking the ESD signal from entering the internal circuit 102), so that the ESD signal is greatly reduced between node A and node B, so the ESD signal will not easily enter the internal circuit 102 directly. Thus, the internal circuit 102 is prevented from being damaged. In this way, the present invention can appropriately design the circuit so as not to affect the operation of the internal circuit 102 in the normal mode, and can reduce the influence of the ESD signal on the internal circuit 102 in the ESD mode. In addition, the present invention can also appropriately design the circuit size of the variable impedance circuit 104 to have a smaller circuit area (for example, the variable impedance circuit 104 accounts for less than 0.5% of the overall circuit area of the IC 10) and parasitic capacitance. . The smaller parasitic capacitance helps maintain the integrity of the input signal in the normal mode and can improve the influence on the switching speed of the internal circuit 102.

詳細來說，在正常模式，節點電壓Vn與開關電路106之第一端的電壓或第二端的電壓之電壓差之絕對值大於開關電路106的閾值電壓（threshold voltage）的絕對值，使開關電路106為導通狀態。導通的開關電路106可使可變阻抗電路104的控制端為電性耦接參考電壓端以具有第一特定電壓（如接近參考電壓端上的參考電壓Vref），可變阻抗電路104從而提供低阻抗路徑。另一方面，在ESD模式，節點電壓Vn與開關電路106之第一端的電壓或第二端的電壓之電壓差之絕對值小於開關電路106的閾值電壓的絕對值，使開關電路106為截止狀態。截止的開關電路106可使可變阻抗電路104的控制端為電性浮接，可變阻抗電路104從而提供高阻抗路徑。值得注意的是，節點電壓Vn可與內部電路102的電源啟閉狀態有關或可由其它電路提供。本領域具通常知識者當可據以進行修飾或變化，而不限於此。In detail, in the normal mode, the absolute value of the voltage difference between the node voltage Vn and the voltage at the first terminal or the voltage at the second terminal of the switching circuit 106 is greater than the absolute value of the threshold voltage of the switching circuit 106, so that the switching circuit 106 is the on state. The turned-on switch circuit 106 enables the control terminal of the variable impedance circuit 104 to be electrically coupled to the reference voltage terminal so as to have a first specific voltage (for example, close to the reference voltage Vref on the reference voltage terminal), and the variable impedance circuit 104 thus provides low Impedance path. On the other hand, in the ESD mode, the absolute value of the voltage difference between the node voltage Vn and the voltage at the first terminal or the voltage at the second terminal of the switch circuit 106 is less than the absolute value of the threshold voltage of the switch circuit 106, so that the switch circuit 106 is turned off . The switched-off switch circuit 106 can make the control terminal of the variable impedance circuit 104 electrically floating, and the variable impedance circuit 104 thus provides a high impedance path. It should be noted that the node voltage Vn may be related to the power on/off state of the internal circuit 102 or may be provided by other circuits. Those with ordinary knowledge in the field can make modifications or changes accordingly, and it is not limited to this.

具體而言，請參考第2圖，第2圖為本發明實施例另一IC 20之示意圖。可變阻抗電路104可包括至少一開關。值得注意的是，開關的數量與IC 20的ESD保護能力有關。也就是說，可變阻抗電路104在設計上具有彈性。進一步而言，可設計開關的數量與IC 20的ESD保護能力之間的關係為正相關。第2圖的實施例以可變阻抗電路104包括n個開關SW1～SWn為例進行說明。n個開關SW1～SWn可以形成堆疊（stack）結構。詳細來說，開關SWi具有第一端耦接可變阻抗電路104的第一端，第二端耦接可變阻抗電路104的第二端，以及控制端耦接可變阻抗電路104的控制端。開關SW1具有第一端耦接可變阻抗電路104的第一端，第二端耦接開關SWi的第一端，以及控制端耦接可變阻抗電路104的控制端。開關SWn具有第一端耦接開關SWi的第二端，第二端耦接可變阻抗電路104的該第二端，以及控制端耦接可變阻抗電路104的控制端。變數n及i為正整數，1

i

n。開關SW1～SWn各者可包括P通道金屬氧化物半導體（P-channel metal oxide semiconductor，PMOS）電晶體、P通道場效電晶體（P-channel field effect transistor，PFET）或假晶高速電子移動電晶體（pseudomorphic high electron mobility transistor，pHEMT）。此外，本發明可透過選用具有較小尺寸的PMOS電晶體、PFET或pHEMT，以使可變阻抗電路104具有較小的電路面積及寄生電容。第2圖的實施例是以開關SW1～SWn各者包括PMOS電晶體為例進行說明。開關SW1～SWn的第一端可為PMOS電晶體的汲極與源極之一，第二端可為PMOS電晶體的汲極與源極之另一，以及控制端可為PMOS電晶體的閘極。 Specifically, please refer to FIG. 2, which is a schematic diagram of another IC 20 according to an embodiment of the present invention. The variable impedance circuit 104 may include at least one switch. It is worth noting that the number of switches is related to the ESD protection capability of the IC 20. In other words, the variable impedance circuit 104 has flexibility in design. Furthermore, the relationship between the number of designable switches and the ESD protection capability of the IC 20 is positively correlated. The embodiment in FIG. 2 is described by taking an example in which the variable impedance circuit 104 includes n switches SW1 to SWn. The n switches SW1 ˜SWn may form a stack structure. In detail, the switch SWi has a first terminal coupled to the first terminal of the variable impedance circuit 104, a second terminal coupled to the second terminal of the variable impedance circuit 104, and a control terminal coupled to the control terminal of the variable impedance circuit 104 . The switch SW1 has a first terminal coupled to the first terminal of the variable impedance circuit 104, a second terminal coupled to the first terminal of the switch SWi, and a control terminal coupled to the control terminal of the variable impedance circuit 104. The switch SWn has a first terminal coupled to the second terminal of the switch SWi, a second terminal coupled to the second terminal of the variable impedance circuit 104, and a control terminal coupled to the control terminal of the variable impedance circuit 104. Variables n and i are positive integers, 1

i

n. Each of the switches SW1 to SWn may include P-channel metal oxide semiconductor (PMOS) transistors, P-channel field effect transistors (PFET), or pseudomorphic high-speed electronic mobile devices. Crystal (pseudomorphic high electron mobility transistor, pHEMT). In addition, in the present invention, the variable impedance circuit 104 can have a smaller circuit area and parasitic capacitance by selecting a PMOS transistor, PFET, or pHEMT with a smaller size. The embodiment in FIG. 2 is described with an example in which each of the switches SW1 to SWn includes a PMOS transistor. The first terminal of the switches SW1 to SWn can be one of the drain and source of the PMOS transistor, the second terminal can be the other of the drain and the source of the PMOS transistor, and the control terminal can be the gate of the PMOS transistor pole.

如第2圖所示，開關電路106的控制端耦接內部電路102，節點電壓Vn與內部電路102的電源啟閉狀態有關。開關電路106可包括PMOS電晶體或N通道金屬氧化物半導體（N-channel metal oxide semiconductor，NMOS）電晶體。第2圖的實施例以開關電路106包括NMOS電晶體Mn為例進行說明。開關電路106的第一端可為NMOS電晶體Mn的汲極，第二端可為NMOS電晶體Mn的源極，以及控制端可為NMOS電晶體Mn的閘極。As shown in FIG. 2, the control terminal of the switch circuit 106 is coupled to the internal circuit 102, and the node voltage Vn is related to the power on/off state of the internal circuit 102. The switch circuit 106 may include a PMOS transistor or an N-channel metal oxide semiconductor (NMOS) transistor. The embodiment in FIG. 2 is described by taking the switch circuit 106 including the NMOS transistor Mn as an example. The first terminal of the switch circuit 106 may be the drain of the NMOS transistor Mn, the second terminal may be the source of the NMOS transistor Mn, and the control terminal may be the gate of the NMOS transistor Mn.

在正常模式，內部電路102為電源開啟（power on）狀態，以使節點電壓Vn具有第二特定電壓。亦即，參考電壓Vdd施加於內部電路102之高準位參考電壓端，及參考電壓Vref施加於內部電路102之低準位參考電壓端，用以對內部電路102供電，使內部電路102可正常運作（如用以處理輸入訊號）。與內部電路102的電源開啟狀態有關的節點電壓Vn因內部電路102的運作而具有第二特定電壓，使得節點電壓Vn與NMOS電晶體Mn之源極的電壓之電壓差（又或是NMOS電晶體Mn之閘源極電壓差）之絕對值大於NMOS電晶體Mn的閾值電壓的絕對值，從而使NMOS電晶體Mn為導通狀態。如此一來，開關SW1～SWn之控制端為電性耦接至具有參考電壓Vref之參考電壓端而具有較低電壓準位，開關SW1～SWn因此為導通狀態，可變阻抗電路104便可於訊號焊墊100與內部電路102之間提供低阻抗路徑。In the normal mode, the internal circuit 102 is in a power on state, so that the node voltage Vn has the second specific voltage. That is, the reference voltage Vdd is applied to the high-level reference voltage terminal of the internal circuit 102, and the reference voltage Vref is applied to the low-level reference voltage terminal of the internal circuit 102 to supply power to the internal circuit 102 so that the internal circuit 102 can be normal Operation (such as processing input signals). The node voltage Vn related to the power-on state of the internal circuit 102 has a second specific voltage due to the operation of the internal circuit 102, so that the voltage difference between the node voltage Vn and the source voltage of the NMOS transistor Mn (or NMOS transistor The absolute value of the gate-source voltage difference of Mn) is greater than the absolute value of the threshold voltage of the NMOS transistor Mn, so that the NMOS transistor Mn is turned on. In this way, the control terminals of the switches SW1 to SWn are electrically coupled to the reference voltage terminal with the reference voltage Vref and have a lower voltage level. The switches SW1 to SWn are therefore turned on, and the variable impedance circuit 104 can be A low impedance path is provided between the signal pad 100 and the internal circuit 102.

另一方面，在ESD模式，內部電路102為電源關閉（power off）狀態，以使節點電壓Vn具有浮接電壓。亦即，參考電壓Vdd未施加於內部電路102之高準位參考電壓端，及參考電壓Vref未施加於內部電路102之低準位參考電壓端，內部電路102的高準位參考電壓端及低準位參考電壓端為電性浮接，內部電路102因而未被供電。與內部電路102的電源關閉狀態有關之節點電壓Vn因內部電路102未被供電而具有浮接電壓，使得節點電壓Vn與NMOS電晶體Mn之源極的電壓之電壓差（又或是NMOS電晶體Mn之閘源極電壓差）之絕對值小於NMOS電晶體Mn的閾值電壓的絕對值，從而使NMOS電晶體Mn為截止狀態。如此一來，開關SW1～SWn之控制端為電性浮接，開關SW1～SWn因此為截止狀態，可變阻抗電路104便可於訊號焊墊100與內部電路102之間提供高阻抗路徑。其中，浮接電壓可具有不特定電壓。On the other hand, in the ESD mode, the internal circuit 102 is in a power off state, so that the node voltage Vn has a floating voltage. That is, the reference voltage Vdd is not applied to the high-level reference voltage terminal of the internal circuit 102, and the reference voltage Vref is not applied to the low-level reference voltage terminal of the internal circuit 102, and the high-level reference voltage terminal and the low-level reference voltage terminal of the internal circuit 102 are not applied. The level reference voltage terminal is electrically floating, and therefore the internal circuit 102 is not powered. The node voltage Vn related to the power-off state of the internal circuit 102 has a floating voltage because the internal circuit 102 is not powered, so that the voltage difference between the node voltage Vn and the source voltage of the NMOS transistor Mn (or NMOS transistor The absolute value of the gate-source voltage difference of Mn) is smaller than the absolute value of the threshold voltage of the NMOS transistor Mn, so that the NMOS transistor Mn is turned off. In this way, the control terminals of the switches SW1 ˜SWn are electrically floating, and the switches SW1 ˜SWn are therefore in an off state, and the variable impedance circuit 104 can provide a high impedance path between the signal pad 100 and the internal circuit 102. Among them, the floating voltage may have an unspecified voltage.

值得注意的是，在其它實施例中，當開關電路106包括PMOS電晶體時，開關電路106的第一端可為PMOS電晶體的源極，第二端可為PMOS電晶體的汲極，以及控制端可為PMOS電晶體的閘極。在正常模式下，節點電壓Vn亦因內部電路102的運作而具有第二特定電壓，使得節點電壓Vn與PMOS電晶體之源極的電壓之電壓差（又或是PMOS電晶體之源閘極電壓差）之絕對值大於PMOS電晶體的閾值電壓的絕對值，從而使PMOS電晶體為導通狀態。如此一來，開關SW1～SWn之控制端為電性耦接至具有參考電壓Vref之參考電壓端而具有較低電壓準位，開關SW1～SWn因此為導通狀態，可變阻抗電路104便可於訊號焊墊100與內部電路102之間提供低阻抗路徑。另外，在ESD模式下，節點電壓Vn亦因內部電路102未被供電而具有浮接電壓，使得節點電壓Vn與PMOS電晶體之源極的電壓之電壓差（又或是PMOS電晶體之源閘極電壓差）之絕對值小於PMOS電晶體的閾值電壓的絕對值，從而使PMOS電晶體為截止狀態。如此一來，開關SW1～SWn之控制端為電性浮接，開關SW1～SWn因此為截止狀態，可變阻抗電路104便可於訊號焊墊100與內部電路102之間提供高阻抗路徑。It is worth noting that in other embodiments, when the switch circuit 106 includes a PMOS transistor, the first terminal of the switch circuit 106 may be the source of the PMOS transistor, and the second terminal may be the drain of the PMOS transistor, and The control terminal can be the gate of a PMOS transistor. In the normal mode, the node voltage Vn also has a second specific voltage due to the operation of the internal circuit 102, so that the voltage difference between the node voltage Vn and the source voltage of the PMOS transistor (or the source gate voltage of the PMOS transistor) The absolute value of the difference) is greater than the absolute value of the threshold voltage of the PMOS transistor, so that the PMOS transistor is turned on. In this way, the control terminals of the switches SW1 to SWn are electrically coupled to the reference voltage terminal with the reference voltage Vref and have a lower voltage level. The switches SW1 to SWn are therefore turned on, and the variable impedance circuit 104 can be A low impedance path is provided between the signal pad 100 and the internal circuit 102. In addition, in the ESD mode, the node voltage Vn also has a floating voltage because the internal circuit 102 is not powered, so that the voltage difference between the node voltage Vn and the source voltage of the PMOS transistor (or the source gate of the PMOS transistor) The absolute value of the extreme voltage difference is smaller than the absolute value of the threshold voltage of the PMOS transistor, so that the PMOS transistor is in the off state. In this way, the control terminals of the switches SW1 ˜SWn are electrically floating, and the switches SW1 ˜SWn are therefore in an off state, and the variable impedance circuit 104 can provide a high impedance path between the signal pad 100 and the internal circuit 102.

具體而言，請參考第3圖，第3圖為本發明實施例另一IC 30之示意圖。IC 30與第2圖所示之IC 20大致相似，因此結構與功能相似之元件以相同符號表示，IC 30與IC 20之主要差別在於，IC 30還包括靜電放電偵測電路（ESD detection circuit）300，用以根據輸入訊號或ESD訊號產生節點電壓Vn。詳細來說，ESD偵測電路300具有第一端耦接於訊號焊墊100與可變阻抗電路104的第一端之間，第二端耦接參考電壓端，以及輸出端耦接開關電路106的控制端，用以輸出節點電壓Vn。第3圖的實施例以開關電路106包括NMOS電晶體Mn為例進行說明。在此情況下，ESD偵測電路300可包括電阻Res及電容Cap。電阻Res具有第一端耦接ESD偵測電路300的第一端，以及第二端耦接ESD偵測電路300的輸出端。電容Cap具有第一端耦接電阻Res的第二端，以及第二端耦接ESD偵測電路300的第二端。其中，可設計電阻Res與電容Cap的時間常數（time constant）大於ESD訊號的脈寬（pulse width）且小於輸入訊號的切換時間（如電阻Res與電容Cap的時間常數可設計為大於100 ns 且小於300 ns）。在其它實施例中，在內部電路102本身具有串聯於節點A與參考電壓端之間的電阻與電容的情況下，則可將其作為ESD偵測電路，也即開關電路106的控制端將與內部電路102耦接，並與內部電路102內的其它元件共用電阻與電容，而不需於內部電路102的外部再額外設置電阻Res與電容Cap。Specifically, please refer to FIG. 3, which is a schematic diagram of another IC 30 according to an embodiment of the present invention. IC 30 is roughly similar to IC 20 shown in Figure 2, so components with similar structures and functions are represented by the same symbols. The main difference between IC 30 and IC 20 is that IC 30 also includes an ESD detection circuit. 300, for generating a node voltage Vn according to the input signal or the ESD signal. In detail, the ESD detection circuit 300 has a first terminal coupled between the signal pad 100 and the first terminal of the variable impedance circuit 104, a second terminal coupled to the reference voltage terminal, and an output terminal coupled to the switch circuit 106 The control terminal is used to output the node voltage Vn. The embodiment in FIG. 3 is described by taking the switch circuit 106 including the NMOS transistor Mn as an example. In this case, the ESD detection circuit 300 may include a resistor Res and a capacitor Cap. The resistor Res has a first end coupled to the first end of the ESD detection circuit 300 and a second end coupled to the output end of the ESD detection circuit 300. The capacitor Cap has a first end coupled to the second end of the resistor Res, and a second end coupled to the second end of the ESD detection circuit 300. Among them, the time constant of the resistor Res and the capacitor Cap can be designed to be greater than the pulse width of the ESD signal and less than the switching time of the input signal (for example, the time constant of the resistor Res and the capacitor Cap can be designed to be greater than 100 ns and Less than 300 ns). In other embodiments, when the internal circuit 102 itself has a resistance and a capacitance connected in series between the node A and the reference voltage terminal, it can be used as an ESD detection circuit, that is, the control terminal of the switch circuit 106 will be connected to the The internal circuit 102 is coupled, and shares resistance and capacitance with other components in the internal circuit 102, and there is no need to additionally provide a resistor Res and a capacitor Cap outside the internal circuit 102.

在正常模式，輸入訊號會從訊號焊墊100經過節點A，由於設計電阻Res與電容Cap的時間常數小於輸入訊號的切換時間，電容Cap對輸入訊號而言相當於斷路（open circuit），使得節點電壓Vn被拉升至接近節點A上的電壓，節點電壓Vn與NMOS電晶體Mn之源極的電壓之電壓差（又或是NMOS電晶體Mn之閘源極電壓差）之絕對值大於NMOS電晶體Mn的閾值電壓的絕對值，從而使NMOS電晶體Mn為導通狀態。如此一來，開關SW1～SWn之控制端耦接至具有參考電壓Vref之參考電壓端而具有較低電壓準位，開關SW1～SWn因此為導通狀態，可變阻抗電路104便可於訊號焊墊100與內部電路102之間提供低阻抗路徑。在ESD模式，ESD訊號會從訊號焊墊100經過節點A，電容Cap對高頻的ESD訊號而言相當於短路（short circuit），使得節點電壓Vn被拉低至接近參考電壓端上的參考電壓Vref，或者說，由於設計電阻Res與電容Cap的時間常數大於ESD訊號的脈寬，而使得節點電壓Vn在ESD訊號的脈寬時間內被拉低至接近參考電壓端上的參考電壓Vref。因此，節點電壓Vn與NMOS電晶體Mn之源極的電壓之電壓差（又或是NMOS電晶體Mn之閘源極電壓差）之絕對值小於NMOS電晶體Mn的閾值電壓的絕對值，從而使NMOS電晶體Mn為截止狀態。如此一來，開關SW1～SWn之控制端為電性浮接，開關SW1～SWn因而為截止狀態，可變阻抗電路104便可於訊號焊墊100與內部電路102之間提供高阻抗路徑。In the normal mode, the input signal passes through the node A from the signal pad 100. Since the time constant of the design resistance Res and the capacitor Cap is less than the switching time of the input signal, the capacitor Cap is equivalent to an open circuit for the input signal, so that the node The voltage Vn is pulled up to be close to the voltage on the node A, and the absolute value of the voltage difference between the node voltage Vn and the source voltage of the NMOS transistor Mn (or the gate source voltage difference of the NMOS transistor Mn) is greater than that of the NMOS transistor The absolute value of the threshold voltage of the crystal Mn, so that the NMOS transistor Mn is turned on. In this way, the control terminals of the switches SW1 to SWn are coupled to the reference voltage terminal with the reference voltage Vref and have a lower voltage level. The switches SW1 to SWn are therefore turned on, and the variable impedance circuit 104 can be connected to the signal pad A low impedance path is provided between 100 and the internal circuit 102. In the ESD mode, the ESD signal passes through the node A from the signal pad 100. The capacitor Cap is equivalent to a short circuit for high-frequency ESD signals, so that the node voltage Vn is pulled down to be close to the reference voltage on the reference voltage terminal. Vref, in other words, because the time constant of the design resistor Res and the capacitor Cap is greater than the pulse width of the ESD signal, the node voltage Vn is pulled down to be close to the reference voltage Vref on the reference voltage terminal during the pulse width of the ESD signal. Therefore, the absolute value of the voltage difference between the node voltage Vn and the source voltage of the NMOS transistor Mn (or the gate-source voltage difference of the NMOS transistor Mn) is smaller than the absolute value of the threshold voltage of the NMOS transistor Mn, so that The NMOS transistor Mn is in an off state. In this way, the control terminals of the switches SW1 ˜SWn are electrically floating, and the switches SW1 ˜SWn are therefore in an off state, and the variable impedance circuit 104 can provide a high impedance path between the signal pad 100 and the internal circuit 102.

另一方面，請參考第4圖，第4圖為本發明實施例另一IC 40之示意圖。IC 40與第3圖所示之IC 30大致相似，因此結構與功能相似之元件以相同符號表示，IC 40與IC 30之主要差別在於，第4圖的實施例以開關電路106包括PMOS電晶體Mp為例進行說明。而IC 40所包括之ESD偵測電路400外部連結方式與ESD偵測電路300相似，惟所包含之元件不同。在開關電路106包括PMOS電晶體Mp的情況下，ESD偵測電路400可包括至少一二極體以及阻抗元件Z。值得注意的是，二極體的數量與輸入訊號的操作電壓有關。進一步而言，可設計至少一二極體之整體導通電壓大於輸入訊號在正常模式下的操作電壓。阻抗元件Z可包括電感及/或電阻。也就是說，ESD偵測電路400在設計上具有彈性。第4圖的實施例以ESD偵測電路400包括m個二極體D1～Dm，且阻抗元件Z包括電阻為例進行說明。m個二極體D1～Dm可以形成堆疊結構。詳細來說，二極體Dj具有第一端耦接ESD偵測電路400的第一端，以及第二端耦接ESD偵測電路400的輸出端。二極體D1具有第一端耦接ESD偵測電路400的第一端，以及第二端耦接二極體Dj的第一端。二極體Dm具有第一端耦接二極體Dj的第二端，以及第二端耦接ESD偵測電路400的輸出端。阻抗元件Z具有第一端耦接二極體Dm的第二端，以及第二端耦接ESD偵測電路400的第二端。其中，變數m及j為正整數，1

j

m。然而，當ESD偵測電路400僅包括二極體Dj及阻抗單元Z時，則阻抗單元Z的第一端耦接二極體Dj的第二端。二極體D1～Dm的第一端可為陽極，第二端可為陰極。在其它實施例中，亦可使用以二極體形式連接（diode connected）的電晶體取代ESD偵測電路400內的至少一二極體D1～Dm。此外，在其它實施例中，在內部電路102本身具有串聯於節點A與參考電壓端之間的至少一二極體與阻抗元件的情況下，則可將其作為ESD偵測電路，也即開關電路106的控制端將與內部電路102耦接，並與內部電路102內的其它元件共用至少一二極體與阻抗元件，而不需於內部電路102的外部再額外設置至少一二極體D1～Dm與阻抗元件Z。 On the other hand, please refer to FIG. 4, which is a schematic diagram of another IC 40 according to an embodiment of the present invention. The IC 40 is roughly similar to the IC 30 shown in Figure 3, so components with similar structures and functions are represented by the same symbols. The main difference between the IC 40 and the IC 30 is that the embodiment in Figure 4 uses the switching circuit 106 to include a PMOS transistor. Take Mp as an example. The external connection method of the ESD detection circuit 400 included in the IC 40 is similar to that of the ESD detection circuit 300, but the included components are different. When the switch circuit 106 includes a PMOS transistor Mp, the ESD detection circuit 400 may include at least one diode and an impedance element Z. It is worth noting that the number of diodes is related to the operating voltage of the input signal. Furthermore, the overall conduction voltage of at least one diode can be designed to be greater than the operating voltage of the input signal in the normal mode. The impedance element Z may include an inductance and/or a resistance. In other words, the ESD detection circuit 400 has flexibility in design. In the embodiment of FIG. 4, the ESD detection circuit 400 includes m diodes D1 to Dm, and the impedance element Z includes a resistor as an example for description. The m diodes D1 to Dm can form a stacked structure. In detail, the diode Dj has a first end coupled to the first end of the ESD detection circuit 400, and a second end coupled to the output end of the ESD detection circuit 400. The diode D1 has a first end coupled to the first end of the ESD detection circuit 400, and a second end coupled to the first end of the diode Dj. The diode Dm has a first end coupled to the second end of the diode Dj, and a second end coupled to the output end of the ESD detection circuit 400. The impedance element Z has a first end coupled to the second end of the diode Dm, and a second end coupled to the second end of the ESD detection circuit 400. Among them, the variables m and j are positive integers, 1

j

m. However, when the ESD detection circuit 400 only includes the diode Dj and the impedance unit Z, the first end of the impedance unit Z is coupled to the second end of the diode Dj. The first ends of the diodes D1 to Dm may be anodes, and the second ends may be cathodes. In other embodiments, diode connected transistors can also be used to replace at least one diode D1 to Dm in the ESD detection circuit 400. In addition, in other embodiments, when the internal circuit 102 itself has at least one diode and impedance element connected in series between the node A and the reference voltage terminal, it can be used as an ESD detection circuit, that is, a switch The control terminal of the circuit 106 will be coupled to the internal circuit 102, and share at least one diode and impedance element with other components in the internal circuit 102, without the need to additionally provide at least one diode D1 outside the internal circuit 102 ~Dm and impedance element Z.

在正常模式，輸入訊號會從訊號焊墊100經過節點A，由於設計二極體D1～Dm之整體導通電壓大於輸入訊號在正常模式下的操作電壓，也就是說，節點A上的電壓會小於二極體D1～Dm之整體導通電壓，因此二極體D1～Dm為截止狀態，使得節點電壓Vn為接近參考電壓端上的參考電壓Vref，節點電壓Vn與PMOS電晶體Mp之源極的電壓之電壓差（又或是PMOS電晶體Mp之源閘極電壓差）之絕對值大於PMOS電晶體Mp的閾值電壓的絕對值，從而使PMOS電晶體Mp為導通狀態。如此一來，開關SW1～SWn之控制端耦接至具有參考電壓Vref之參考電壓端而具有較低電壓準位，開關SW1～SWn因而為導通狀態，可變阻抗電路104便可於訊號焊墊100與內部電路102之間提供低阻抗路徑。在ESD模式，ESD訊號會從訊號焊墊100經過節點A，節點A上的電壓會大於二極體D1～Dm之整體導通電壓，因此二極體D1～Dm為導通狀態，使得節點電壓Vn可視為節點A上的電壓減去二極體D1～Dm之整體導通電壓，節點電壓Vn與PMOS電晶體之源極的電壓之電壓差（又或是PMOS電晶體Mp之源閘極電壓差）之絕對值小於PMOS電晶體的閾值電壓的絕對值為，從而使PMOS電晶體Mp為截止狀態。如此一來，開關SW1～SWn之控制端為電性浮接，開關SW1～SWn因而為截止狀態，可變阻抗電路104便可於訊號焊墊100與內部電路102之間提供高阻抗路徑。In the normal mode, the input signal will pass through the node A from the signal pad 100. Because the overall conduction voltage of the design diodes D1～Dm is greater than the operating voltage of the input signal in the normal mode, that is, the voltage on node A will be less than The overall turn-on voltage of the diodes D1～Dm, so the diodes D1～Dm are in the off state, so that the node voltage Vn is close to the reference voltage Vref on the reference voltage terminal, the node voltage Vn and the source voltage of the PMOS transistor Mp The absolute value of the voltage difference (or the source gate voltage difference of the PMOS transistor Mp) is greater than the absolute value of the threshold voltage of the PMOS transistor Mp, so that the PMOS transistor Mp is turned on. In this way, the control terminals of the switches SW1 to SWn are coupled to the reference voltage terminal with the reference voltage Vref and have a lower voltage level. The switches SW1 to SWn are thus turned on, and the variable impedance circuit 104 can be connected to the signal pad A low impedance path is provided between 100 and the internal circuit 102. In the ESD mode, the ESD signal passes through node A from the signal pad 100, and the voltage on node A is greater than the overall conduction voltage of the diodes D1 to Dm. Therefore, the diodes D1 to Dm are in the on state, making the node voltage Vn visible Is the voltage on node A minus the overall conduction voltage of diodes D1～Dm, the voltage difference between node voltage Vn and the source voltage of the PMOS transistor (or the source gate voltage difference of the PMOS transistor Mp) The absolute value is smaller than the absolute value of the threshold voltage of the PMOS transistor, so that the PMOS transistor Mp is turned off. In this way, the control terminals of the switches SW1 ˜SWn are electrically floating, and the switches SW1 ˜SWn are therefore in an off state, and the variable impedance circuit 104 can provide a high impedance path between the signal pad 100 and the internal circuit 102.

請參考第5圖，第5圖為本發明實施例另一IC 50之示意圖。IC 50與第1圖所示之IC 10大致相似，因此結構與功能相似之元件以相同符號表示，IC 50與IC 10之主要差別在於，IC 50另包括ESD偵測電路500以及靜電放電保護裝置（ESD protection device）502。ESD偵測電路500可以第3圖所示之ESD偵測電路300或第4圖所示之ESD偵測電路400實現，於此不再贅述以求簡潔。ESD保護裝置502具有第一端耦接於訊號焊墊100與ESD偵測電路500的第一端之間（或者說ESD保護裝置502第一端耦接於節點A），以及第二端耦接參考電壓端。ESD保護裝置502用以在ESD模式提供ESD訊號放電路徑。進一步而言，ESD訊號放電路徑是用以將ESD訊號分流（shunt）到參考電壓端，以減少ESD訊號的強度。換言之，在ESD模式下，IC 50的結構不僅可透過ESD保護裝置502將ESD訊號分流到參考電壓端，還可透過可變阻抗電路104提供的高阻抗路徑使ESD訊號更加不易直接進入內部電路102（如高阻抗路徑相當於是用以為內部電路102提供額外的承受ESD保護裝置502的導通電阻與ESD訊號所產生的電壓之能力，進而阻擋ESD訊號進入內部電路102）。亦即，ESD保護裝置502與可變阻抗電路104可用以對內部電路102提供雙層ESD保護機制，有利於提升IC 50的ESD保護能力。值得注意的是，在上述實施例中，是透過可變阻抗電路104提供的高阻抗路徑來降低ESD訊號進入內部電路102，而可不增加ESD保護裝置502之電路尺寸。因此，相較於習知技術透過增加ESD保護裝置之電路尺寸（如增加為原尺寸的3倍）的做法，可變阻抗電路104（如尺寸為ESD保護裝置502的0.3倍）與ESD保護裝置502可具有較小的整體電路面積（如為ESD保護裝置502的1.3倍），且相對存在較小的寄生電容。在其它實施例中，可不額外設置ESD偵測電路500，而是將開關電路106的控制端耦接內部102，以使節點電壓Vn與內部電路102的電源啟閉狀態有關，亦或是節點電壓Vn可由內部電路102內的元件提供。此外，節點電壓Vn亦可由其它電路提供。Please refer to FIG. 5, which is a schematic diagram of another IC 50 according to an embodiment of the present invention. IC 50 is roughly similar to IC 10 shown in Figure 1, so components with similar structures and functions are represented by the same symbols. The main difference between IC 50 and IC 10 is that IC 50 also includes an ESD detection circuit 500 and an electrostatic discharge protection device. (ESD protection device) 502. The ESD detection circuit 500 can be implemented by the ESD detection circuit 300 shown in FIG. 3 or the ESD detection circuit 400 shown in FIG. The ESD protection device 502 has a first end coupled between the signal pad 100 and the first end of the ESD detection circuit 500 (or the first end of the ESD protection device 502 is coupled to node A), and a second end is coupled Reference voltage terminal. The ESD protection device 502 is used to provide an ESD signal discharge path in the ESD mode. Furthermore, the ESD signal discharge path is used to shunt the ESD signal to the reference voltage terminal to reduce the intensity of the ESD signal. In other words, in the ESD mode, the structure of the IC 50 can not only shunt the ESD signal to the reference voltage terminal through the ESD protection device 502, but also make the ESD signal more difficult to directly enter the internal circuit 102 through the high impedance path provided by the variable impedance circuit 104 (For example, the high-impedance path is equivalent to providing the internal circuit 102 with an additional ability to withstand the voltage generated by the on-resistance of the ESD protection device 502 and the ESD signal, thereby preventing the ESD signal from entering the internal circuit 102). That is, the ESD protection device 502 and the variable impedance circuit 104 can be used to provide a double-layer ESD protection mechanism for the internal circuit 102, which is beneficial to improve the ESD protection capability of the IC 50. It is worth noting that in the above embodiment, the high impedance path provided by the variable impedance circuit 104 is used to reduce the ESD signal entering the internal circuit 102 without increasing the circuit size of the ESD protection device 502. Therefore, compared with the conventional technique of increasing the circuit size of the ESD protection device (e.g. 3 times the original size), the variable impedance circuit 104 (e.g. the size is 0.3 times the size of the ESD protection device 502) and the ESD protection device The 502 may have a smaller overall circuit area (for example, 1.3 times that of the ESD protection device 502), and relatively small parasitic capacitance. In other embodiments, the ESD detection circuit 500 may not be additionally provided, but the control terminal of the switch circuit 106 is coupled to the internal 102, so that the node voltage Vn is related to the power on/off state of the internal circuit 102, or the node voltage Vn can be provided by components in the internal circuit 102. In addition, the node voltage Vn can also be provided by other circuits.

詳細來說，請參考第6圖，第6圖為本發明實施例第5圖所示之IC 50之電路示意圖。IC 50與第3圖所示之IC 30大致相似，因此結構與功能相似之元件以相同符號表示，IC 50與IC 30之主要差別在於，IC 50還包括ESD保護裝置502，且ESD保護裝置502係以電阻、電容、反向器及NMOS電晶體結構實現。在ESD模式，電阻、電容及反向器用以控制NMOS電晶體為導通狀態，以提供ESD訊號放電路徑。第6圖之電路操作為本領域通常知識者所熟知，於此不再贅述以求簡潔。此外，請參考第7圖至第10圖，第7圖至第10圖為本發明實施例第6圖所示之ESD保護裝置502之變化實施例。如第7圖至第10圖所示，ESD保護裝置502之電路結構可分別以矽控整流器（Silicon-Controlled Rectifier，SCR）結構、MOS電晶體結構、二極體結構以及電感實現，用以在ESD模式提供ESD訊號放電路徑。第7圖至第10圖之電路操作為本領域通常知識者所熟知，於此不再贅述以求簡潔。For details, please refer to Fig. 6, which is a circuit diagram of the IC 50 shown in Fig. 5 of the embodiment of the present invention. IC 50 is roughly similar to IC 30 shown in Figure 3, so components with similar structures and functions are represented by the same symbols. The main difference between IC 50 and IC 30 is that IC 50 also includes ESD protection device 502, and ESD protection device 502 It is realized with resistor, capacitor, inverter and NMOS transistor structure. In the ESD mode, resistors, capacitors, and inverters are used to control the NMOS transistor to be in a conductive state to provide an ESD signal discharge path. The circuit operation in Figure 6 is well known to those skilled in the art, and will not be repeated here for the sake of brevity. In addition, please refer to FIGS. 7-10. FIGS. 7-10 are variations of the ESD protection device 502 shown in FIG. 6 of the embodiment of the present invention. As shown in Figures 7 to 10, the circuit structure of the ESD protection device 502 can be implemented with a silicon-controlled rectifier (SCR) structure, a MOS transistor structure, a diode structure, and an inductor. ESD mode provides ESD signal discharge path. The circuit operations in FIGS. 7 to 10 are well known to those skilled in the art, and will not be repeated here for the sake of brevity.

綜上所述，本發明可適當設計電路以在正常模式形成低阻抗路徑阻，使內部電路可正常接收並處理輸入訊號，而不影響內部電路的運作。並可在ESD模式形成高阻抗路徑，以降低ESD訊號對內部電路102的影響。此外，本發明可透過適當設計可變阻抗電路的電路尺寸以及其所包括的開關數量，以具有較小電路面積及寄生電容，不但設計上較為簡單、也較具有彈性，且生產成本較低。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 In summary, the present invention can appropriately design the circuit to form a low impedance path resistance in the normal mode, so that the internal circuit can receive and process the input signal normally without affecting the operation of the internal circuit. A high-impedance path can be formed in the ESD mode to reduce the influence of the ESD signal on the internal circuit 102. In addition, the present invention can appropriately design the circuit size of the variable impedance circuit and the number of switches included to have a smaller circuit area and parasitic capacitance. The design is simpler, more flexible, and lower in production cost. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10, 20, 30, 40, 50:積體電路 100:訊號焊墊 102:內部電路 104:可變阻抗電路 106:開關電路 300, 400, 500:靜電放電偵測電路 502:靜電放電保護裝置 A, B:節點 Cap:電容 D1~Dm:二極體 Mn:NMOS電晶體 Mp:PMOS電晶體 Res:電阻 SW1~SWn:開關 Vn:節點電壓 Vref, Vdd:參考電壓 Z:阻抗元件 10, 20, 30, 40, 50: integrated circuit 100: signal pad 102: internal circuit 104: Variable impedance circuit 106: switch circuit 300, 400, 500: Electrostatic discharge detection circuit 502: Electrostatic discharge protection device A, B: node Cap: Capacitance D1~Dm: Diode Mn: NMOS transistor Mp: PMOS transistor Res: resistance SW1~SWn: switch Vn: node voltage Vref, Vdd: Reference voltage Z: impedance element

第1圖為本發明實施例一積體電路之示意圖。第2圖為本發明實施例另一積體電路之示意圖。第3圖為本發明實施例另一積體電路之示意圖。第4圖為本發明實施例另一積體電路之示意圖。第5圖為本發明實施例另一積體電路之示意圖。第6圖為本發明實施例第5圖所示之積體電路之電路示意圖。第7圖至第10圖為本發明實施例第6圖所示之一靜電放電保護裝置之變化實施例。 Figure 1 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. Figure 2 is a schematic diagram of another integrated circuit according to an embodiment of the present invention. Figure 3 is a schematic diagram of another integrated circuit according to an embodiment of the present invention. Figure 4 is a schematic diagram of another integrated circuit according to an embodiment of the present invention. Figure 5 is a schematic diagram of another integrated circuit according to an embodiment of the present invention. Fig. 6 is a circuit diagram of the integrated circuit shown in Fig. 5 of the embodiment of the present invention. Figures 7 to 10 are modified examples of the electrostatic discharge protection device shown in Figure 6 of the embodiment of the present invention.

10:積體電路 100:訊號焊墊 102:內部電路 104:可變阻抗電路 106:開關電路 A, B:節點 Vref:參考電壓 Vn:節點電壓 10: Integrated circuit 100: signal pad 102: internal circuit 104: Variable impedance circuit 106: switch circuit A, B: node Vref: Reference voltage Vn: node voltage

Claims

An integrated circuit with an electrostatic discharge (ESD) protection mechanism, including: A signal pad for receiving an input signal in a normal mode and for receiving an electrostatic discharge signal in an electrostatic discharge mode; An internal circuit for processing the input signal in the normal mode; A variable impedance circuit has a first end coupled to the signal pad, a second end coupled to the internal circuit, and a control end. The variable impedance circuit is used to connect the signal pad and the signal pad in the normal mode Providing a low impedance path between the internal circuits, and for providing a high impedance path between the signal pad and the internal circuit in the electrostatic discharge mode; and A switch circuit having a first terminal coupled to the control terminal of the variable impedance circuit, a second terminal coupled to a reference voltage terminal, and a control terminal for receiving a node voltage, the switch circuit is used for The normal mode enables the control terminal of the variable impedance circuit to have a first specific voltage, and is used to make the control terminal of the variable impedance circuit electrically floating in the electrostatic discharge mode.

The integrated circuit described in claim 1, wherein in the normal mode, an absolute value of a voltage difference between the node voltage and a voltage at the first terminal or a voltage at the second terminal of the switching circuit An absolute value greater than a threshold voltage of the switch circuit makes the switch circuit in a conducting state.

In the integrated circuit described in item 2 of the scope of patent application, the control terminal of the variable impedance circuit is electrically coupled to the reference voltage terminal to have the first specific voltage.

The integrated circuit described in claim 1, wherein in the electrostatic discharge mode, the voltage difference between the node voltage and the voltage at the first terminal or the voltage at the second terminal of the switching circuit is absolute The value is less than an absolute value of a threshold voltage of the switch circuit, so that the switch circuit is turned off.

The integrated circuit described in item 4 of the scope of patent application, wherein the node voltage has a floating voltage.

In the integrated circuit described in item 1 of the scope of patent application, the control terminal of the switch circuit is coupled to the internal circuit, and the node voltage is related to a power on/off state of the internal circuit.

The integrated circuit as described in item 6 of the scope of patent application, in which In the normal mode, the internal circuit is in a power on state, so that the node voltage has a second specific voltage; and In the electrostatic discharge mode, the internal circuit is in a power off state, so that the node voltage has a floating voltage.

The integrated circuit as described in item 1 of the scope of patent application also includes: A first electrostatic discharge detection circuit is used to generate the node voltage according to the input signal or the electrostatic discharge signal.

According to the integrated circuit described in claim 8, wherein the first electrostatic discharge detection circuit has a first end coupled between the signal pad and the first end of the variable impedance circuit, a The second terminal is coupled to the reference voltage terminal, and an output terminal is coupled to the control terminal of the switch circuit for outputting the node voltage.

According to the integrated circuit described in item 9 of the scope of patent application, the switch circuit includes a PMOS transistor, and the first electrostatic discharge detection circuit includes: At least one first diode having a first end coupled to the first end of the first electrostatic discharge detection circuit, and a second end coupled to the output end of the first electrostatic discharge detection circuit; and A first impedance element has a first end coupled to the second end of the at least one first diode, and a second end coupled to the second end of the first electrostatic discharge detection circuit.

According to the integrated circuit described in item 9 of the scope of patent application, wherein the switch circuit includes an NMOS transistor, and the first electrostatic discharge detection circuit includes: A first resistor having a first end coupled to the first end of the first electrostatic discharge detection circuit, and a second end coupled to the output end of the first electrostatic discharge detection circuit; and A first capacitor has a first end coupled to the second end of the first resistor, and a second end coupled to the second end of the first electrostatic discharge detection circuit.

The integrated circuit described in claim 11, wherein a time constant of the first resistor and the first capacitor is greater than a pulse width of the electrostatic discharge signal and less than a switching time of the input signal.

The integrated circuit according to claim 1, wherein the variable impedance circuit includes at least one switch, and a first switch of the at least one switch has a first end coupled to the first terminal of the variable impedance circuit One end, a second end is coupled to the second end of the variable impedance circuit, and a control end is coupled to the control end of the variable impedance circuit.

The integrated circuit according to claim 13, wherein a second switch of the at least one switch has a first end coupled to the second end of the first switch, and a second end coupled to the The second terminal of the variable impedance circuit and a control terminal are coupled to the control terminal of the variable impedance circuit.

The integrated circuit described in the scope of patent application, wherein the first switch includes a PMOS transistor, a PFET or a pHEMT.

The integrated circuit as described in item 15 of the scope of patent application, wherein the switch circuit includes a PMOS transistor or an NMOS transistor.

The integrated circuit described in item 16 of the scope of patent application also includes: A second electrostatic discharge detection circuit has a first terminal coupled to the signal pad and the first terminal of the variable impedance circuit, a second terminal coupled to the reference voltage terminal, and an output terminal coupled to the The control terminal of the switch circuit is used to output the node voltage.

The integrated circuit according to item 17 of the scope of patent application, wherein the switch circuit includes the PMOS transistor, and the second electrostatic discharge detection circuit includes: At least one second diode having a first end coupled to the first end of the second electrostatic discharge detection circuit, and a second end coupled to the output end of the second electrostatic discharge detection circuit; and A second impedance element has a first end coupled to the second end of the at least one second diode, and a second end coupled to the second end of the second electrostatic discharge detection circuit.

The integrated circuit according to item 17 of the scope of patent application, wherein the switch circuit includes the NMOS transistor, and the second electrostatic discharge detection circuit includes: A second resistor having a first end coupled to the first end of the second electrostatic discharge detection circuit, and a second end coupled to the output end of the second electrostatic discharge detection circuit; and A second capacitor has a first end coupled to the second end of the second resistor, and a second end coupled to the second end of the second electrostatic discharge detection circuit.

The integrated circuit described in item 17 of the scope of patent application, wherein the integrated circuit further includes: An electrostatic discharge protection device having a first end coupled between the signal pad and the first end of the second electrostatic discharge detection circuit, and a second end coupled to the reference voltage end, the electrostatic discharge The protection device is used for providing an electrostatic discharge signal discharge path in the electrostatic discharge mode.