JP6784820B2 - ESD protection circuit - Google Patents

Description

An embodiment of the present invention relates to an ESD protection circuit that protects an internal circuit from a surge caused by ESD (Electrostatic Discharge) in a semiconductor integrated circuit.

An ESD protection circuit is used to protect an internal circuit in a semiconductor device from a surge generated by ESD from a power supply terminal or the like. The ESD protection circuit detects a voltage rise in the power supply wiring due to a surge, and detects a shunt MOS (Metal Oxid) connected between the power supply wiring and the ground wiring.
e Semiconductor) Makes the transistor conductive and releases the charge from the surge to the ground wiring. An RC trigger circuit that generates a trigger signal by using a series junction of a resistor (R) and a capacitor (C) is used as a means for detecting a voltage rise due to a surge and making the shunt MOS transistor conductive.

JP-A-2015-46507

It is desirable that the shunt transistor for discharging the electric charge generated by the surge in the ESD protection circuit has a large driving force, but the larger the driving force, the larger the leakage current in the outrageous state, and the power consumption of the semiconductor device. Will be higher. On the other hand, if the leakage current is suppressed to reduce the power consumption of the semiconductor device, the driving power of the shunt transistor is lowered, the discharge property of the ESD protection circuit is lowered, and the shunt transistor may be destroyed. It is desired to reduce power consumption while maintaining the discharge performance of the ESD protection circuit.

The ESD protection circuit of the embodiment is connected between the first power supply wiring and the second power supply wiring, and has a first capacitor, a first resistor, a diode, a MOS transistor, a second resistor, and a second capacitor.
It includes a capacitor and a first inverter circuit. One end of the first capacitor is the first.
Connected to the power supply wiring. One end of the first resistor is connected to the other end of the first capacitor via a connection point, and the other end is connected to the second power supply wiring. The cathode of the diode is connected to the second power supply wiring. In the MOS transistor, the source is connected to the anode of the diode, the drain is connected to the first power supply wiring, and the well region is connected to the connection point. One end of the second resistor is connected to the first power supply wiring. One end of the second capacitor is connected to the other end of the second resistor. In the first inverter circuit, an input terminal is connected to the other end of the second resistor, and an output terminal is connected to the gate of the MOS transistor.

The figure which shows the structure of the ESD protection circuit which concerns on Embodiment 1. FIG. The figure which shows an example of the structure of the RC trigger circuit which concerns on Embodiment 1. FIG. The figure which shows the structure of the ESD protection circuit which concerns on a comparative example. The figure explaining the operation of the ESD protection circuit which concerns on a comparative example. The figure explaining the operation of the ESD protection circuit which concerns on Embodiment 1. FIG. The figure explaining the substrate bias effect. The figure explaining the substrate bias effect. The figure which shows the structure of the ESD protection circuit which concerns on Embodiment 2. The figure which shows an example of the structure of the RC trigger circuit which concerns on Embodiment 2. The figure explaining the structure of the ESD protection circuit which concerns on Embodiment 3.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The figure used in the description in the embodiment is a schematic diagram for facilitating the description, and the shape, dimensions, magnitude relationship, etc. of each element in the figure are not necessarily shown in the figure in actual implementation. This is not always the case, and it can be changed as appropriate within the range in which the effects of the present invention can be obtained. Elements having similar properties, functions, or characteristics use the same reference number or the same reference symbol, and the description thereof will be omitted.

(Embodiment 1)
The first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing a configuration of an ESD protection circuit according to a first embodiment of the present invention in a semiconductor integrated circuit. FIG. 2 shows R
This is an example of a configuration of a C trigger circuit.

1, the semiconductor integrated circuit 1, the potential lower than the first power supply terminal TVDD, and the first potential V _DD is connected to a first power source for supplying a first electric potential V _DD (not shown) a second power supply terminal TVSS connected to the second power source (not shown) for supplying a second electric potential _{V SS.} Here, the second power source as a ground, the second voltage V _SS explaining an embodiment 1 as a ground potential. Further, the first power source is simply a power source, and the first potential _VDD is a power source potential.
Will be explained.

The semiconductor integrated circuit 1 includes a first power supply wiring L VDD, a second power supply wiring LVSS, an ESD protection circuit 100, and an internal circuit 101. The internal circuit 101 is a core portion including a CPU (Central Processing Unit) constituting the semiconductor integrated circuit 1, a memory, and the like.

The first power supply wiring L _VDD electrically connects the first power supply terminal T _VDD and one end of the internal circuit, and supplies the power potential _VDD supplied to the first power supply terminal T _VDD to one end of the internal circuit 101. The second power supply wiring LVSS electrically connects the second power supply terminal TVSS and the other end of the internal circuit 101, and supplies the ground potential supplied to the second power supply terminal TVSS to the other end of the internal circuit 101.

The ESD protection circuit 100 is connected between the first power supply wiring L VDD and the second power supply wiring LVSS. When a surge due to ESD enters the semiconductor integrated circuit 1 from the first power supply terminal T VDD, the ESD protection circuit 100 operates and discharges the electric charge generated by the surge due to ESD to the second power supply wiring LVSS, which is generated by the surge. A large amount of electric charge was generated in the internal circuit 101.
Prevents the internal circuit 101 from being invaded and destroyed.

The ESD protection circuit 100 includes an RC trigger circuit RCT1, a shunt nMOS transistor (n-channel MOS transistor) Mn, a diode D, a capacitor C2, and a resistor R.
Has 2. In the diode D, the anode is connected to the first power supply wiring (L VDD) and the cathode is connected to the second power supply wiring LVSS. The source and drain of the shunt nMOS transistor Mn are connected in series with the diode D between the first power supply wiring L VDD and the second power supply wiring LVSS. That is, the source of the shunt nMOS transistor is connected to the anode of the diode D, and the drain of the shunt nMOS transistor is the first power supply wiring L VDD.
Connected to. The cathode of the diode D is connected to the second power supply wiring.

Here, the diode D is, for example, a pn junction diode in which an n-type semiconductor and a p-type semiconductor are bonded. In the present embodiment, the case where the pn junction is one stage will be described, but it is also possible to use a multi-stage pn junction. The diode D is not limited to the pn junction type diode, and may be a parasitic diode of a MOS transistor, a diode-connected bipolar transistor, or the like.

In the case of an nMOS transistor, for example, the parasitic diode of the MOS transistor has a gate, a drain, and a back gate connected to each other to function as an anode, and the source functions as a cathode. In the case of a pMOS transistor (p-channel transistor), the gate, drain and back gate are connected and function as a cathode, and the source functions as an anode.

Further, in the case of a diode-connected bipolar transistor, in the case of an npn transistor, the base functions as an anode, and the emitter and collector are connected to function as a cathode. In the case of a pnp transistor, the base functions as a cathode, and the emitter and collector are connected to function as an anode.

The source and drain of the shunt nMOS transistor are n-type semiconductors and are formed in the well region of the p-type semiconductor. The gate electrode is connected to the source, well region, through the gate insulating film.
And provided on the drain. The backgate electrode (not shown) is provided so as to be electrically connected to the well region, and the potential of the well region is adjusted via the backgate electrode.

The capacitor C2 is connected between the first power supply wiring L VDD and the second power supply wiring LVSS.
The resistor R2 is connected between the first power supply wiring L VDD and the second power supply wiring LVSS so as to be connected in series with the capacitor C2. That is, one end of the capacitor C2 is the first power supply wiring LVD.
It is connected to D, and the other end of the capacitor C2 is connected to one end of the resistor R2 at the connection point n2. The other end of the resistor R2 is connected to the second power supply wiring LVSS. The connection point n2 is a shunt nMO.
It is connected to the well region of the S transistor via a back gate electrode. The potential of the connection point n2 is supplied to the well region.

As shown in FIG. 2, the RC trigger circuit RCT1 includes a first resistor R1, a first capacitor C1, and a first inverter circuit INV1. One end of the first resistor is the first power supply wiring LV
It is connected to the DD, and the other end is connected to one end of the first capacitor C1 at the connection point n1. The other end of the first capacitor C1 is connected to the second power supply wiring LVSS. The first resistor R1 and the first capacitor C1 are connected in series between the first power supply wiring L VDD and the second power supply wiring LVSS.

The other end of the first resistor R1 is connected to the input terminal of the first inverter circuit INV1. 1st
The output terminal of the inverter INV1 is connected to the gate of the shunt nMOS transistor. When a surge is applied to the first power supply terminal T _VDD , the potential _VDD of the first power supply wiring L _VDD rises, and in synchronization with this, the shunt n from the first inverter circuit INV1 of the RC trigger circuit.
A trigger signal SC1 that makes the MOS transistor conductive is output (details will be described later).

Next, the operation of the ESD protection circuit according to the present embodiment will be described in comparison with a comparative example. Figure 3
The ESD protection circuit 2000 according to a comparative example will be described. Also in the comparative example, the ESD protection circuit 2000 is the first power supply wiring LV in the semiconductor integrated circuit 1000 as in the present embodiment.
It is joined between the DD and the second power supply wiring LVSS. The internal circuit 101 is the first power supply wiring L.
It is connected between VDD and the second power supply wiring LVSS. When a surge due to ESD enters the semiconductor integrated circuit 1000 from the first power supply terminal T VDD, the ESD protection circuit 2000 operates, and the electric charge generated by the surge is transferred from the first power supply wiring to the second power supply wiring via the ESD protection circuit 2000. Be released. This prevents the electric charge generated by the surge from entering the internal circuit 101.

The protection circuit 2000 according to the comparative example includes an RC trigger circuit RCT1, a shunt nMOS transistor Mn, and a diode D in the same manner as the ESD protection circuit 100 according to the present embodiment. The ESD protection circuit 2000 according to the comparative example and the ESD protection circuit 100 according to the present embodiment are
It differs in the following points. The back gate of the shunt nMOS transistor of the ESD protection circuit 2000 according to the comparative example is connected to the second power supply wiring. That is, the potential in the well region of the shunt nMOS transistor Mn is fixed to the ground potential.

The operation of the ESD protection circuit 2000 according to the comparative example will be described with reference to FIG. FIG. 4 shows the gate potential of the shunt nMOS transistor, the drain current of the shunt nMOS transistor, and the drain potential of the shunt nMOS transistor when a surge due to ESD enters the semiconductor integrated circuit 1000 from the first power supply terminal (first in the figure). (Described by the power supply potential _VDD applied to the power supply wiring), the source potential of the shunt nMOS transistor, and the shunt nM.
The time change of the back gate potential of the OS transistor is shown. The vertical axis on the left side shows the potential standardized based on the maximum value of the drain potential of the ESD protection circuit according to the comparative example. The vertical axis on the right is
The current standardized based on the maximum value of the drain current of the ESD protection circuit 2000 according to the comparative example is shown. The horizontal axis shows the time change.

When a surge caused by ESD is applied to the first power supply wiring L VDD in the semiconductor integrated circuit,
The potential (drain potential) _{VDD of} the first power supply wiring L _VDD increases due to the amount of electric charge generated by the surge. In the RC trigger circuit RCT1, within the time constant R1 × C1 of the resistance / capacitance product of the first resistor R1 and the first capacitor C1, the first resistor R1 and the first capacitor C1
The potential of the connection point n1 is lower than the potential of the first power supply wiring L VDD.

Since the power supply of the first inverter circuit INV1 is supplied with the same power potential _VDD as that of the first power supply wiring L _VDD , the potential of the input of the first inverter circuit INV1 is set within the time corresponding to the time constant of the RC trigger circuit. It becomes lower than the source potential of the p-channel MOS transistor in the first inverter circuit. As a result, the p-channel MOS transistor is turned on (conducting), the first inverter circuit INV1 outputs a high level, and this output is the RC trigger circuit R.
It becomes the trigger signal SC1 output from CT1.

Before the surge is applied, the potential of the connection point n1 between the first resistor R1 and the first capacitor C1 is the same as the potential of the first power supply wiring L VDD. In this case, the first inverter circuit INV
The p-channel MOS transistor of 1 is turned off (non-conducting), and the first inverter circuit INV
1 outputs a low level as a trigger signal SC1.

This trigger signal SC1 is supplied to the gate of the shunt nMOS transistor Mn. As shown in FIG. 4, since the trigger signal becomes high level only within the time corresponding to the time constant of the RC trigger circuit RCT1 after the surge is applied to the first power supply wiring L VDD, the gate potential of the shunt nMOS transistor rises. The shunt nMOS transistor is then kept on.

When the shunt nMOS transistor is turned on, a drain current flows between the drain and source of the shunt nMOS transistor, and the electric charge generated by the surge in the first power supply wiring L VDD is discharged to the ground via the second power supply wiring LVSS.

The anode of the diode D is the source of the shunt nMOS transistor and the second power supply wiring LV.
It is connected to the SS. In the steady state in which the surge is not applied to the first power supply wiring L VDD, the shunt nMOS transistor is turned off because the trigger signal SC1 is at a low level. At this time, the gate of the shunt nMOS transistor is at the ground potential. Further, since the back gate of the shunt nMOS transistor is grounded, it always has a ground potential. That is, the potential in the well region always maintains the ground potential.

Even when the shunt nMOS transistor is off, a leakage current occurs between the drain and source. Here, by connecting the diode D to the source of the shunt nMOS transistor, the source potential becomes higher than the ground potential by the forward bias voltage of the diode D. As a result,
Since the gate-source voltage is even more negative than it would be without the diode D,
The leakage current of the shunt nMOS transistor is suppressed.

However, in the ESD protection circuit 2000 according to the comparative example, the gate-source voltage is the diode D even when the electric charge generated by the surge is discharged by passing the drain current.
It is reduced by the forward bias voltage of. Therefore, the driving force of the shunt nMOS transistor in the on state is reduced. As a result, even if the shunt nMOS transistor is turned on immediately after the surge is applied as shown in FIG. 4, it becomes difficult for a large amount of electric charge generated by the surge to be immediately released into the first power supply wiring L VDD, and the second 1 Power supply potential V of power supply wiring L VDD
_{The DD} rises sharply, causing an overshoot. As a result, when the drain current starts to flow, the potential _VDD of the first power supply wiring L _VDD greatly overshoots.

As described above, in the ESD protection circuit 2000 according to the comparative example, since the diode D is connected to the shunt nMOS transistor, it is possible to suppress the leakage current in the off state, while the ESD protection circuit 2000 During operation of, shunt nMO
Since the driving force of the S transistor Mn is reduced, the potential overshoot of the first power supply wiring L VDD when a surge is applied is extremely large. Due to this, the shunt nMOS transistor Mn is easily destroyed. That is, the shunt nMOS transistor may be destroyed due to the decrease in the discharge property of the ESD protection circuit 2000.

On the other hand, in the ESD protection circuit 100 according to the present embodiment, the back gate electrode V _B of the shunt nMOS transistor is connected to the connection point n2 between the capacitor C2 and the resistor R2. Therefore, the potential of the well region of the shunt nMOS transistor Mn is not fixed to the ground potential, but fluctuates with the potential of the connection point n2 between the capacitor C2 and the resistor R2.

When a surge is applied to the first power supply wiring L _VDD, the potential _VDD of the first power supply wiring L _VDD rapidly rises due to the amount of electric charge due to the surge. At this time, the resistor R2 is charged for a period of time corresponding to the time constant R2 × C2 of the capacitor C2 and the resistor R2 so that the capacitor C2 is charged.
Since the current flows through, the connection point n2 has a positive potential higher than the ground potential from the ground potential. Therefore, a positive potential is applied to the well region of the shunt nMOS transistor Mn. That is, the well region of the shunt nMOS transistor Mn is a p-type semiconductor.
Since the source is an n-type semiconductor, a forward voltage is applied to the pn junction between the well region of the shunt nMOS transistor Mn and the source.

FIG. 6 is a simple cross-sectional view for explaining the operation of the shunt nMOS transistor. V
_G is the gate voltage, _{V D} is the drain potential, _{V S} is the source potential, and _{V B} indicates the back gate potential. As described above, the back gate potential V _B of the ESD protection circuit 100 according to the present embodiment.
Rise from the ground potential to the positive potential immediately after the surge is applied.

The back gate effect of the nMOS transistor will be described with reference to FIG. 7. FIG. 7 shows nMO
The back gate-source voltage _VBS dependence of the relationship between the drain current of the S transistor and the gate potential (gate-source voltage) is shown. threshold V _th decreases as compared with the case back gate-source voltage V _BS is a positive voltage when the back gate-source voltage V _BS of the nMOS transistor is zero (back gate grounded), the drain current of the nMOS transistor It increases and the driving force increases. That is, when a forward voltage is applied to the pn junction between the well region and the source, the drain current of the nMOS transistor increases and the driving force of the nMOS transistor increases. On the other hand, the threshold value _{V th} is increased as compared with the case back gate-source voltage _{V BS} a negative voltage to become the back gate-source voltage _{V BS} of the nMOS transistor is zero (back gate grounded), the drain of the nMOS transistor The current decreases and the driving force decreases. That is, when a reverse voltage is applied to the pn junction between the well region and the source, nMO
The drain current of the S transistor decreases, and the driving force of the nMOS transistor decreases.

As shown in FIG. 5, the ESD protection circuit 100 according to the present embodiment, the driving force of the shunt nMOS transistor for a surge is applied, the back gate-source potential V _BS of the shunt nMOS transistor Mn becomes a positive potential Increases. As a result, as compared with the ESD protection circuit 2000 according to the comparative example, the surge charge is efficiently discharged by the shunt nMOS transistor immediately after the surge is applied. As a result, the ESD protection circuit 1 of the present embodiment
At 00, the overshoot of the potential _VDD of the first power supply wiring L VDD immediately after the surge is applied is suppressed as compared with the ESD protection circuit 2000 according to the comparative example. By improving the discharge property of the ESD protection circuit 100, it is possible to prevent the shunt nMOS transistor Mn from being destroyed.

Immediately after the surge is applied, the trigger signal SC1 is used for a time corresponding to the time constant R1 × C1 of the series circuit of the first resistor R1 and the first capacitor C1 in the trigger circuit RCT1 of the ESD protection circuit 100. The level becomes high, the gate potential of the shunt nMOS transistor Mn becomes a positive potential, and the shunt nMOS transistor keeps the on state. At the same time, since the connection point n2 of the resistor R2 and the capacitor C2 maintains a positive potential for a time corresponding to the time constant R2 × C2 of the series circuit of the resistor R2 and the capacitor C2 immediately after the surge is applied.
Back gate-to-source voltage V _BS is maintained at a positive voltage. That is, a forward voltage is maintained between the backgate and source.

(Embodiment 2)
Next, the ESD protection circuit 200 according to the second embodiment will be described with reference to FIG. The ESD protection circuit 200 according to the present embodiment differs from the ESD protection circuit 100 according to the first embodiment in the following points.

The ESD protection circuit 200 according to the present embodiment has a p-channel shunt pMOS transistor Mp instead of the n-channel shunt nMOS transistor Mn. Diode D
The anode is connected to the first power supply wiring L VDD and the cathode is connected to the second power supply wiring LVSS, and the source and drain of the shunt pMOS transistor Mp are the first.
It is the same as the first embodiment that the power supply wiring L VDD and the second power supply wiring LVSS are connected in series with the diode D. The source of the shunt pMOS transistor is diode D
The drain of the shunt pMOS transistor Mp is connected to the cathode of the second power supply wiring L.
The ESD protection circuit 200 according to the present embodiment is E according to the first embodiment in that it is connected to VSS.
It is different from the SD protection circuit. The well region of the shunt pMOS transistor Mp is an n-type semiconductor, and the source and drain are p-type semiconductors.

Further, the capacitor C2 is connected between the first power supply wiring L VDD and the second power supply wiring LVSS, and the resistor R2 is connected between the first power supply wiring L VDD and the second power supply wiring LVSS.
The ESD protection circuit 200 according to the present embodiment and the ESD protection circuit 100 according to the first embodiment are the same in that they are connected so as to be connected in series with 2. However, E according to this embodiment
The SD protection circuit 200 differs from the ESD protection circuit 100 according to the first embodiment in the following points. That is, one end of the resistor R2 is connected to the first power supply wiring L VDD, and the other end of the resistor R2 is connected to one end of the capacitor C2 at the connection point n2. The other end of the capacitor C2 is connected to the second power supply wiring LVSS. The connection point n2 is connected to the well region of the shunt pMOS transistor Mp via the back gate electrode. The potential of the connection point n2 is supplied to the well region.

FIG. 9 shows a specific example of the RC trigger circuit RCT2 in the ESD protection circuit 200 according to the present embodiment. As shown in FIG. 9, the RC trigger circuit RCT2 has a first resistor R1, a first capacitor C1, and a first inverter circuit INV1 in the same manner as the ESD protection circuit according to the first embodiment. The ESD protection circuit 200 according to the present embodiment and the ESD protection circuit according to the first embodiment are different from each other in the following points. One end of the first capacitor C1 is connected to the first power supply wiring L VDD, and the other end is connected to one end of the first resistor R1 at the connection point n1. The other end of the first resistor R1 is connected to the second power supply wiring LVSS. The first resistor R1 and the first capacitor C1 are connected in series between the first power supply wiring L VDD and the second power supply wiring LVSS.

The other end of the first capacitor C1 is connected to the input terminal of the first inverter circuit INV1.
The output terminal of the first inverter INV1 is connected to the gate of the shunt pMOS transistor. When a surge is applied to the first power supply terminal T VDD, the potential V _D of the first power supply wiring L VDD
_D rises, and in synchronization with this, a trigger signal SC2 that makes the shunt pMOS transistor conductive is output from the first inverter circuit INV1 of the RC trigger circuit RCT2 (details will be described later).

Next, the operation of the ESD protection circuit 200 according to the second embodiment will be described. When a surge caused by ESD is applied to the first power supply wiring L VDD in the semiconductor integrated circuit, the first power supply wiring L
The potential of VDD (drain potential) _VDD is increased by the electric charge generated in large quantities by the surge. In the RC trigger circuit RCT2, within the time corresponding to the time constant R1 × C1 of the resistance / capacitance product of the first resistor R1 and the first capacitor C1, the connection point n1 between the first resistor R1 and the first capacitor C1 potential, a ground potential V from the potential or ground potential _{V SS} of the second power line LVSS
_It will be higher than _SS . As a result, the trigger signal SC2 output from the first inverter circuit INV1 becomes low level. That is, a low-level signal is input to the gate of the shunt pMOS transistor Mp, and the shunt pMOS transistor is turned on. Before the surge is applied to the first power supply wiring L VDD, the first inverter circuit INV1 receives the ground potential and outputs a high level, and the gate voltage is higher than the threshold value, so that the shunt pMOS
The transistor Mp is in the off state.

When the shunt pMOS transistor Mp is turned on, a drain current flows between the drain and the source of the shunt pMOS transistor Mp, and the electric charge due to the surge in the first power supply wiring L VDD is discharged to the ground via the second power supply wiring LVSS. During the time corresponding to the time constant R1 × C1 of the series circuit of the first resistor R1 and the first capacitor C1, the shunt pMOS transistor is turned on and the electric charge generated by the surge is discharged to the ground.

Immediately after the surge is applied, the potential of the connection point n2 between the resistor R2 and the capacitor C2 is lower than the potential _{VDD of} the second power supply wiring L _VDD due to the current flowing through the resistor R2 for charging the capacitor C2. Become. Therefore, the well region of the shunt pMOS transistor is in a negatively biased state with respect to the source potential. That is, a forward voltage is applied to the pn junction between the well region and the source.

the back gate effect of the pMOS transistor becomes opposite characteristics to the nMOS transistor with respect to the voltage _{V BS} between the back gate and source. That is, the voltage between the back gate and the source V _{B
When S} becomes negative, a forward voltage is applied to the pn junction between the well region and the source, and the shunt pM
The driving force of the OS transistor increases. Therefore, the ESD protection circuit 20 according to the present embodiment
Even at 0, the overshoot of the potential _VDD of the first power supply wiring L VDD immediately after the surge is applied can be suppressed, as in the ESD protection circuit 100 according to the first embodiment. As a result, the discharge property of the ESD protection circuit 200 is improved, and the shunt pMOS in the ESD protection circuit 200 is improved.
It is possible to prevent the destruction of the transistor.

Similar to the first embodiment, in the present embodiment as well, the connection point n2 of the resistor R2 and the capacitor C2 is the first for a time corresponding to the time constant R2 × C2 of the series circuit of the resistor R2 and the capacitor C2 immediately after the surge is applied. 1 Maintain a potential lower than the potential of the power supply wiring L VDD. This will
Back gate-to-source voltage V _BS is maintained at a negative voltage. That is, since the well region of the shunt pMOS transistor is an n-type semiconductor and the source is a p-type semiconductor, the shunt pM
A forward voltage is applied to the pn junction between the well region of the OS transistor Mp and the source. During this time, the driving force of the shunt pMOS transistor Mp is increased, and the discharge property of the ESD protection circuit 200 is improved.

(Embodiment 3)
Next, the ESD protection circuit 300 according to the third embodiment will be described with reference to FIG. FIG. 10 shows
The configuration of the ESD protection circuit 300 of the third embodiment is shown. ESD protection circuit 30 according to the third embodiment
0 is the shunt nMOS transistor M as in the ESD protection circuit 100 according to the first embodiment.
It includes n, a diode D, a capacitor C2, a resistor R2, and an RC trigger circuit RCT1. In the ESD protection circuit 300 according to the present embodiment, the second inverter circuit INV2 is connected in series between the back gate of the shunt nMOS transistor Mn and the connection point n2 between the capacitor C2 and the resistor R2. Therefore, it differs from the ESD protection circuit 100 according to the embodiment.

Also in the ESD protection circuit 300 according to the present embodiment, similarly to the ESD protection circuit 100 according to the first embodiment, the potential of the connection point n2 between the capacitor C2 and the resistor R2 is supplied to the well region of the shunt nMOS transistor. Immediately after the surge is applied, the back gate-source voltage VBS of the shunt nMOS transistor Mn is set to a positive voltage for a time corresponding to the time constant R2 × C2 of the series circuit of the capacitor C2 and the resistor R2. As a result, a forward voltage is applied to the pn junction between the well region and the source, the driving force of the shunt nMOS transistor Mn is increased, the overshoot of the potential _VDD of the first power supply wiring L _VDD is suppressed, and the overshoot of the potential _VDD of the shunt nMOS transistor is suppressed. Prevent destruction.

Further, in the ESD protection circuit 300 according to the present embodiment, the second is between the back gate potential of the shunt nMOS transistor Mn and the connection point n2 between the capacitor C2 and the resistor R2.
By providing the inverter circuit INV2 to the two stages in series, when a surge is applied, further the effect can be maintained more stably the back gate-source voltage V _BS to the positive voltage. In the present embodiment, the second inverter circuit is described in two stages, but the second inverter circuit is not limited to two stages as long as it is an even number stage.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1,1000 semiconductor integrated circuits,
100, 200, 300, 2000 ESD protection circuit, 101 internal circuit,
C1, C2 Capacitor D Diode,
L VDD 1st power supply wiring,
LVSS 2nd power supply wiring,
Mn shunt nMOS transistor,
MP shunt pMOS transistor,
n1, n2 connection point,
R1, R2 resistors,
RCT1, RCT2 trigger circuit,
SC1, SC2 trigger signal,
T VDD 1st power supply terminal,
TVSS 2nd power supply terminal,
V _B backgate potential,
V _BS backgate source voltage V _D drain potential,
_VDD 1st power supply potential,
V _G gate potential,
_VGS gate-source voltage,
V _S source potential,
V _SS 2nd power supply potential,

Claims (6)

The first power supply wiring that supplies the first potential from the first power supply to one end of the internal circuit of the semiconductor integrated circuit,
An ESD protection circuit connected between a second power supply and a second power supply wiring that supplies a second potential lower than the first potential to the other end of the internal circuit.
A first capacitor whose one end is connected to the first power supply wiring,
A first resistor having one end connected to the other end of the first capacitor via a connection point and the other end connected to the second power supply wiring.
A diode whose cathode is connected to the second power supply wiring,
An n-channel MOS transistor in which the source is connected to the anode of the diode, the drain is connected to the first power supply wiring, and the well region where the source and drain are formed is connected to the connection point.
A second resistor whose one end is connected to the first power supply wiring,
A second capacitor with one end connected to the other end of the second resistor and the other end connected to the second power supply wiring.
An ESD protection circuit comprising a first inverter circuit in which an input terminal is connected to the other end of the second resistor and an output terminal is connected to the gate of the n-channel MOS transistor. The first power supply wiring that supplies the first potential from the first power supply to one end of the internal circuit of the semiconductor integrated circuit,
An ESD protection circuit connected between a second power supply and a second power supply wiring that supplies a second potential lower than the first potential to the other end of the internal circuit.
A first resistor whose one end is connected to the first power supply wiring,
A first capacitor having one end connected to the other end of the first resistor via a connection point and the other end connected to the second power supply wiring.
The anode is connected to the first power supply wiring, and the diode and
A p-channel MOS transistor in which the source is connected to the cathode of the diode, the drain is connected to the second power supply wiring, and the well region where the source and the drain are formed is connected to the connection point.
A second capacitor whose one end is connected to the first power supply wiring,
A second resistor having one end connected to the other end of the second capacitor and the other end connected to the second power supply wiring.
The input terminal is connected to the other end of the second capacitor, and the output terminal is the p-channel MO.
An ESD protection circuit including a first inverter circuit connected to the gate of an S transistor. The ESD according to claim 1 or 2, wherein the diode is a pn junction diode.
Protection circuit. The ESD protection circuit according to claim 1 or 2, wherein the diode is a parasitic diode of a MOS transistor. The ESD protection circuit according to claim 1 or 2, wherein the diode is a diode-connected bipolar transistor. The ESD protection circuit according to any one of claims 1 to 5, wherein an even number of second inverter circuits are further connected between the well region and the connection point.

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