JP2020053689A - ESD protection circuit - Google Patents

Abstract

To provide an ESD protection circuit capable of reducing power consumption while maintaining discharge performance.SOLUTION: In a semiconductor integrated circuit 1, an ESD protection circuit 100 is connected between a first power supply wiring LVDD and a second power supply wiring LVSS, and comprises an RC trigger circuit RCT1, a shunt nMOS transistor Mn, a diode D, a capacitor C2, and a resistor R2. In the diode D, an anode is connected to the first power supply wiring LVDD, and a cathode is connected to the second power supply wiring LVSS. A source and a drain of the shunt nMOS transistor Mn are connected in series to the diode D between the first power supply wiring LVDD and the second power supply wiring LVSS. In other words, the source of the shunt nMOS transistor is connected to the anode of the diode D, and the drain of the shunt nMOS transistor is connected to the first power supply wiring LVDD. The cathode of the diode D is connected to the second power supply wiring.SELECTED DRAWING: Figure 1

Description

Embodiments described herein relate generally to an ESD protection circuit that protects an internal circuit in a semiconductor integrated circuit from a surge caused by an ESD (Electrostatic Discharge).

An ESD protection circuit is used to protect an internal circuit in a semiconductor device from a surge generated by an ESD from a power supply terminal or the like. The ESD protection circuit detects a voltage increase in a power supply line due to a surge and detects a shunt MOS (Metal Oxid) connected between the power supply line and the ground line.
e Semiconductor) to make the transistor conductive, and discharge the charges due to the surge to the ground wiring. An RC trigger circuit that generates a trigger signal by using a series junction of a resistor (R) and a capacitor (C) is used as a means for detecting a voltage increase due to a surge to make a shunt MOS transistor conductive.

JP-A-2005-46507

It is desired that the shunt transistor for discharging the charge generated by the surge in the ESD protection circuit has a large driving force. However, the larger the driving force is, the larger the leakage current in the non-conductive state is, and the power consumption of the semiconductor device is increased. Will be higher. On the other hand, when the power consumption of the semiconductor device is reduced by suppressing the leakage current, the driving power of the shunt transistor is reduced, the discharge performance of the ESD protection circuit is reduced, and the shunt transistor may be destroyed. It is desired to reduce power consumption while maintaining the discharge performance of the ESD protection circuit.

The ESD protection circuit according to the embodiment is connected between a first power supply line and a second power supply line, and includes a first capacitor, a first resistor, a diode, a MOS transistor, a second resistor, and a second resistor.
A capacitor and a first inverter circuit; The first capacitor has one end connected to the first capacitor.
Connected to power supply wiring. The first resistor has one end connected to the other end of the first capacitor via a connection point, and the other end connected to the second power supply line. The diode has a cathode connected to the second power supply line. The MOS transistor has a source connected to the anode of the diode, a drain connected to the first power supply line, and a well region connected to the connection point. One end of the second resistor is connected to the first power supply line. One end of the second capacitor is connected to the other end of the second resistor. The first inverter circuit has an input terminal connected to the other end of the second resistor, and an output terminal connected to the gate of the MOS transistor.

FIG. 2 is a diagram showing a configuration of the ESD protection circuit according to the first embodiment. FIG. 2 is a diagram illustrating an example of a configuration of an RC trigger circuit according to the first embodiment. FIG. 9 is a diagram illustrating a configuration of an ESD protection circuit according to a comparative example. FIG. 9 is a diagram illustrating an operation of the ESD protection circuit according to the comparative example. FIG. 4 is a diagram illustrating an operation of the ESD protection circuit according to the first embodiment. FIG. 4 is a diagram illustrating a substrate bias effect. FIG. 4 is a diagram illustrating a substrate bias effect. FIG. 4 is a diagram showing a configuration of an ESD protection circuit according to a second embodiment. FIG. 9 is a diagram illustrating an example of a configuration of an RC trigger circuit according to the second embodiment. FIG. 9 is a diagram illustrating a configuration of an ESD protection circuit according to a third embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description of the embodiments are schematic for ease of description, and the shapes, dimensions, size relationships, etc. of the respective elements in the drawings are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range in which the effects of the present invention can be obtained. Elements having similar properties, functions, or characteristics are denoted by the same reference numerals or the same reference symbols, and description thereof is omitted.

(Embodiment 1)
Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a diagram illustrating a configuration of an ESD protection circuit in a semiconductor integrated circuit according to a first embodiment of the present invention. FIG.
5 is an example of a configuration example of a C trigger circuit.

As shown in FIG. 1, the semiconductor integrated circuit 1 has a first power supply terminal TVDD connected to a first power supply (not shown) that supplies a first potential _VDD , and a potential lower than the first potential V _DD. a second power supply terminal TVSS connected to the second power source (not shown) for supplying a second electric potential _{V SS.} Here, the first embodiment is described with the second power supply being ground and the second potential _VSS being ground potential. The first power supply is simply a power supply, and the first potential V _DD is a power supply potential.
Will be described.

The semiconductor integrated circuit 1 includes a first power supply line LVDD, a second power supply line LVSS, an ESD protection circuit 100, and an internal circuit 101. The internal circuit 101 is a core part including a CPU (Central Processing Unit) constituting the semiconductor integrated circuit 1 and a memory.

The first power supply line LVDD electrically connects the first power supply terminal TVDD to one end of the internal circuit, and supplies the power supply potential _VDD supplied to the first power supply terminal TVDD to one end of the internal circuit 101. The second power supply line LVSS electrically connects the second power supply terminal TVSS to the other end of the internal circuit 101, and supplies the ground potential supplied to the second power supply terminal TVSS to the other end of the internal circuit 101.

The ESD protection circuit 100 is connected between the first power supply line LVDD and the second power supply line LVSS. When a surge due to ESD enters the semiconductor integrated circuit 1 from the first power supply terminal TVDD, the ESD protection circuit 100 operates and discharges the charge generated by the surge due to ESD to the second power supply line LVSS, thereby generating the surge. The large amount of electric charges
To prevent the internal circuit 101 from being destroyed.

The ESD protection circuit 100 includes an RC trigger circuit RCT1, a shunt nMOS transistor (n-channel MOS transistor) Mn, a diode D, a capacitor C2, and a resistor R
2 The diode D has an anode connected to the first power supply line (LVDD) and a cathode connected to the second power supply line LVSS. The source and the drain of the shunt nMOS transistor Mn are connected in series with the diode D between the first power supply wiring LVDD and the second power supply wiring LVSS. That is, the source of the shunt nMOS transistor is connected to the anode of the diode D, and the drain of the shunt nMOS transistor is connected to the first power supply line LVDD.
Connected to. The cathode of the diode D is connected to the second power supply wiring.

Here, the diode D is, for example, a pn junction type diode in which an n-type semiconductor and a p-type semiconductor are joined. In the present embodiment, the case where the number of pn junctions is one is described, but it is also possible to use multi-stage pn junctions. The diode D is not limited to a pn junction type diode, but may be a parasitic diode of a MOS transistor, a diode-connected bipolar transistor, or the like.

For example, in the case of an nMOS transistor, the parasitic diode of the MOS transistor has a gate, a drain, and a back gate connected to function as an anode, and the source functions as a cathode. In the case of a pMOS transistor (p-channel transistor), the gate, the drain, and the back gate are connected and function as a cathode, and the source functions as an anode.

In the case of an npn transistor, a diode-connected bipolar transistor has a base functioning as an anode, and an emitter and a collector connected to function as a cathode. In the case of a pnp transistor, the base functions as a cathode, and the emitter and the collector are connected to function as an anode.

The source and drain of the shunt nMOS transistor are an n-type semiconductor and are formed in a well region of a p-type semiconductor. The gate electrode has a source, a well region,
And on the drain. The back gate electrode (not shown) is provided so as to be electrically connected to the well region, and the potential of the well region is adjusted via the back gate electrode.

The capacitor C2 is connected between the first power supply line LVDD and the second power supply line LVSS.
The resistor R2 is connected between the first power supply line LVDD and the second power supply line LVSS so as to be connected in series with the capacitor C2. That is, one end of the capacitor C2 is connected to the first power supply line LVD.
D, and the other end of the capacitor C2 is connected to one end of the resistor R2 at a connection point n2. The other end of the resistor R2 is connected to the second power supply line LVSS. The connection point n2 is a shunt nMO
It is connected to the well region of the S transistor via a back gate electrode. The potential at the connection point n2 is supplied to the well region.

As shown in FIG. 2, the RC trigger circuit RCT1 has a first resistor R1, a first capacitor C1, and a first inverter circuit INV1. One end of the first resistor has a first power supply line LV.
DD, and the other end is connected to one end of the first capacitor C1 at a connection point n1. The other end of the first capacitor C1 is connected to the second power line LVSS. The first resistor R1 and the first capacitor C1 are connected in series between the first power supply wiring LVDD and the second power supply wiring LVSS.

The other end of the first resistor R1 is connected to an input terminal of the first inverter circuit INV1. First
The output terminal of the inverter INV1 is connected to the gate of the shunt nMOS transistor. When a surge is applied to the first power supply terminal TVDD, the potential _VDD of the first power supply line LVDD rises, and in synchronization with this, the shunt n from the first inverter circuit INV1 of the RC trigger circuit.
A trigger signal SC1 for turning on the MOS transistor is output (details will be described later).

Next, the operation of the ESD protection circuit according to the present embodiment will be described in comparison with a comparative example. FIG.
Next, an ESD protection circuit 2000 according to a comparative example will be described. Also in the comparative example, the ESD protection circuit 2000 includes the first power supply line LV in the semiconductor integrated circuit 1000 as in the present embodiment.
DD and the second power supply line LVSS. The internal circuit 101 includes a first power supply line L
It is connected between VDD and the second power supply wiring LVSS. When a surge due to ESD enters the semiconductor integrated circuit 1000 from the first power supply terminal TVDD, the ESD protection circuit 2000 is activated, and charges generated by the surge are transferred from the first power supply wiring to the second power supply wiring via the ESD protection circuit 2000. Released. This prevents the charge generated by the surge from entering the internal circuit 101.

The protection circuit 2000 according to the comparative example includes an RC trigger circuit RCT1, a shunt nMOS transistor Mn, and a diode D, similarly to the ESD protection circuit 100 according to the present embodiment. The ESD protection circuit 2000 according to the comparative example and the ESD protection circuit 100 according to the present embodiment include:
They differ in the following points. The back gate of the shunt nMOS transistor of the ESD protection circuit 2000 according to the comparative example is connected to the second power supply line. That is, the potential of the well region of the shunt nMOS transistor Mn is fixed to the ground potential.

The operation of the ESD protection circuit 2000 according to the comparative example will be described with reference to FIG. FIG. 4 shows the gate potential of the shunt nMOS transistor, the drain current of the shunt nMOS transistor, and the drain potential of the shunt nMOS transistor when the surge due to the ESD enters the semiconductor integrated circuit 1000 from the first power supply terminal. Power supply potential _VDD applied to the power supply wiring), the source potential of the shunt nMOS transistor, and the shunt nM
5 shows a change over time in a back gate potential of an OS transistor. The vertical axis on the left side shows the potential normalized on the basis of the maximum value of the drain potential of the ESD protection circuit according to the comparative example. The vertical axis on the right is
7 shows a current normalized based on the maximum value of the drain current of the ESD protection circuit 2000 according to the comparative example. The horizontal axis indicates a time change.

When a surge caused by ESD is applied to the first power supply wiring LVDD in the semiconductor integrated circuit,
The potential (drain potential) _{VDD of} the first power supply wiring LVDD increases due to the amount of charge generated by the surge. In the RC trigger circuit RCT1, the first resistor R1 and the first capacitor C1 are set within a time constant R1 × C1 of the resistance-capacity product of the first resistor R1 and the first capacitor C1.
Is at a lower level than the potential of the first power supply line LVDD.

Since the power supply of the first inverter circuit INV1 is supplied with the same power supply potential _VDD as the first power supply line LVDD, the potential of the input of the first inverter circuit INV1 is within the time corresponding to the time constant of the RC trigger circuit. It becomes lower than the source potential of the p-channel MOS transistor in the first inverter circuit. As a result, the p-channel MOS transistor is turned on (conducting), the first inverter circuit INV1 outputs a high level, and this output is output to the RC trigger circuit R
The trigger signal SC1 is output from CT1.

Before the surge is applied, the potential of the connection point n1 between the first resistor R1 and the first capacitor C1 is the same as the potential of the first power supply line LVDD. In this case, the first inverter circuit INV
The first p-channel MOS transistor is turned off (disconnected), and the first inverter circuit INV
1 outputs a low level as the trigger signal SC1.

This trigger signal SC1 is supplied to the gate of the shunt nMOS transistor Mn. As shown in FIG. 4, since the trigger signal goes high only within a time period corresponding to the time constant of the RC trigger circuit RCT1 after the surge is applied to the first power supply line LVDD, the gate potential of the shunt nMOS transistor rises. As a result, the shunt nMOS transistor maintains the ON state.

When the shunt nMOS transistor is turned on, a drain current flows between the drain and the source of the shunt nMOS transistor, and discharges a charge generated by a surge in the first power supply line LVDD to the ground via the second power supply line LVSS.

The anode of the diode D is connected to the source of the shunt nMOS transistor and the second power supply line LV.
Connected to SS. In a steady state in which no surge is applied to the first power supply line LVDD, the shunt nMOS transistor is turned off because the trigger signal SC1 is at a low level. At this time, the gate of the shunt nMOS transistor is at the ground potential. In addition, the back gate of the shunt nMOS transistor is always grounded because it is grounded. That is, the potential of the well region always maintains the ground potential.

Even when the shunt nMOS transistor is off, a leak current occurs between the drain and the source. Here, since the diode D is connected to the source of the shunt nMOS transistor, the source potential becomes higher than the ground potential by the forward bias voltage of the diode D. As a result,
The voltage between the gate and the source is more negative than when there is no diode D.
The leakage current of the shunt nMOS transistor is suppressed.

However, in the ESD protection circuit 2000 according to the comparative example, even when the charge generated by the surge is released by flowing the drain current, the voltage between the gate and the source is reduced by the diode D.
In the forward bias voltage. For this reason, the driving force in the ON state of the shunt nMOS transistor decreases. As a result, even if the shunt nMOS transistor is turned on immediately after the application of the surge as shown in FIG. 4, a large amount of electric charges generated by the surge in the first power supply wiring LVDD is less likely to be immediately released, and Power supply potential V of one power supply line LVDD
_DD rises rapidly causing overshoot. As a result, when the drain current starts to flow, the potential _VDD of the first power supply wiring LVDD greatly overshoots.

As described above, in the ESD protection circuit 2000 according to the comparative example, since the diode D is connected to the shunt nMOS transistor, it is possible to suppress the off-state leakage current. During operation, the shunt nMO
In order to reduce the driving force of the S transistor Mn, the overshoot of the potential of the first power supply line LVDD when a surge is applied is extremely large. Due to this, the shunt nMOS transistor Mn is easily broken. That is, there is a possibility that the shunt nMOS transistor may be destroyed due to a decrease in the discharge performance of the ESD protection circuit 2000.

In contrast, in the ESD protection circuit 100 according to the present embodiment, the back gate electrode _{V B} of the shunt nMOS transistor is connected to a connection point n2 of the capacitor C2 and the resistor R2. Therefore, the potential of the well region of the shunt nMOS transistor Mn is not fixed to the ground potential, but varies with the potential of the connection point n2 between the capacitor C2 and the resistor R2.

When a surge is applied to the first power supply line LVDD, the potential _VDD of the first power supply line LVDD sharply increases due to the amount of charge due to the surge. At this time, the resistor R2 is charged for a time corresponding to a time constant R2 × C2 by the capacitor C2 and the resistor R2 so that the capacitor C2 is charged.
, The connection point n2 has a positive potential higher than the ground potential from the ground potential. Therefore, a positive potential is applied to the well region of the shunt nMOS transistor Mn. That is, the well region of the shunt nMOS transistor Mn is a p-type semiconductor,
Since the source is an n-type semiconductor, a forward voltage is applied to the pn junction between the well region of the shunt nMOS transistor Mn and the source.

FIG. 6 is a simple cross-sectional view for explaining the operation of the shunt nMOS transistor. V
_G is the gate voltage, _{V D} is the drain potential, _{V S} is the source potential, and _{V B} indicates the back gate potential. As described above, the back gate potential V _B of the ESD protection circuit 100 according to the present embodiment.
Rises from the ground potential to the positive potential immediately after the application of the surge.

The back gate effect of the nMOS transistor will be described with reference to FIG. FIG.
The relationship between the S transistor drain current and the gate potential of (the gate-source voltage), indicating between the back gate and source voltage V _BS dependence. When the back gate-source voltage V _{BS of the} nMOS transistor becomes a positive voltage, the threshold value V _th decreases as compared with the case where the back gate-source voltage V _BS is zero (the back gate is grounded), and the drain current of the nMOS transistor becomes lower. The driving force increases. That is, when a forward voltage is applied to the pn junction between the well region and the source, the drain current of the nMOS transistor increases, and the driving force of the nMOS transistor increases. On the other hand, when the back gate-source voltage V _{BS of} the nMOS transistor becomes a negative voltage, the threshold V _th increases as compared with the case where the back gate-source voltage V _BS is zero (the back gate is grounded), and the drain of the nMOS transistor is drained. The current decreases and the driving force decreases. That is, when a reverse voltage is applied to the pn junction between the well region and the source, nMO
The drain current of the S transistor decreases, and the driving force of the nMOS transistor decreases.

As shown in FIG. 5, in the ESD protection circuit 100 according to the present embodiment, when a surge is applied, the back gate-source potential V _{BS of the} shunt nMOS transistor Mn becomes positive, so that the driving force of the shunt nMOS transistor is increased. Increase. As a result, compared with the ESD protection circuit 2000 according to the comparative example, the discharge of the surge charge by the shunt nMOS transistor is performed more efficiently immediately after the application of the surge. As a result, the ESD protection circuit 1 of the present embodiment
In 00, the overshoot of the potential _VDD of the first power supply line LVDD immediately after the application of the surge is suppressed more than in the ESD protection circuit 2000 according to the comparative example. By improving the discharge performance of the ESD protection circuit 100, it is possible to prevent the shunt nMOS transistor Mn from being destroyed.

Immediately after the surge is applied, the trigger signal SC1 is maintained for a time corresponding to the time constant R1 × C1 of the series circuit of the first resistor R1 and the first capacitor C1 in the trigger circuit RCT1 of the ESD protection circuit 100. High level, the gate potential of the shunt nMOS transistor Mn becomes positive potential, and the shunt nMOS transistor maintains the ON state. At the same time, the connection point n2 of the resistor R2 and the capacitor C2 maintains a positive potential for a time corresponding to the time constant R2 × C2 of the series circuit of the resistor R2 and the capacitor C2 immediately after the application of the surge.
The back gate-source voltage V _BS maintains a positive voltage. That is, a forward voltage is maintained between the back gate and the source.

(Embodiment 2)
Next, an ESD protection circuit 200 according to the second embodiment will be described with reference to FIG. The ESD protection circuit 200 according to the present embodiment is different from the ESD protection circuit 100 according to the first embodiment in the following points.

The ESD protection circuit 200 according to the present embodiment includes a p-channel shunt pMOS transistor Mp instead of the n-channel shunt nMOS transistor Mn. Diode D
Has an anode connected to the first power supply line LVDD, a cathode connected to the second power supply line LVSS, and a source and a drain of the shunt pMOS transistor Mp
The connection between the power supply line LVDD and the second power supply line LVSS in series with the diode D is the same as in the first embodiment. The source of the shunt pMOS transistor is diode D
And the drain of the shunt pMOS transistor Mp is connected to the second power supply line L
The ESD protection circuit 200 according to the present embodiment differs from the ESD protection circuit 200 according to the first embodiment in that it is connected to VSS.
Different from SD protection circuit. The well region of the shunt pMOS transistor Mp is an n-type semiconductor, and the source and drain are p-type semiconductors.

Further, the capacitor C2 is connected between the first power line LVDD and the second power line LVSS, and the resistor R2 is connected between the first power line LVDD and the second power line LVSS.
2 is the same as the ESD protection circuit 200 according to the present embodiment and the ESD protection circuit 100 according to the first embodiment. However, according to the present embodiment,
The SD protection circuit 200 differs from the ESD protection circuit 100 according to the first embodiment in the following points. That is, one end of the resistor R2 is connected to the first power supply line LVDD, and the other end of the resistor R2 is connected to one end of the capacitor C2 at the connection point n2. The other end of the capacitor C2 is connected to the second power line LVSS. The connection point n2 is connected to the well region of the shunt pMOS transistor Mp via a back gate electrode. The potential at the connection point n2 is supplied to the well region.

FIG. 9 shows a specific example of the RC trigger circuit RCT2 in the ESD protection circuit 200 according to the present embodiment. As shown in FIG. 9, the RC trigger circuit RCT2 has a first resistor R1, a first capacitor C1, and a first inverter circuit INV1, similarly to the ESD protection circuit according to the first embodiment. The ESD protection circuit 200 according to the present embodiment is different from the ESD protection circuit according to the first embodiment in the following points. One end of the first capacitor C1 is connected to the first power supply line LVDD, and the other end is connected to one end of the first resistor R1 at a connection point n1. The other end of the first resistor R1 is connected to the second power supply line LVSS. The first resistor R1 and the first capacitor C1 are connected in series between the first power supply wiring LVDD and the second power supply wiring LVSS.

The other end of the first capacitor C1 is connected to an input terminal of the first inverter circuit INV1.
The output terminal of the first inverter INV1 is connected to the gate of the shunt pMOS transistor. When a surge is applied to the first power supply terminal TVDD, the potential V _D of the first power supply wiring LVDD is applied.
_D rises, and in synchronization with this, a trigger signal SC2 for turning on the shunt pMOS transistor is output from the first inverter circuit INV1 of the RC trigger circuit RCT2 (details will be described later).

Next, the operation of the ESD protection circuit 200 according to the second embodiment will be described. When a surge caused by ESD is applied to the first power supply line LVDD in the semiconductor integrated circuit, the first power supply line LVDD
VDD potential (drain potential) V _DD is increased by the electric charge generated in large quantities by the surge. In the RC trigger circuit RCT2, the connection point n1 between the first resistor R1 and the first capacitor C1 is within a time corresponding to the time constant R1 × C1 of the resistance-capacity product of the first resistor R1 and the first capacitor C1. potential, a ground potential V from the potential or ground potential _{V SS} of the second power line LVSS
Higher than _SS . As a result, the trigger signal SC2 output from the first inverter circuit INV1 becomes low level. That is, a low-level signal is input to the gate of the shunt pMOS transistor Mp, and the shunt pMOS transistor is turned on. Before the surge is applied to the first power supply line LVDD, the first inverter circuit INV1 outputs a high level by inputting the ground potential and the gate voltage is higher than the threshold value.
The transistor Mp is off.

When the shunt pMOS transistor Mp is turned on, a drain current flows between the drain and the source of the shunt pMOS transistor Mp, and discharges a charge due to a surge in the first power supply line LVDD to the ground via the second power supply line LVSS. During a time corresponding to the time constant R1 × C1 of the series circuit of the first resistor R1 and the first capacitor C1, the shunt pMOS transistor is turned on, and charges generated by the surge are discharged to the ground.

Immediately after the surge is applied, the potential at the connection point n2 between the resistor R2 and the capacitor C2 becomes lower than the potential _{VDD of} the second power supply line LVDD due to the current for charging the capacitor C2 flowing through the resistor R2. Become. Therefore, the well region of the shunt pMOS transistor is in a state of being negatively biased with respect to the source potential. That is, a forward voltage is applied to the pn junction between the well region and the source.

the back gate effect of the pMOS transistor becomes opposite characteristics to the nMOS transistor with respect to the voltage _{V BS} between the back gate and source. That is, the back gate-source voltage V _{B
When S} becomes negative, a forward voltage is applied to the pn junction between the well region and the source, and the shunt pM
The driving force of the OS transistor increases. Therefore, the ESD protection circuit 20 according to the present embodiment
Even at 0, as in the ESD protection circuit 100 according to the first embodiment, it is possible to suppress the overshoot of the potential _VDD of the first power supply line LVDD immediately after the application of the surge. As a result, the discharge performance of the ESD protection circuit 200 is improved, and the shunt pMOS in the ESD protection circuit 200 is improved.
Destruction of the transistor can be prevented.

Similarly to the first embodiment, in the present embodiment, the connection point n2 between the resistor R2 and the capacitor C2 is set to the second point during a time corresponding to the time constant R2 × C2 of the series circuit of the resistor R2 and the capacitor C2 immediately after the application of the surge. A potential lower than the potential of one power supply line LVDD is maintained. This allows
The back gate-source voltage V _BS maintains a negative voltage. That is, the well region of the shunt pMOS transistor is an n-type semiconductor and the source is a p-type semiconductor.
A forward voltage is applied to the pn junction between the well region and the source of the OS transistor Mp. During this time, the driving force of the shunt pMOS transistor Mp increases, and the discharge performance of the ESD protection circuit 200 improves.

(Embodiment 3)
Next, an ESD protection circuit 300 according to the third embodiment will be described with reference to FIG. FIG.
9 shows a configuration of an ESD protection circuit 300 according to a third embodiment. ESD protection circuit 30 according to the third embodiment
0 is the shunt nMOS transistor M as in the ESD protection circuit 100 according to the first embodiment.
n, a diode D, a capacitor C2, a resistor R2, and an RC trigger circuit RCT1. The ESD protection circuit 300 according to the present embodiment is configured such that the second inverter circuit INV2 is connected in series between two stages between the back gate of the shunt nMOS transistor Mn and the connection point n2 between the capacitor C2 and the resistor R2. This is different from the ESD protection circuit 100 according to the embodiment.

In the ESD protection circuit 300 according to the present embodiment, similarly to the ESD protection circuit 100 according to the first embodiment, by supplying the potential of the connection point n2 between the capacitor C2 and the resistor R2 to the well region of the shunt nMOS transistor. The voltage VBS between the back gate and the source of the shunt nMOS transistor Mn is set to a positive voltage for a time corresponding to the time constant R2 × C2 of the series circuit of the capacitor C2 and the resistor R2 immediately after the application of the surge. As a result, a forward voltage is applied to the pn junction between the well region and the source, the driving force of the shunt nMOS transistor Mn is increased, the overshoot of the potential _VDD of the first power supply line LVDD is suppressed, and the shunt nMOS transistor Prevent destruction.

Furthermore, in the ESD protection circuit 300 according to the present embodiment, the second between the back gate potential of the shunt nMOS transistor Mn and the connection point n2 between the capacitor C2 and the resistor R2.
By providing the inverter circuit INV2 in two stages in series, there is an effect that the back gate-source voltage V _BS can be more stably maintained at a positive voltage when a surge is applied. In the present embodiment, the second inverter circuit is described in two stages, but is not limited to two stages as long as it is an even number stage.

Although several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

1, 1000 semiconductor integrated circuits,
100, 200, 300, 2000 ESD protection circuit, 101 internal circuit,
C1, C2 capacitor D diode,
LVDD first power supply wiring,
LVSS second power supply wiring,
Mn shunt nMOS transistor,
MP shunt pMOS transistor,
n1, n2 connection points,
R1, R2 resistor,
RCT1, RCT2 trigger circuit,
SC1, SC2 trigger signal,
TVD first power supply terminal,
TVSS second power supply terminal,
V _B back gate potential,
_VBS back gate / source voltage V _D drain potential,
V _DD first power supply potential,
V _G gate potential,
V _GS gate-source voltage,
V _S source potential,
_VSS second power supply potential,

Claims (6)

A first power supply line for supplying a first potential from a first power supply to one end of an internal circuit of the semiconductor integrated circuit;
An ESD protection circuit connected between a second power supply and a second power supply line that supplies a second potential lower than the first potential to the other end of the internal circuit from a second power supply,
A first capacitor having one end connected to the first power supply wiring;
A first resistor having one end connected to the other end of the first capacitor via a connection point and the other end connected to the second power supply wiring;
A diode having a cathode connected to the second power supply line;
An n-channel MOS transistor having a source connected to the anode of the diode, a drain connected to the first power supply line, and a well region where the source and the drain are formed connected to the connection point;
A second resistor having one end connected to the first power supply wiring;
A second capacitor having one end connected to the other end of the second resistor and the other end connected to the second power supply wiring;
A first inverter circuit having an input terminal connected to the other end of the second resistor and an output terminal connected to the gate of the n-channel MOS transistor. A first power supply line for supplying a first potential from a first power supply to one end of an internal circuit of the semiconductor integrated circuit;
An ESD protection circuit connected between a second power supply and a second power supply line that supplies a second potential lower than the first potential to the other end of the internal circuit from a second power supply,
A first resistor having one end connected to the first power supply wiring;
A first capacitor having one end connected to the other end of the first resistor via a connection point and the other end connected to the second power supply wiring;
An anode connected to the first power supply line, and a diode;
A p-channel MOS transistor having a source connected to the cathode of the diode, a drain connected to the second power supply line, and a well region where the source and the drain are formed, connected to the connection point;
A second capacitor having one end connected to the first power supply wiring;
A second resistor having one end connected to the other end of the second capacitor and the other end connected to the second power supply wiring;
An input terminal is connected to the other end of the second capacitor, and an output terminal is connected to the p-channel MO.
And a first inverter circuit connected to the gate of the S transistor. The ESD according to claim 1, wherein the diode is a pn junction diode.
Protection circuit. The ESD protection circuit according to claim 1, wherein the diode is a parasitic diode of a MOS transistor. The ESD protection circuit according to claim 1, wherein the diode is a diode-connected bipolar transistor. The ESD protection circuit according to claim 1, wherein an even number of second inverter circuits are further connected between the well region and the connection point.

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