JP2014131062A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrostatic protective circuit capable of operating at a low voltage even if a part of a discharge current flows into a power supply line from a signal line.SOLUTION: A semiconductor device includes a power-supply line 4, a ground line 6, a signal line 5 for transmitting a signal, a signal pad 2 connected to the signal line 5, a thyristor 7 provided between the signal line 5 and the ground line 6, and a trigger circuit 8 for passing a trigger current Ito the thyristor 7. The trigger circuit 8 includes a PMOS transistor P1 having a gate and a back gate connected to the power-supply line 4 and having a source connected to the thyristor 7, and an NMOS transistor N1 generating a current in which a current I1 is amplified in response to the current I1 flowing through the PMOS transistor P1. A current flowing through the NMOS transistor N1 is passed to the thyristor 7 as the trigger current I.

Description

  The present invention relates to a semiconductor device, and more particularly to an electrostatic protection circuit for a semiconductor device.

  In a semiconductor device, an electrostatic protection circuit is mounted to protect an internal circuit against an ESD (electrostatic discharge) surge applied to an input / output pad. One known circuit topology for electrostatic protection circuits is a circuit topology that uses active elements such as thyristors and bipolar transistors. An electrostatic protection circuit using an active element has an advantage of high discharge capability because it performs an active operation when a surge is input, and is widely used (for example, see Non-Patent Documents 1 and 2).

  An electrostatic protection circuit using an active element is desired to have a low leakage current during normal operation and a low trigger voltage when an ESD surge is applied. Non-Patent Document 3 and Patent Document 1 disclose configurations of an electrostatic protection circuit for satisfying such a requirement.

  FIG. 1 is a circuit diagram showing a configuration of an electrostatic protection circuit disclosed in Non-Patent Document 3 (Note that Patent Document 1 also discloses an electrostatic protection circuit having the same configuration). 1 includes a VDD pad 101, a signal pad 102, a VSS pad 103, a power supply line 104, a signal line 105, a ground line 106, a thyristor 107, and an ESD protection diode D1. And a PMOS transistor P1.

  In the electrostatic protection circuit of FIG. 1, the PMOS transistor P <b> 1 functions as a trigger element that supplies a trigger current to the thyristor 107. The electrostatic protection circuit of FIG. 1 supports various modes of ESD surge that can be applied to the VDD pad 101, the signal pad 102, and the VSS pad 103. However, in the following, only the operation in the case where an ESD surge is applied between the signal pad 102 and the VSS pad 103 related to the subject of the present invention so that the potential of the signal pad 102 is positive with respect to the potential of the VSS pad 103 will be described. explain.

  When an ESD surge is applied between the signal pad 102 and the VSS pad 103 such that the potential of the signal pad 102 is positive with respect to the potential of the VSS pad 103, the power supply line 104 becomes floating. Since the power supply capacitor Cx provided parasitically or intentionally exists between the power supply line 104 and the ground line 106, the power supply line 104 is connected to the ground line 106 until the power supply capacitor Cx is charged. And are fixed at substantially the same potential. When a positive ESD surge is applied to the signal pad 102 and the potential of the signal line 105 having the same potential increases, the source potential of the PMOS transistor P1 is the gate potential (the same potential as the power supply line 104 and almost the same as the ground line 106). The voltage between the gate and source of the PMOS transistor P1 exceeds the threshold voltage. When the gate-source voltage of the PMOS transistor P1 exceeds the threshold voltage, the PMOS transistor P1 operates to supply a trigger current to the thyristor 107, whereby the thyristor 107 operates to discharge the ESD surge.

JP 2008-218886 A

"A Low-Voltage Triggering SCR for On-chip ESD Protection at Output and Input Pads", IEEE Electron Device Letters, vol. 12, No. 1, January 1991 "GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes", EOS / ESD Symposium 2001, p.22 "A Low-Leakage SCR Design Using Trigger-PMOS Modulations for ESD Protection", EOS / ESD Symposium 07-376.

  One problem with the configuration of the electrostatic protection circuit of FIG. 1 is that the PMOS transistor P1 is less likely to operate at a low voltage depending on the configuration of the internal circuit to be protected and other attached circuits / attached elements. For example, as shown in FIG. 2A, consider a case where an output circuit is used as an internal circuit connected to the signal line 105 and a PMOS transistor P11 is used as a pull-up transistor of the output circuit. In this case, when an ESD surge such that the potential of the signal pad 102 is positive is applied, a P-type diffusion layer at the drain of the PMOS transistor P11 and an N well at the back gate form between the signal line 105 and the power supply line 104. The parasitic diode D11 is biased in the forward direction (see FIG. 2B). For this reason, a charging path passing through the parasitic diode D11 is formed, and the power supply line 104 is quickly charged. When the power supply line 104 is charged, the potential of the power supply line 104 increases following the potential of the signal line 105, and the gate-source voltage of the PMOS transistor P1 does not increase. As a result, in the circuit configuration of FIG. 2A, the voltage between the signal line 105 and the power supply line 104 is reduced to the forward bias voltage Vf_D11 of the parasitic diode D11, that is, a voltage of about 0.6V to 1.1V. End up.

On the other hand, in order for the PMOS transistor P1 to operate, the source-gate voltage of the PMOS transistor P1 must exceed the threshold voltage Vt_P1. The source-gate voltage Vgs of the PMOS transistor P1 is obtained by using the base-emitter voltage Vbe of the PNP transistor Q1 built in the thyristor 107:
Vgs = Vf_D11−Vbe, (1)
Therefore, in order to operate the PMOS transistor P1, the following conditions must be satisfied:
Vf_D11-Vbe> Vt_P1. ... (2)
Here, since Vf_D11 and Vbe are both forward bias voltages of the PN junction, both are about 0.6V. That is, depending on the operating conditions, the condition of equation (2) may not be satisfied, and a situation may occur in which the thyristor 107 does not perform a discharging operation. Even if a large current flows through the parasitic diode D11 and the condition of the expression (2) is satisfied, the difference between the source-gate voltage Vgs of the PMOS transistor P1 and the threshold voltage Vt_P1 becomes small, that is, the current flowing through the PMOS transistor P1, that is, The trigger current may be small. If the trigger current supplied to the thyristor 107 becomes small, the thyristor 107 may be destroyed without being operated, or the internal circuit 108 may be destroyed by being applied with voltage stress.

  The same applies to the case where an electrostatic protection diode D12 is provided between the signal line 105 and the power supply line 104 as shown in FIG. Also in this case, when an ESD surge in which the potential of the signal pad 102 is positive is applied, the electrostatic protection diode D12 is forward-biased. For this reason, a charging path passing through the electrostatic protection diode D12 is formed, and the power supply line 104 is quickly charged. When the power supply line 104 is charged, the potential of the power supply line 104 increases following the potential of the signal line 105, and the gate-source voltage of the PMOS transistor P1 does not increase. This is not preferable because the PMOS transistor P1 does not operate or the trigger current decreases.

  In one embodiment of the present invention, a semiconductor device includes a power line, a ground line, a signal line for transmitting a signal, a signal pad connected to the signal line, and the signal line and the ground line. A protection element provided; and a trigger circuit for causing a trigger current to flow through the protection element. The trigger circuit includes a PMOS transistor having a gate and a back gate connected to the power supply line, a source connected to the protection element, and the first current amplified in response to the first current flowing through the PMOS transistor. And an amplifier circuit unit for generating a second current. The trigger current includes the second current.

  According to the present invention, an electrostatic protection circuit that can operate at a low voltage even when a part of a discharge current flows from a signal line to a power supply line is provided.

It is a circuit diagram which shows the structure of the conventional electrostatic protection circuit. It is a circuit diagram for demonstrating the problem of the conventional electrostatic protection circuit. It is sectional drawing which shows the structure of the PMOS transistor in the conventional electrostatic protection circuit. It is a circuit diagram for demonstrating the problem of the conventional electrostatic protection circuit. 1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the semiconductor device in the 2nd Embodiment of this invention. It is a graph which shows the waveform of the trigger current in the conventional electrostatic protection circuit and the electrostatic protection circuit of 1st and 2nd embodiment. It is a graph which shows the waveform of each electric current which flows into the electrostatic protection circuit of 2nd Embodiment. It is a circuit diagram which shows the modification of the structure of the semiconductor device in 1st Embodiment. It is a circuit diagram which shows the modification of the structure of the semiconductor device in 2nd Embodiment.

(First embodiment)
FIG. 4 is a circuit diagram showing a configuration of the semiconductor device according to the first embodiment of the present invention, particularly, a configuration of an electrostatic protection circuit integrated in the semiconductor device. In the present embodiment, the semiconductor device includes a VDD pad 1, a signal pad 2, a VSS pad 3, a power supply line 4, a signal line 5, a ground line 6, a thyristor 7, and a trigger circuit 8. Yes. The VDD pad 1 and the VSS pad 3 are connected to the power supply line 4 and the ground line 6, respectively, and the signal pad 2 is connected to the signal line 5. The signal line 5 is a line for transmitting a signal, and the signal pad 2 is an external connection pad for inputting and / or outputting the signal. An internal circuit is connected to the signal line 5. FIG. 4 shows a PMOS transistor P10 of the output circuit 9 of the internal circuit. The PMOS transistor P10 is a pull-up transistor that pulls up the signal line 5 in response to a signal supplied to the gate, the drain is connected to the signal line 5, and the source and back gate are connected to the power supply line 4.

In this embodiment, the electrostatic protection circuit includes a thyristor 7 and a trigger circuit 8. The thyristor 7 functions as a protective element that discharges charges when a positive ESD surge is applied to the signal pad 2. The thyristor 7 has an anode connected to the signal line 5 and a cathode connected to the ground line 6. In FIG. 4, the thyristor 7 is equivalently expressed as including a PNP transistor Q1, an NPN transistor Q2, a P well resistor R _PW , and an N well resistor _RNW .

  The trigger circuit 8 is a circuit that generates a trigger current for turning on the thyristor 7. In the present embodiment, the trigger circuit 8 includes a PMOS transistor P1, an NMOS transistor N1, and a resistance element R1. The PMOS transistor P 1 has a source connected to the gate of the thyristor 7, a drain connected to the node T 1, and a gate and a back gate connected to the power supply line 4. The NMOS transistor N1 has a drain connected to the gate of the thyristor 7, a source and a back gate connected to the ground line 6, and a gate connected to the node T1. Resistance element R1 is connected between node T1 and ground line 6.

  Below, operation | movement of the semiconductor device of this embodiment is demonstrated. As described above, when the PMOS transistor P10 is connected between the power supply line 4 and the signal line 5, when the ESD surge is applied to the signal pad 2, the potential of the power supply line 4 is changed by the parasitic diode D1. It rises with the potential of. Even in such a case, the operation of discharging the ESD surge is correctly performed in the semiconductor device of this embodiment.

Specifically, in the present embodiment, the trigger circuit 8 is configured such that a current obtained by amplifying the current I1 flowing through the PMOS transistor P1 flows through the NMOS transistor N1, and the current flowing through the NMOS transistor N1 is used as the trigger current I _trigger. used. Thereby, since the source-gate voltage of the PMOS transistor P1 is small, even if the current I1 is small, a large trigger current I _trigger can be generated and the thyristor 7 can be operated. More specifically, in the present embodiment, the trigger circuit 8 includes an amplifier circuit unit including an NMOS transistor N1 and a resistor element R1, and the current I1 flowing through the PMOS transistor P1 is amplified by the amplifier circuit unit. The amplification of the current I1 flowing through the PMOS transistor P1 is performed by flowing the current I1 through the resistance element R1 connected between the gate and source of the NMOS transistor N1. By appropriately adjusting the resistance value of the resistance element R1, the source-gate voltage of the NMOS transistor N1 when the current I1 flows can be sufficiently increased.

Here, in this embodiment, the PMOS transistor P1 and the NMOS transistor N1 generate the trigger current I _trigger by a normal MOS operation, and note that the parasitic bipolar operation is not involved in the generation of the trigger current I _trigger. I want to be. This is effective for realizing a low voltage operation.

Hereinafter, an example of the operation of the semiconductor device of this embodiment will be described in detail.
When an ESD surge is applied to the signal pad 2, the potential of the signal line 5 becomes higher than the potential of the power supply line 4, and the source potential of the PMOS transistor P1 becomes higher than the gate potential. As a result, the PMOS transistor P1 starts operating, and a current I1 flows through the PMOS transistor P1. However, since the power supply capacitor Cx is quickly charged via the parasitic diode D1 of the PMOS transistor P10, the current I1 of the PMOS transistor P1 does not become so large. The current I1 is insufficient as a trigger current for the thyristor 7.

Here, since the current I1 generated in the PMOS transistor P1 flows to the resistance element R1, the potential of the node T1, that is, the source-gate voltage of the NMOS transistor N1 rises. Here, the source-gate voltage Vgs_N1 of the NMOS transistor N1 is
Vgs_N1 = I1 · R1, (3)
It becomes.

When the current I1 flows and the potential of the node T1 becomes higher than the threshold voltage of the NMOS transistor N1, the NMOS transistor N1 operates and the trigger voltage I _trigger flows. Since the potential of the node T1 is I1 · R1, the potential of the node T1 when the current I1 is generated is set higher than the threshold voltage of the NMOS transistor N1 by appropriately setting the resistance value of the resistance element R1. In addition, the amount of current of the trigger voltage I _trigger can be adjusted. For example, when the current I1 generated in the PMOS transistor P1 is 1 mA, the source-gate voltage Vgs_N1 of the NMOS transistor N1 becomes 1 V (= 1 mA × 1 kΩ) if the resistance value of the resistance element R1 is set to 1 kΩ. The source-gate voltage Vgs_N1 exceeds a threshold voltage (for example, 0.3 to 0.6 V) and is large enough to generate a large trigger current I _trigger .

  In addition, in the present embodiment, the leakage current flowing from the signal line 5 to the ground line 6 is small even during normal operation. Due to the voltage drop at the pn junction between the anode and gate of the thyristor 7 (emitter-base junction of the PNP transistor Q1), the source of the PMOS transistor P1 is always maintained at a potential lower than the potentials of the back gate and gate during normal operation. The Here, it should be noted that during normal operation, the back gate and gate of the PMOS transistor P1 are maintained at the power supply voltage level VDD. Since the source of the PMOS transistor P1 is maintained at a potential lower than the potentials of the back gate and the gate, the PMOS transistor P1 is maintained off. Then, since the current I1 does not flow, the source-gate voltage of the NMOS transistor N1 becomes zero, and the NMOS transistor N1 is also kept off. Therefore, according to the configuration of the present embodiment, the leakage current flowing from the signal line 5 to the ground line 6 can be reduced even during normal operation.

As described above, in the semiconductor device according to the present embodiment, there is a path through which a current flows from the signal line 5 to the power supply line 4, so that a potential difference between the power supply line 4 and the signal line 5 is unlikely to occur. Also, a large trigger current I _trigger can be generated and passed through the thyristor 7. Also in this case, a low voltage operation is possible, and the leakage current flowing from the signal line 5 to the ground line 6 during normal operation can be reduced.

(Second Embodiment)
FIG. 5 is a circuit diagram showing a configuration of a semiconductor device according to the second embodiment of the present invention. In the present embodiment, a trigger circuit 8A having a configuration different from that of the first embodiment is used. Specifically, in the second embodiment, an NMOS transistor N2 and a resistance element R2 are added to the trigger circuit 8A. The NMOS transistor N2 has a drain connected to the node T2, a gate connected to the node T1, and a source connected to the ground line 6. The resistance element R2 is connected between the node T2 and the power supply line 4. The NMOS transistor N2 functions as a switch element that provides a path for current to flow from the node T2 to the ground line 6 in response to the potential of the node T1.

The trigger circuit 8A to which the NMOS transistor N2 and the resistance element R2 are added can supply more trigger current I _trigger than the trigger circuit 8 of the first embodiment. Hereinafter, the operation of the trigger circuit 8A of the second embodiment will be described in detail.

  When an ESD surge is applied to the signal pad 2, the potential of the signal line 5 becomes higher than the potential of the power supply line 4, and the source potential of the PMOS transistor P1 becomes higher than the gate potential. As a result, the PMOS transistor P1 starts operating, and a current I1 flows through the PMOS transistor P1. Since the current I1 generated in the PMOS transistor P1 flows to the resistance element R1, the potential of the node T1 rises. When the potential of the node T1 rises, the source-gate voltage of the NMOS transistor N1 rises and the NMOS transistor N1 is turned on. The above operation is the same as in the first embodiment.

In addition, when the potential of the node T1 rises, the source-gate voltage of the NMOS transistor N2 rises. Then, the NMOS transistor N2 is turned on, and a part of the discharge current of the ESD surge applied to the signal pad 2, that is, the current I2 is grounded via the parasitic diode D1 of the PMOS transistor P10 and the NMOS transistor N2. Flows on line 6. Here, it should be noted that the NMOS transistor N2 also performs a normal MOS operation and does not perform a parasitic bipolar operation. When the current I2 flows, the source-gate voltage of the PMOS transistor P1 increases due to the voltage drop of the resistance element R2. At this time, the source-gate voltage Vgs_P1 of the PMOS transistor P1 is
Vgs_P1 = Vf_D11−Vbe + I2 · R2, (4)
It becomes. Therefore, when the current I2 flows,
Vgs_P1 = Vf_D11−Vbe + I2 · R2> Vt_P1, (5)
Becomes easier to establish. Here, Vt_P1 is a threshold voltage of the PMOS transistor P1. As described above, when the current I2 flows, the difference between the source-gate voltage Vgs of the PMOS transistor P1 and the threshold voltage Vt_P1 increases, and the current I1 flowing through the PMOS transistor P1 can be increased. Due to this effect, the source-gate voltage Vgs_N1 of the NMOS transistor N1 is further increased, and more trigger current I _trigger can be supplied. This enables the thyristor 7 to operate at a low voltage and at a high speed.

Depending on the design, instead of increasing the trigger current I _trigger , it is possible to reduce the resistance value of the resistance element R1. In the second embodiment, since the current I1 flowing through the PMOS transistor P1 is increased, the equivalent trigger current I _trigger can be obtained even if the resistance value of the resistance element R1 is reduced. It is preferable to reduce the resistance value of the resistance element R1 because it is effective in reducing the circuit area and can prevent the thyristor 7 from malfunctioning due to the potential of the node T1 being raised by a high-speed pulse during normal operation. .

  Hereinafter, simulation results of operations of the semiconductor devices of the first and second embodiments will be described. FIG. 6 shows the magnitude of the trigger current generated in the conventional electrostatic protection circuit shown in FIG. 1 and the electrostatic protection circuits of the first and second embodiments shown in FIGS. It is a graph which shows the result of having calculated this by simulation. Here, the symbol “A” indicates the waveform of the trigger current in the conventional electrostatic protection circuit, and the symbols “B” and “C” indicate the electrostatic protection circuits of the first and second embodiments, respectively. The waveform of the trigger current at is shown. As understood from FIG. 6, the trigger current amount is significantly increased in the electrostatic protection circuits of the first and second embodiments as compared with the conventional electrostatic protection circuit. In the electrostatic protection circuit of the second embodiment in which the bias to the PMOS transistor P1 is enhanced, the trigger current can be further increased as compared with the electrostatic protection circuit of the first embodiment.

FIG. 7 is a graph showing an example of the operation of the electrostatic protection circuit of the second embodiment. Specifically, (1) the current I1 flowing through the PMOS transistor P1
(2) Current I2 flowing through the NMOS transistor N2
(3) Trigger current I _trigger (current flowing through the NMOS transistor N1)
The waveform is shown.

As shown in FIG. 7, first, a current I1 flows through the PMOS transistor P1. Subsequently, when the current I1 flows through the resistance element R1 and the gate-source voltage of the NMOS transistor N1 becomes equal to or higher than the threshold voltage, the NMOS transistor N1 starts a MOS operation (not a parasitic bipolar operation), and a large trigger current I _{A trigger} flows. At the same time, the gate-source voltage of the NMOS transistor N2 increases and the current I2 flows, and the gate-source voltage of the PMOS transistor P1 increases and the current I1 increases, whereby the trigger current I _{The trigger} is increased. In the operation of FIG. 7, the current I1 reaches 20 mA, while the trigger current I _trigger exceeds 50 mA.

  Although various embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments. For example, in the above-described embodiment, the case where the PMOS transistor P10 used as the pull-up transistor is connected to the signal line 5 has been described. However, the present invention can be applied to the power line 4 from the signal line 5 when an ESD surge is applied. In particular, the circuit is preferably used for a circuit in which a part of the discharge current flows, particularly a circuit in which a parasitic diode or a diode element is connected between the signal line 5 and the power supply line 4. For example, as shown in FIG. 2A, the application of the present invention is also suitable when an ESD protection diode is connected between the signal line 5 and the power supply line 4.

In the above-described embodiment, the thyristor 7 is used as a protective element of the electrostatic protection circuit. However, another protective element, for example, a PNP transistor may be used instead of the thyristor 7. FIG. 8 shows a configuration in which the thyristor 7 is replaced with a PNP transistor 7A in the electrostatic protection circuit of the first embodiment. FIG. 9 shows the thyristor 7 in the electrostatic protection circuit of the second embodiment. The configuration replaced with 7A is shown. In FIG. 8 and FIG. 9, the base resistance component and the collector resistance component of the PNP transistor 7A are described as symbols “R _B ” and “R _C ”, respectively, and an element that functions purely as a bipolar transistor is represented by the symbol “Q1” It is expressed equivalently. As shown in FIGS. 8 and 9, the PNP transistor 7A has its emitter connected to the signal line 5, its collector connected to the ground line 6, and its base connected to the trigger circuit 8 or 8A.

1: VDD pad 2: Signal pad 3: VSS pad 4: Power supply line 5: Signal line 6: Ground line 7: Thyristor 7A: PNP transistor 8, 8A: Trigger circuit 9: Output circuit 101: VDD pad 102: Signal pad 103 : VSS pad 104: Power supply line 105: Signal line 106: Ground line 107: Thyristor P1, P10, P11: PMOS transistor N1, N2: NMOS transistor D1: Diode D11: Parasitic diode D12: Static protection diode

Claims (10)

A power line;
A ground wire,
A signal line for transmitting the signal;
A signal pad connected to the signal line;
A protective element provided between the signal line and the ground line;
A trigger circuit for the protection element,
The trigger circuit is
A PMOS transistor having a gate and a back gate connected to the power supply line and a source connected to a trigger terminal of the protection element;
A first node connected to the trigger terminal, the drain of the PMOS transistor, and an amplifier circuit unit connected to the ground line;
The amplifier circuit unit is
A first resistance element connected between the first node and the ground line;
A first NMOS transistor having a drain connected to the trigger terminal, a source connected to the ground line, and a gate connected to the first node;
A second resistance element connected between the second node connected to the gate of the PMOS transistor and the power supply line;
A semiconductor device comprising: a switching element that provides a current path between the second node and the ground line in response to the potential of the first node. The semiconductor device according to claim 1,
A semiconductor device, wherein the switch element includes a second NMOS transistor having a drain connected to the second node, a gate connected to the first node, and a source connected to the ground line. The semiconductor device according to claim 1 or 2,
A semiconductor device in which a parasitic diode or a diode element is connected between the signal line and the power supply line. A semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the protection element is a thyristor. A power line;
A ground wire,
A signal line for transmitting the signal;
A signal pad connected to the signal line;
A protective element provided between the signal line and the ground line;
A trigger circuit for passing a trigger current through the protection element;
An internal circuit including an output circuit protected by the protection circuit,
The trigger circuit is
A first PMOS transistor having a gate and a back gate connected to the power supply line and a source connected to the protection element;
An amplification circuit unit that generates a second current obtained by amplifying the first current in response to a first current flowing through the first PMOS transistor;
The output circuit includes a second PMOS transistor, wherein the second PMOS transistor has a gate connected to an internal circuit, a source connected to the power supply line, and a drain connected to the signal line. The semiconductor device according to claim 5,
The amplification circuit portion of the trigger circuit is
A first resistance element connected between a first node connected to the drain of the first PMOS transistor and the ground line;
A semiconductor device comprising: a first NMOS transistor having a drain connected to the protection element, a source connected to the ground line, and a gate connected to the first node. The semiconductor device according to claim 6,
The amplifying circuit unit further includes:
A second resistance element connected between a second node connected to the gate of the first PMOS transistor and the power line;
A semiconductor device comprising: a switching element that provides a current path between the second node and the ground line in response to the potential of the first node. The semiconductor device according to claim 7,
A semiconductor device, wherein the switch element includes a second NMOS transistor having a drain connected to the second node, a gate connected to the first node, and a source connected to the ground line. A semiconductor device according to any one of claims 5 to 8,
A semiconductor device in which a parasitic diode or a diode element is connected between the signal line and the power supply line. A semiconductor device according to any one of claims 5 to 9,
The semiconductor device, wherein the protection element is a thyristor.

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