JP2014053497A - Esd protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ESD protection circuit that protects a semiconductor integrated circuit by few elements.SOLUTION: An ESD protection circuit includes an SCR 21 formed from bipolar transistors 11 and 12, and a trigger circuit 20 formed from field-effect transistors MPH and MPL and outputting a trigger for the SCR 21. A gate of the field-effect transistor MPH is connected to a first node, one end of a current path of the field-effect transistor MPH is connected to a fourth node, and the other end of the current path of the field-effect transistor MPH is connected to one end of a current path of the field-effect transistor MPL. A gate of the field-effect transistor MPL is connected to a third node, and the one end of the current path of the field-effect transistor MPL is connected to the SCR 21.

Description

  Embodiments described herein relate generally to an ESD (Electro Static Discharge) protection circuit.

  In order to prevent ESD destruction of the semiconductor circuit, an ESD protection circuit is provided in the semiconductor circuit.

  While miniaturization of elements (for example, field effect transistors) forming a semiconductor circuit is promoted, various proposals have been made regarding the circuit configuration of an ESD protection circuit.

Japanese Patent No. 4008744

  An ESD protection circuit capable of protecting a semiconductor integrated circuit with a small number of elements is proposed.

  The ESD protection circuit of the present embodiment includes a first node, a second node, a third node, a fourth node, a first emitter connected to the fourth node, and the first node. A first bipolar transistor of a first conductivity type having a first collector connected to a second node and a first base; a second emitter connected to the second node; A silicon-controlled rectifier element including a second bipolar transistor of a second conductivity type having a second collector connected to a first base and a second base connected to the first collector; A first field effect transistor of a third conductivity type having a first gate connected to a first node and one end of a first current path connected to the fourth node; and A second gate connected to the node of One end of a second current path connected to the other end of the first current path of the first field-effect transistor and the other end of the second current path connected to the second base A second diode of the third conductivity type, and a first diode having a cathode connected to a back gate of the first and second field effect transistors and an anode connected to the fourth node; Including a trigger circuit.

FIG. 10 is a diagram illustrating an example of a semiconductor circuit including an ESD protection circuit. The figure which shows the structural example of the ESD protection circuit of 1st Embodiment. The figure for demonstrating operation | movement of the ESD protection circuit of 1st Embodiment. The figure which shows the structural example of the ESD protection circuit of 2nd Embodiment. The figure which shows the modification of the ESD protection circuit of embodiment.

[Embodiment]
Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given as necessary.

(1) First embodiment
An ESD (Electro Static Discharge) protection circuit according to the first embodiment will be described with reference to FIGS.

(Constitution)
The configuration of the ESD protection circuit according to the first embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a diagram schematically showing a semiconductor circuit (for example, a semiconductor integrated circuit) in which the ESD circuit of this embodiment is used.

  As shown in FIG. 1, a plurality of pads (external connection terminals) 60, 61, 62, 63 are connected to the internal circuit 5 of a semiconductor integrated circuit (hereinafter referred to as LSI) 100.

The internal circuit 5 includes a plurality of N-type (fourth conductivity type) field effect transistors (FETs) T1 and a plurality of P-type (third conductivity types) so that a predetermined operation or function can be executed. Type) field effect transistor T2.
Among the plurality of pads 60, 61, 62, 63, the pads 60, 62, 63 are pads for supplying an external power supply voltage and ground voltage to the internal circuit 5. Of the plurality of pads 60, 61, 62, 63, the pad 61 is an I / O pad for inputting / outputting signals to / from the internal circuit 5.

  The pads 60, 62, 63 are connected to the internal circuit 5 through power supply lines and ground lines 70, 72, 73. The pad 61 is connected to the internal circuit 5 via the signal line 71.

  Hereinafter, nodes formed from pads (power supply pads) to which power supply voltage is applied and power supply lines are referred to as power supply nodes. A node formed from a pad (ground pad) to which a ground voltage is applied and a ground line is called a ground node. A node formed by the signal input / output pad 61 and the signal line 71 is called a signal node (or I / O node).

  The power supply nodes 60, 62, 70 and 72 are connected to the internal circuit 5, for example. The signal nodes 61 and 71 are connected to the input / output circuit 51 in the internal circuit 5, for example. For example, the internal circuit 5 may include a power supply circuit to which a power supply voltage from a power supply node is applied.

  The ESD protection circuit 1 of the present embodiment is provided on a common chip with the internal circuit 5. The ESD protection circuit 1 is connected to pads 60, 61, 62, 63 that are common to the internal circuit 5.

  In FIG. 1, an example in which one internal circuit 5 is provided in the LSI 100 is shown for simplification of illustration, but two or more internal circuits 5 may be provided in one LSI 100. In FIG. 1, an example in which four pads 60, 61, 62, 63 are provided for one internal circuit 5 is shown for simplification of illustration, but depending on the configuration of the internal circuit 5, Five or more pads having different functions may be provided. FIG. 1 shows an example in which one ESD protection circuit 1 is provided in one internal circuit 5, but there are a plurality of ESD protection circuits 1 depending on the configuration of the internal circuit 5 and the pads 60, 61, 62, 63. The ESD protection circuit 1 may be provided in one internal circuit 5.

  FIG. 2 is an equivalent circuit diagram showing a circuit configuration of the ESD protection circuit 1 of the present embodiment.

  For example, during the normal operation of the LSI 100, the power supply voltage VDDH is applied to the pad 60, and the voltage VDDL having a magnitude different from the voltage VDDH is applied to the pad 62. When the LSI 100 is driven by the user (when the LSI 100 is in a normal operation), the power supply line to which the ESD protection circuit 1 is connected as a voltage for driving the internal circuit 5 when these power supply voltages VDDH and VDDL greater than 0V are driven. 70, 72.

  A ground voltage is applied to the pad 63 and applied to the signal line 73 to which the ESD protection circuit 1 is connected when the internal circuit 3 is driven.

  The ESD protection circuit 1 of the present embodiment is an ESD protection circuit using a silicon controlled rectifier (SCR).

  The ESD protection circuit 1 of this embodiment is formed of a trigger circuit 20 and an SCR 21. The trigger circuit 20 includes first and second field effect transistors MPH and MPL and a diode 19. The SCR 21 includes first and second bipolar transistors (BJT: Bipolar Junction Transistors) 11 and 12. In the present embodiment, a circuit configuration in which the ESD protection circuit 1 further includes resistance elements RNW and RB and a diode 15 will be described.

  The two field effect transistors MPH and MPL forming the trigger circuit 20 are P-type MOS transistors MPH and MPL. For example, the field effect transistors MPH and MPL are enhancement type.

  The gate of the first P-type MOS transistor MPH is connected to first power supply nodes (first nodes) 60 and 70 to which the power supply voltage VDDH is applied. One end (source) of the current path of the first P-type MOS transistor MPH is directly connected to signal nodes (fourth nodes) 61 and 71.

The gate of the second P-type MOS transistor MPL is connected to second power supply nodes (third nodes) 62 and 72 to which a power supply voltage VDDL lower than the power supply voltage VDDH is applied. One end (source) of the current path of the second P-type MOS transistor MPL is connected to the other end (drain) of the current path of the first P-type MOS transistor MPH.
The other end (drain) of the current path of the second P-type MOS transistor MPL is connected to the ground nodes (second nodes) 63 and 73 via the resistance element RB. The other end of the current path of the second P-type MOS transistor MPL is connected to the SCR 21 described later.

  Well regions (not shown) in which the first and second P-type MOS transistors MPH and MPL are provided are connected to power supply nodes 60 and 70 via a resistance element RNW as a limiter resistor. The resistance element RNW is connected between the back gates (substrate terminals) of the first and second P-type MOS transistors MPH and MPL and the power supply nodes 60 and 70.

  The resistance element RNW is formed by, for example, a diffusion layer (impurity semiconductor layer) in the well region (or semiconductor substrate) or a silicon layer on the semiconductor substrate.

  A diode 19 is formed between the N-type well region where the first P-type MOS transistor MPH is provided and the P-type diffusion layer as the source / drain of the first P-type MOS transistor MPH.

Thus, the trigger circuit 20 in the ESD protection circuit 1 is formed by using two P-type MOS transistors MPH and MPL that are stacked (current paths are connected in series).
The withstand voltages (absolute values) of the P-type MOS transistors MPH and MPL in the trigger circuit 20 are smaller than the power supply voltage VDDH applied to the power supply nodes 60 and 70 on the high voltage side during the normal operation of the LSI 100.

  The SCR 21 includes a PNP type (first conductivity type) bipolar transistor 11 and an NPN type (second conductivity type) bipolar transistor 12.

The emitter of the PNP bipolar transistor 11 is connected to the signal nodes 61 and 71.
The base of the PNP bipolar transistor 11 is connected to the collector of the NPN bipolar transistor 12. A connection node (connection point) nd2 is formed by the base of the PNP type bipolar transistor 11 and the collector of the NPN type bipolar transistor 12.

The collector of the PNP bipolar transistor 11 is connected to the base of the NPN bipolar transistor. A connection node (connection point) nd1 is formed by the collector of the PNP bipolar transistor 11 and the base of the NPN bipolar transistor 12.
The collector of the PNP-type bipolar transistor 11 is connected to the drain of the P-type MOS transistor MPL. The collector of the PNP bipolar transistor 11 is connected to the ground nodes 63 and 73 via the resistance element RB.

  Here, the resistance element RB has a resistance value of a predetermined magnitude so that noise in the ESD protection circuit 1 or the internal circuit 5 can be reduced, and latch-up of the element in the ESD protection circuit 1 can be suppressed. Is formed. As a result, the operations of the ESD protection circuit 1 and the internal circuit 5 can be stabilized. For example, the resistance element RB has a resistance value of about 100Ω (for example, about 90Ω to 110Ω) according to the characteristics of the SCR 21 and the internal circuit 5. The resistance element RB is formed by, for example, a diffusion layer in the semiconductor substrate or a polysilicon layer on the semiconductor substrate.

  The SCR 21 is activated or maintained in an inactive state by a current (trigger current) supplied from the trigger circuit 20 to the SCR 21.

In the ESD protection circuit 1, the diode 15 is connected between the signal nodes 61 and 71 and the ground nodes 63 and 73. The diode 15 is connected in parallel to the SCR 21. The cathode of the diode 15 is connected to the signal nodes 61 and 71, and the anode of the diode 15 is connected to the ground nodes 63 and 73.
The diode 15 is an ESD protection diode. Hereinafter, the diode 15 is also referred to as an ESD protection diode.

  The P-type MOS transistors MPH and MPL in the ESD protection circuit 1 are formed on the same semiconductor substrate substantially simultaneously in the same manufacturing process as the MOS transistors T1 and T2 as components in the internal circuit 5. The MOS transistors MPH and MPL in the ESD protection circuit 1 have the same breakdown voltage (insulation breakdown voltage, surface breakdown voltage, or junction breakdown voltage) as the MOS transistors T1 and T2 in the internal circuit 5. For example, when the transistors T1 and T2 in the internal circuit 5 have a withstand voltage of about 1.8V, the P-type MOS transistors MPH and MPL in the ESD protection circuit 1 also have a withstand voltage of about 1.8V. In the internal circuit 5, a transistor having a withstand voltage of 1.8V is driven with a voltage of 1.8V or less.

  When the internal circuit 5 is formed using two or more types of withstand voltage MOS transistors, the withstand voltages of the MOS transistors MPH and MPL in the trigger circuit 20 are the same as the withstand voltage of the MOS transistors in the internal circuit 5. If present, the breakdown voltages of the MOS transistors MPH and MPL in the trigger circuit 20 may be different from each other.

  For example, in order to reduce the manufacturing cost of LSI, a MOS transistor (withstand voltage of about 1.8V) driven by a voltage of about 1.8V is provided in an input / output circuit driven by a voltage of 3.3V. May be.

  For example, a voltage of about 3.3V is used as the power supply voltage VDDH applied to the pad 60 on the high power supply voltage side, and a voltage of about 1.8V is used as the power supply voltage VDDL applied to the pad 62 on the low power supply voltage side. Is used. The magnitude of the power supply voltage VDDL is substantially the same as the breakdown voltage of the MOS transistors of the ESD protection circuit and the input / output circuit.

  During normal operation of the LSI, a power supply voltage VDDH greater than the withstand voltage of the field effect transistors MPH and MPL in the ESD protection circuit 1 is applied to at least one field effect transistor MPH and MPL in the ESD protection circuit 1.

  The ESD protection circuit 1 of the present embodiment is a tolerant I / O protection circuit, and is provided in the LSI 100 in order to protect the internal circuit 5 and the input / output circuit 51 from ESD generated on the I / O pad 61. Yes.

(Operation)
The operation of the ESD protection circuit 1 according to the first embodiment will be described with reference to FIG. FIG. 3 is a schematic diagram for explaining the operation of the ESD protection circuit of the present embodiment.

  The operation (ESD protection operation) of the ESD protection circuit 1 of this embodiment when ESD is applied to the pad will be described with reference to FIG.

As shown in FIG. 3A, before or when the chip of the semiconductor integrated circuit 100 is mounted on the lead frame or the printed board, the power supply voltage and the signal voltage are set to the pads 60, 61, 62. , 63 is not applied. When ESD occurs in the LSI 100 chip, an ESD voltage V _ESD (for example, a voltage of 6 V or more) may be applied to the pads 60, 61, 62, 63.

When a positive ESD voltage V _ESD is applied to the I / O pad 61, an ESD current I _ESD is generated at the signal nodes 61 and 71.

  Since the power supply voltages VDDH and VDDL are not applied to the power supply pads 60 and 62, 0V is applied to the gates of the first P-type MOS transistors MPH in the two P-type MOS transistors MPH and MPL in the trigger circuit 20. In this state, 0V is applied to the gate of the second P-type MOS transistor MPL.

When the ESD voltage V _ESD is applied to the signal line 71, the ESD voltage V _ESD is applied to the source of the first P-type MOS transistor MPH on the signal line 71 side. Further, the parasitic diode 19 of the P-type MOS transistor on the signal nodes 61 and 71 side is in a forward bias state, and the potential of the well region rises. As a result, a back bias is applied to the P-type MOS transistors MPH and MPL.

A voltage larger than the threshold voltage (absolute value) of the P-type MOS transistor MPH is applied between the gate and source of the first P-type MOS transistor MPH. Thereby, when the ESD voltage V _ESD is applied to the signal nodes 61 and 71, the P-type MOS transistor MPH on the signal line 71 side is turned on. Note that, depending on the potential difference between the gate and the source of the first P-type MOS transistor MPH without depending on the application of the back bias caused by the diode 19, there is a case where the transistor is turned on.

  A back bias is applied, and the voltages of the signal nodes 61 and 71 are applied to the source of the second P-type MOS transistor MPL via the first P-type MOS transistor MPH in the on state. While the gate potential of the P-type MOS transistor MPL is 0V, the potential of the source of the second P-type MOS transistor MPL rises.

  Therefore, also for the second P-type MOS transistor MPL, a voltage larger than the absolute value of the threshold voltage of the MOS transistor MPL is applied between the gate and source of the second P-type MOS transistor MPL. As a result, the second P-type MOS transistor MPL is turned on.

  As described above, when ESD occurs in the signal nodes 61 and 71, the enhancement type first and second P-type MOS transistors MPH and MPL shift from the off state to the on state. As a result, the trigger circuit 20 in the ESD protection circuit 1 is driven substantially simultaneously with the occurrence of ESD.

P-type MOS transistor MPH ON state in the trigger circuit 20, via the channel of MPL, a portion of the current _{I 1} of the ESD current _{I ESD} is, the base of the NPN bipolar transistor 12 in the SCR21, supplied .

The current I ₂ supplied from the P-type MOS transistors MPH, MPL in the trigger circuit 20 to the SCR 21 becomes the trigger current of the SCR 21, and the driving of the SCR 21 is started.

The SCR 21 in the driving state (active state) takes in the ESD current I _ESD of the signal nodes 61 and 71. By the driving force of the two bipolar transistors 11 and 12 forming the SCR21, most of the current I ₁ of the ESD current _{I ESD} is via a clamp path formed in SCR21, the ground line 73 from the signal line 71 Released. Therefore, the ESD protection circuit 1 can prevent the ESD voltage V _ESD and the ESD current I _ESD from being supplied into the internal circuit 5.
Therefore, internal circuit 5 is protected from positive voltage ESD generated at signal nodes 61 and 71.

When a negative ESD voltage is applied to the I / O pad 61 and the signal line 71, a forward bias is applied to the diode 15 and the diode 15 is turned on. As a result, the signal nodes 61 and 71 and the ground nodes 63 and 73 become conductive through the diode 15. The ESD current I _ESD caused by the negative ESD voltage V _ESD is discharged from the signal line 71 to the ground line 73 by the diode 15 in the on state (forward bias state).
As a result, the internal circuit 5 is protected from negative voltage ESD.

Note that ESD is an instantaneous phenomenon with a time of about several nsec to several hundred nsec. Further, most of the ESD current I _ESD is discharged to the ground line 73 by the SCR 21. Therefore, even if the generated ESD voltage V _ESD and the resulting ESD current I _ESD are larger than the breakdown voltage of the P-type MOS transistors MPH and MPL in the ESD protection circuit 1, the MOS transistors MPH and MPL are caused by ESD. There is almost no destruction.

  As shown in FIG. 3A, the ESD protection circuit 1 of this embodiment can prevent the internal circuit 5 in the LSI 100 from being destroyed by ESD.

  FIG. 3B is a diagram for explaining the operation of the ESD protection circuit 1 of the present embodiment when the LSI 100 and the internal circuit 5 are driven (for example, when used by a user).

  In a normal operation of the LSI 100 such as when the user is using, the power supply voltage VDDH is applied to the power supply nodes 60 and 70, and the power supply voltage VDDL is applied to the power supply nodes 62 and 72. A ground voltage VSS (= 0 V) is applied to the ground nodes 63 and 73.

  A voltage corresponding to the H level or the L level is applied to the signal nodes 61 and 71 according to the signal / data from the outside of the chip to the internal circuit 5 and the signal / data from the internal circuit 5 to the outside of the chip. Yes.

  Here, a case where a voltage of 3.3 V is used as the power supply voltage VDDH of the LSI 100 and a voltage of 1.8 V is used as the power supply voltage VDDL will be described. For example, in the signal levels supplied to the signal nodes 61 and 71, the H level signal level corresponds to a voltage of 1.8V to 3.3V, and the L level signal level is set to a voltage of 0V to 1.8V. It corresponds. The breakdown voltage of the P-type MOS transistors MPH and MPL is about 1.8V.

  When an H level signal (here, a voltage of 3.3V) is supplied to the signal nodes 61 and 71, the voltage VDDH applied to the gate of the P-type MOS transistor MPH of the trigger circuit 20 is 3.3V. Therefore, the potential difference between the gate and the source of the P-type MOS transistor MPH on the signal line 71 side is substantially zero. When the H level signal level is 1.8 V, which is smaller than the 3.3 V power supply voltage VDDH, the potential difference between the gate and source of the P-type MOS transistor MPH is about 1.5 V.

  Therefore, when an H level signal is applied to the signal node, the potential difference (3.3V-3.3V) applied between the gate and source of the P-type MOS transistor MPH is equal to the breakdown voltage of the P-type MOS transistor MPH. It is within the range.

  A power supply voltage VDDH as a back bias is applied to the P-type MOS transistor MPH via the resistance element RNW. By adjusting the resistance value of the well resistor RNW, the potential difference between the gate and the back gate (well region / semiconductor substrate) of the P-type MOS transistor MPH is reduced so as to be within the breakdown voltage range of the transistor MPH. Yes. For example, when the voltage drop of the resistance element RNW is ignored, a voltage of 3.3 V is applied as a back bias to the transistor in the well region where the P-type MOS transistor MPH is provided. Therefore, the gate-back gate potential difference (3.3V-3.3V) of the P-type MOS transistor MPH falls within the breakdown voltage range of the transistor MPH.

  A power supply voltage VDDL of about 1.8 V is applied to the gate of the second P-type MOS transistor MPL. The back bias applied to the second P-type MOS transistor MPL has the same magnitude as the back bias applied to the first P-type MOS transistor MPH. Therefore, the potential difference (for example, 3.3V-1.8V) between the gate and the back gate of the P-type MOS transistor MPL is within the breakdown voltage range of the P-type MOS transistor MPL. The MOS transistor MPL may be turned on by a potential difference between the gate and the back gate of the P-type MOS transistor MPL.

  In the second P-type MOS transistor MPL having the drain connected to the ground nodes 63 and 73, the potential difference between the gate and drain of the second P-type MOS transistor MPL is about 1.8V. Therefore, the potential difference between the gate and drain of the MOS transistor MPL is within the breakdown voltage range of the MOS transistor MPL.

  Here, in the ESD protection circuit 1 of the present embodiment, the source of the P-type MOS transistor MPL is related to the second P-type MOS transistor MPL between the drain of the first P-type MOS transistor MPH and the ground nodes 63 and 73. Of the LSI 100 floats (increases) to a voltage (VDDL + | VthP |) substantially equal to the sum of the voltage VDDL and the threshold voltage VthP of the transistor MPL during normal operation of the LSI 100.

Therefore, the potential of the drain of the P-type MOS transistor MPH is about VDDL + | VthP |, and the drain of the P-type MOS transistor MPH is, for example, 1.8 V or more.
As a result, the potential difference between the gate and the drain of the first P-type MOS transistor MPH and the potential difference between the source and the drain of the first P-type MOS transistor MPH (3.3V-1.8V) It is within the range of pressure resistance. For example, when the threshold voltage VthP of the MOS transistor MPL is 0.3V (absolute value), the potential difference between the gate and the drain of the P-type MOS transistor MPH is 3.3V− (1.8V + 0.3V) = 1. .5V, which is within the range of the breakdown voltage (1.8V) of the transistor.

  Further, the gate-source potential difference (1.8V-1.8V) and the source-drain potential difference (1.8V-0V) of the second P-type MOS transistor MPL are also within the breakdown voltage range of the transistor MPL. Fits in.

  As described above, in the state where the H level signal is supplied to the signal nodes 61 and 71, the potential difference between the terminals of the transistors MPH and MPL in the ESD protection circuit 1 is the voltage applied directly to each terminal. It becomes smaller and falls within the breakdown voltage range of each transistor.

Further, since the first P-type MOS transistor MPH on the signal line 71 side is in the off state, the SCR 21 is turned on even if there is a potential difference between the H level signal line 71 and the L level ground line 73. This current (trigger current) is not supplied to the SCR 21.
Therefore, when the signal levels of the signal nodes 61 and 71 are “H” level during normal operation of the LSI 100, the SCR 21 is not driven.

  When an L level signal (for example, a voltage of 0V) is supplied to the signal nodes 61 and 71, the potential difference between the gate and the source of the P-type MOS transistor MPH on the signal nodes 61 and 71 side is about 3.3V. Become a voltage. However, the P-type MOS transistor MPH is in a full bias accumulation state by the voltage applied to the gate. Therefore, if ESD (or excessive voltage due to noise) does not occur during operation, the breakdown voltage of the P-type MOS transistor MPH is guaranteed.

The current path of the second P-type MOS transistor MPL is connected to the signal nodes 61 and 71 via the accumulated first P-type MOS transistor MPH.
In the second P-type MOS transistor MPL, the second power supply voltage VDDL (about 1.8V) is set according to the potential difference between the power supply voltage VDDL applied to the gate of the transistor MPL and the back bias (about 3.3V). There is a possibility that the P-type MOS transistor MPL is turned on.

  There is a possibility that the signal nodes 61 and 71 and the ground nodes 62 and 63 become conductive via the two P-type MOS transistors MPH and MPL in the trigger circuit 20. However, since the potentials of the signal nodes 63 and 73 are at the L level, the potential difference between the signal nodes 61 and 71 and the ground nodes 62 and 63 is small (substantially zero).

  Therefore, when the signal levels of the signal nodes 61 and 71 are L level, as in the case where the signal level of the signal node is H level, the current that triggers the SCR 21 is not supplied to the SCR 21, and the SCR 21 is turned on. do not do.

  In the normal operation of the LSI 100, in the ESD protection circuit 1, the potential difference of the diode 15 between the signal nodes 61 and 71 and the ground nodes 63 and 73 is in a reverse bias state or an equipotential state. Therefore, the current flowing between the signal nodes 61 and 71 and the ground nodes 63 and 73 via the diode 15 is very small.

As shown in FIG. 3B, during normal operation of the LSI 100 (when used by a user), even when a voltage is applied to each node to which the trigger circuit 20 in the ESD protection circuit 1 is connected. The trigger circuit 20 does not supply the SCR 21 with a trigger current that drives the SCR 21.
Therefore, the ESD protection circuit 1 of the present embodiment does not adversely affect the operation of the internal circuit 5 during the normal operation of the LSI 100.

  In the ESD protection circuit 1 of the present embodiment, during the normal operation of the LSI 100, a voltage larger than the breakdown voltage of the transistors MPH and MPL is applied to at least one of the P-type MOS transistors MPH and MPL forming the trigger circuit 20 of the ESD protection circuit 1. Applied.

  In the ESD protection circuit 1 of the present embodiment, a plurality of P-type MOS transistors MPH and MPL are arranged so that the potential difference between the terminals of the P-type MOS transistors MPH and MPL in the trigger circuit 20 falls within the breakdown voltage range of the MOS transistor. And the power supply nodes 60, 70, 62, 72 and the P-type MOS transistors MPH, MPL are connected.

  As a result, the breakdown voltage of the MOS transistors MPH and MPL in the ESD protection circuit 1 is ensured, and the MOS transistors MPH and MPL can be prevented from being destroyed by a power supply voltage higher than the breakdown voltage of the transistors. As a result, malfunction of the internal circuit 5 and the LSI 100 due to the destruction of the ESD protection circuit 1 is prevented.

As described above, in the ESD protection circuit 1 of the present embodiment, during the ESD protection operation (when ESD is generated), the P-type field effect transistors MPH and MPL forming the trigger circuit 20 are turned on by the ESD voltage. A part of the current I _ESD generated by V _ESD is supplied to the SCR 21 as a trigger current. The trigger current causes the SCR 21 to be in an active state (on state), and the SCR 21 discharges the ESD voltage / current generated at the signal nodes 61 and 71 to the ground nodes 63 and 73.
As a result, the LSI 100 of the ESD protection circuit 1 of this embodiment is protected from ESD.

In the ESD protection circuit 1 of the present embodiment, even when a voltage larger than the withstand voltage of the P-type MOS transistors MPH and MPL of the ESD protection circuit 1 is applied to the ESD protection circuit 1 during the normal operation of the LSI 100, the P of the trigger circuit 20 The type field effect transistors MPH and MPL are in a voltage application state that falls within the breakdown voltage range of the MOS transistor due to the connection relationship between the elements described above. The trigger circuit 20 including the P-type MOS transistors MPH and MPL of the ESD protection circuit 1 does not output a trigger current for turning on the SCR 21 to the SCR 21.
Thereby, the SCR 21 in the ESD protection circuit 1 of the present embodiment is maintained in an inactive state (off state) during the normal operation of the LSI 100.

  Therefore, the ESD protection circuit 1 of the present embodiment can protect the internal circuit 5 of the LSI 100 from ESD and does not adversely affect the normal operation of the LSI 100 and the internal circuit 5.

Since the LSI is connected to an external device, a voltage of various magnitudes such as 3.3 V, 2.5 V, or 1.8 V is applied to the LSI as a power supply voltage of the LSI depending on the external device.
When a field effect transistor forming an LSI is miniaturized, the breakdown voltage of the field effect transistor tends to decrease.

  In a situation where miniaturization of field effect transistors in LSIs is promoted, a large withstand voltage is provided for the ESD protection circuit in a separate process from the transistors in the LSI internal circuit so as to correspond to a power supply voltage of 3.3 V or more. Forming an electric field transistor may increase the manufacturing cost of LSI.

  Further, when a resistance element or the like is added in the ESD protection circuit in order to apply a voltage smaller than the breakdown voltage of the transistor to the transistor in the ESD protection circuit, the internal configuration of the ESD protection circuit is complicated and the area of the ESD protection circuit is increased. And parasitic capacitance / parasitic resistance may increase due to the ESD protection circuit.

  The field effect transistors (for example, P-type MOS transistors) MPH and MPL that form the ESD protection circuit 1 of the present embodiment are formed simultaneously with the field effect transistors T1 and T2 that form the internal circuit 5 in a common process. Have the same characteristics (withstand voltage). For example, the ESD protection circuit 1 and the internal circuit 5 are formed using a field effect transistor having a breakdown voltage of 1.8 V or less.

  In the ESD protection circuit 1 of the present embodiment, regarding the plurality of P-type field effect transistors MPH and MPL forming the trigger circuit 20 for the SCR 21, during normal operation of the LSI 100 and the internal circuit 5, between the gate and the source, between the gate and the drain, etc. P-type field effect transistors MPH, MPL, power supply nodes, and two P-type field effect transistors MPH, MPL so that the potential difference between the terminals of P-type field effect transistors MPH, MPL does not become larger than the breakdown voltage of P-type field effect transistors MPH, MPL Each terminal (between source / drain) of the type field effect transistors MPH and MPL is connected.

  As a result, when the power supply voltage equal to or higher than the withstand voltage of the P-type field effect transistors MPH and MPL in the ESD protection circuit 1 is applied to the ESD protection circuit 1 during the normal operation of the LSI, It is possible to suppress the destruction and malfunction of the protection circuit 1 from being caused by the application of a power supply voltage that exceeds the breakdown voltage of the P-type field effect transistors MPH and MPL.

  Therefore, the ESD protection circuit 1 of the present embodiment is configured so that the field effect transistors of the ESD protection circuit and the electric field of the internal circuit 5 are secured so that the withstand voltages of the P-type field effect transistors MPH and MPL forming the ESD protection circuit 1 are ensured. There is no need to make a separate effect transistor.

  As a result, an increase in manufacturing cost of the semiconductor integrated circuit including the ESD protection circuit 1 of the present embodiment can be suppressed.

  The ESD protection circuit 1 of the present embodiment can form a simple circuit with a relatively small number of elements. As a result of the reduction in the number of elements forming the ESD protection circuit 1, the junction capacitance between the diffusion layers of the transistors MPH, MPL, 11, and 12 in the ESD protection circuit 1 and the semiconductor substrate (well region) can be reduced.

  In an LSI that inputs and outputs data of several Gbps band, considering the pulse shape of the signal waveform (for example, trapezoidal wave), a band margin of about 2 to 4 times is required to obtain operational stability and reliability. It is preferable to ensure. When such a margin for a several Gbps band is considered, the allowable range of the capacitor component of the impedance of the ESD protection circuit connected to the signal node is based on the relationship between the capacitor (C) and 1 / (2πf). 10 fF to 40 fF.

  By forming the ESD protection circuit with a small number of elements as in this embodiment, it is possible to suppress the capacitor component of the ESD protection circuit from deteriorating the operation of the LSI having the high-speed interface.

  Therefore, an LSI capable of high-speed data transfer can be provided by using the ESD protection circuit 1 of the present embodiment for an LSI.

  In this embodiment, the area of the ESD protection circuit in the chip can be reduced by reducing the number of elements forming the ESD protection circuit. As a result, LSI manufacturing costs can be reduced.

  As described above, according to the first embodiment, an ESD protection circuit capable of protecting a semiconductor integrated circuit from ESD can be provided with a small number of elements.

(2) Second embodiment
The ESD protection circuit according to the second embodiment will be described with reference to FIG. Note that substantially the same components as those of the ESD protection circuit of the first embodiment are denoted by the same reference numerals, and detailed description will be given as necessary.

  FIG. 4 is an equivalent circuit diagram showing a circuit configuration of the ESD protection circuit 1X of the second embodiment.

  As shown in FIG. 4, the ESD protection circuit 1X of the second embodiment is that the resistance element RA is connected between the power supply nodes 60 and 70 on the high power supply voltage VDDH side and the SCR 21. This is different from the ESD protection circuit of the first embodiment.

  In the ESD protection circuit 1X of the present embodiment, one end of the resistor element RA is connected to the power supply nodes 60 and 70, and the other end of the resistor element RA is the base of the PNP bipolar transistor 11 and the emitter of the NPN bipolar transistor 12. To the connection node nd2.

  The power supply voltage VDDH of the power supply nodes 60 and 70 is applied to the base (N-type impurity region) of the PNP bipolar transistor 11 and the collector (N-type impurity region) of the NPN bipolar transistor 12 through the resistance element RA. .

  A parasitic transistor or a parasitic thyristor may be formed depending on the layout of the diffusion layer and well region for forming the bipolar transistors 11 and 12 of the SCR 21. These parasitic elements can cause latch-up on the SCR 21.

  As in the ESD protection circuit 1X of the present embodiment, the power supply voltage VDDH is applied to the N-type impurity regions of the PNP-type and NPN-type bipolar transistors 11 and 12 via the resistance element RA, thereby latching up the SCR 21. Can be suppressed.

  The circuit constants of the ESD protection circuit 1 and the magnitude of the latch-up current can be controlled by adjusting the resistance values of the resistance elements RA and RB. For example, when the resistance values of the resistance elements RA and RB are decreased, the latch-up current is increased, and when the resistance values of the resistance elements RA and RB are increased, the latch-up current is decreased.

  Instead of connecting the power supply nodes 60 and 70 and the SCR 21 via the resistor element RA, a region where the SCR 21 is formed is provided in the Deep N-type well region, and the power supply voltage VDDH is applied to the region where the SCR 21 is formed. Good. Thus, the latch-up of the SCR 21 can be suppressed by the arrangement of the Deep N-type well region and the application of the power supply voltage.

  As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained, and the parasitic element caused by the well region and the diffusion layer provided in the semiconductor substrate can be used as an ESD protection circuit and an internal circuit. It is possible to prevent the circuit operation from being adversely affected.

(3) Modification
A modification of the ESD protection circuit of the embodiment will be described with reference to FIG. In addition, the description regarding a structure and operation | movement common to 1st and 2nd embodiment is given as needed.

  In the ESD protection circuit of the present embodiment, an example is shown in which a trigger circuit is formed using two MOS transistors (field effect transistors), but depending on the number of power supply voltages applied to the internal circuit, 3 The trigger circuit may be formed using two or more field effect transistors.

  In this case, different power supply voltages are applied to the gates of the MOS transistors. In the trigger circuit of the ESD protection circuit, the MOS transistor and the power supply voltage are reduced so that the magnitude of the power supply voltage applied to the gate decreases in the order from the MOS transistor on the signal line side to the field effect transistor on the ground line side. The correspondence of is set.

  For example, FIG. 5 shows a configuration example of the ESD protection circuit 1Z when three different power supply voltages VDDH, VDDM, and VDDL are applied to the LSI 100.

  As shown in FIG. 5, when the power supply voltages VDDH, VDDM, and VDDL of 5V, 3.3V, and 1.8V are applied to the internal circuit 5, they are triggered by the three P-type MOS transistors MPH, MPM, and MPL. A circuit 20Z is formed.

  During normal operation of the LSI 100, a power supply voltage (high potential) of 5V is applied to the gate of the P-type MOS transistor MPH on the signal node side, and a power supply voltage of 1.8V is applied to the gate of the P-type MOS transistor MPL on the ground node side. (Low potential) is applied. A power supply voltage (intermediate potential) of 3.3 V is applied to the gate of the P-type MOS transistor MPM between the two P-type MOS transistors MPH and MPL.

  During normal operation of the LSI and internal circuit, in the trigger circuit 20Z, the potential of the source of the P-type MOS transistor MPH directly connected to the signal node is the voltage VDDM and MOS applied to the P-type MOS transistor MPM adjacent to the source side. It floats to the magnitude of the sum (3.3+ | Vth |) of the threshold voltage Vth of the transistor. For this reason, the potential difference between the gate and source of the P-type MOS transistor MPH falls within the range of the breakdown voltage of the MOS transistor.

  The potential of the source of the P-type MOS transistor MPM is a magnitude (1.8V + | Vth |) between the voltage VDDL applied to the P-type MOS transistor MPL on the ground node side and the threshold voltage Vth of the MOS transistor. ) Float to the extent. For this reason, the potential difference between the gate and source of the P-type MOS transistor MPM falls within the range of the breakdown voltage of the MOS transistor.

  As described above, in the P-type MOS transistors MPH and MPM in the trigger circuit in which the power supply voltage larger than the breakdown voltage of the MOS transistor is applied to the gate, the MOS transistor MPL in which the power supply voltage satisfying the breakdown voltage is applied to the gate is the trigger circuit 20. Are connected to the last stage (SCR 21 side) of the MOS transistors MPH, MPM, and MPL stacked in the gate, thereby the potential difference between the gate and source of the P-type MOS transistors MPH and MPM, and the P-type MOS transistors MPH, MPH, The potential difference between the source and the drain of the MPM is within the breakdown voltage range of the transistor.

  In the ESD protection circuit 1Z of the present modification, the operation at the time of occurrence of ESD is substantially the same as the operation described in FIG. 3A in the first embodiment.

  Although the case where the power supply voltages VDDH, VDDM, and VDDL of 5V, 3.3V, and 1.8V are applied to the internal circuit is described here, the magnitudes of the power supply voltages VDDH, VDDM, and VDDL are not limited thereto. . For example, 3.3V, 2.5V, and 1.8V may be used as the power supply voltages VDDH, VDDM, and VDDL.

  As in this modification, in the LSI 100 to which three or more power supply voltages VDDH, VDDM, and VDDL are applied, the trigger circuit 20Z is formed using three or more P-type MOS transistors MPH, MPM, and MPL. The same operation as in the first and second embodiments can be performed, and the internal circuit 5 can be protected from the ESD voltage applied to the signal node.

  As described above, according to the ESD protection circuit 1 of the modification shown in FIG. 5, the same effects as those of the first and second embodiments can be obtained.

[Others]
The ESD protection circuit of the embodiment can be mounted on a chip of a semiconductor integrated circuit such as a system LSI, an image sensor, or a flash memory.

  In the above-described embodiment, the example in which the internal circuit is protected from the ESD generated in the signal nodes 61 and 71 has been described. However, the nodes 61 and 71 may be power supply nodes. Using the ESD protection circuits 1, 1X, and 1Z of the above-described examples, the internal circuit 5 (power supply circuit) is generated from the ESD generated in the pads / wirings 61 and 71 as power supply nodes. ) May be protected. In this case, if the voltage applied to the nodes 61 and 71 is equal to or lower than the voltage applied to the gate of the MOS transistor MPH directly connected to the nodes 61 and 71, the voltage applied to each terminal of the MOS transistor forming the trigger circuit. The applied voltage is within the breakdown voltage range of the transistor.

  In the ESD protection circuit of the embodiment, an example is shown in which the trigger circuit is formed using an enhancement type field effect transistor. However, the trigger circuit may be formed using a depletion type field effect transistor.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1: ESD protection circuit, 20: trigger circuit, 21: SCR, MPH, MPL: field effect transistor, 11, 12: bipolar transistor, 15: diode, 5: internal circuit, 100: semiconductor integrated circuit.

Claims (5)

A first node to which a first power supply voltage is applied;
A second node to which a second power supply voltage lower than the first power supply voltage is applied;
A third node to which a third power supply voltage having a magnitude between the first power supply voltage and the second power supply voltage is applied;
A fourth node to which the signal is supplied;
A first bipolar transistor of a first conductivity type having a first emitter connected to the fourth node, a first collector, and a first base; and connected to the second node A second bipolar transistor of a second conductivity type having a second emitter, a second collector connected to the first base, and a second base connected to the first collector. A silicon controlled rectifier,
A first field effect transistor of a third conductivity type having a first gate connected to the first node and one end of a first current path connected to the fourth node; and A second gate connected to the third node, one end of the second current path connected to the other end of the first current path of the first field effect transistor, and the second base. A cathode connected to the second field effect transistor of the third conductivity type having the other end of the second current path, and back gates of the first and second field effect transistors; A trigger circuit including a first diode having an anode connected to the node;
A first resistance element connected between a back gate of the first and second field effect transistors and the first node;
A second resistance element connected between the second node and the second base;
A second diode having an anode connected to the second node and a cathode connected to the fourth node;
The ESD protection circuit according to claim 1, wherein the first power supply voltage is larger than a withstand voltage of the first and second field effect transistors. A first node;
A second node;
A third node;
A fourth node;
A first bipolar transistor of a first conductivity type having a first emitter connected to the fourth node, a first collector connected to the second node, and a first base; and Second conductivity having a second emitter connected to the second node, a second collector connected to the first base, and a second base connected to the first collector. A silicon controlled rectifier element comprising a second bipolar transistor of the type;
A first field effect transistor of a third conductivity type having a first gate connected to the first node and one end of a first current path connected to the fourth node; and A second gate connected to the third node, one end of the second current path connected to the other end of the first current path of the first field effect transistor, and the second base. A cathode connected to a second field effect transistor of the third conductivity type having the other end of the second current path, and back gates of the first and second field effect transistors; A trigger circuit including a first diode having an anode connected to the node of
An ESD protection circuit comprising:   3. The ESD protection circuit according to claim 2, wherein the first and second power supply effect transistors have a withstand voltage lower than a first power supply voltage applied to the first node. A first resistance element connected between a back gate of the first and second field effect transistors and the first node;
A second resistance element connected between the second base and the second node;
A third resistance element connected between the first base and the first node;
The ESD protection circuit according to claim 2, further comprising:   5. The device according to claim 2, further comprising a second diode having an anode connected to the second node and a cathode connected to the fourth node. 6. ESD protection circuit.

Images