CN204392224U - Realize the change-over circuit of low pressure to high pressure - Google Patents
Realize the change-over circuit of low pressure to high pressure Download PDFInfo
- Publication number
- CN204392224U CN204392224U CN201520140800.3U CN201520140800U CN204392224U CN 204392224 U CN204392224 U CN 204392224U CN 201520140800 U CN201520140800 U CN 201520140800U CN 204392224 U CN204392224 U CN 204392224U
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- CN
- China
- Prior art keywords
- resistance
- grid
- nmos tube
- pmos
- pipe
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Abstract
The utility model discloses and a kind ofly realize the change-over circuit of low pressure to high pressure.Realize low pressure and comprise the first PMOS, the first resistance, the first NMOS tube, the second PMOS, the second resistance, the second NMOS tube, a NPN pipe, the 2nd NPN pipe, the first DMOS pipe and the 3rd resistance to the change-over circuit of high pressure.The change-over circuit utilizing the utility model to provide can realize low pressure and change to high pressure.
Description
Technical field
The utility model relates to change-over circuit, refers more particularly to and realizes the change-over circuit of low pressure to high pressure.
Background technology
In the power supply system, there is low voltage transition to arrive high-tension conversion, need low voltage signal to pass to high voltage circuit.
Summary of the invention
The utility model aims to provide and a kind ofly realizes the change-over circuit of low pressure to high pressure.
Realize the change-over circuit of low pressure to high pressure, comprise the first PMOS, the first resistance, the first NMOS tube, the second PMOS, the second resistance, the second NMOS tube, a NPN pipe, the 2nd NPN pipe, the first DMOS pipe and the 3rd resistance:
The grid of described first PMOS connects the grid of input IN and described first NMOS tube, and source electrode connects 10V power supply, and drain electrode connects one end of described first resistance;
The drain electrode of the first PMOS described in one termination of described first resistance, the grid of the drain electrode of the first NMOS tube described in another termination and the grid of described second PMOS and described second NMOS tube;
The grid of described first NMOS tube connects the grid of input IN and described first PMOS, source ground, and drain electrode connects the grid of one end of described first resistance and the grid of described second PMOS and described second NMOS tube;
The grid of described second PMOS connects the grid of one end of described first resistance and the drain electrode of described first NMOS tube and described second NMOS tube, and source electrode connects 10V power supply, and drain electrode connects one end of described second resistance;
The drain electrode of the second PMOS described in one termination of described second resistance, the drain electrode of the second NMOS tube described in another termination and the collector electrode of a described NPN pipe and the grid of described first DMOS pipe;
The grid of described second NMOS tube connects the grid of one end of described first resistance and the drain electrode of described first NMOS tube and described second PMOS, source ground, drain one end and the collector electrode of a described NPN pipe and the grid of described first DMOS pipe of connecing described second resistance;
The base stage of a described NPN pipe connects the base stage of described 2nd NPN pipe and the source electrode of collector electrode and described first DMOS pipe, and collector electrode connects the grid of one end of described second resistance and the drain electrode of described second NMOS tube and described first DMOS pipe, grounded emitter;
The base stage of described 2nd NPN pipe and collector electrode are connected together and connect the base stage of a described NPN pipe and the source electrode of described first DMOS pipe again, grounded emitter;
The grid of described first DMOS pipe connects the collector electrode of one end of described second resistance and the drain electrode of described second NMOS tube and a described NPN pipe, source electrode connects the base stage of a described NPN pipe and the base stage of described 2nd NPN pipe and collector electrode, drain electrode connect described 3rd resistance one end and as the output of whole change-over circuit;
One termination 600V power supply of described 3rd resistance, the drain electrode of the first DMOS pipe described in another termination as the output of whole change-over circuit.
The inverter that described first PMOS, described first resistance and described first NMOS tube formation inverter drive are made up of described second PMOS, described second resistance and described second NMOS tube goes to drive described first DMOS pipe again, design pipe sizing can increase gradually, improve driving force; Described first resistance and described second resistance are in order to current limliting is protected between the source and drain of described first PMOS and described second PMOS respectively; Input IN is reverse with output OUT phase place, that is to say that input IN exports OUT when being high level is low level, and exporting OUT when input IN is low level is high level, and the high level of input is different with the voltage of the high level of output, one is 10V voltage, and one is 600V voltage; A described NPN pipe and described 2nd NPN pipe form image current, when the grid voltage of described first DMOS pipe is high level, the path of electric current is formed from 600V power supply to described 3rd resistance and described first DMOS pipe and described 2nd NPN pipe, now exporting OUT is low level, the electric current of described 2nd NPN pipe gives a described NPN pipe by mirror image, and when making described second PMOS conducting, electric current flows to ground by described second resistance and a described NPN pipe; Described first DMOS pipe has high-pressure process structure can bear the withstand voltage of 650V.
Accompanying drawing explanation
Fig. 1 of the present utility modelly realizes the circuit diagram of low pressure to the change-over circuit of high pressure.
Embodiment
Below in conjunction with accompanying drawing, the utility model content is further illustrated.
Realize the change-over circuit of low pressure to high pressure, as shown in Figure 1, the first PMOS 101, first resistance 102, first NMOS tube 103, second PMOS 104, second resistance 105, second NMOS tube 106, a NPN pipe 107, the 2nd NPN pipe 108, first DMOS pipe 109 and the 3rd resistance 110 is comprised:
The grid of described first PMOS 101 connects the grid of input IN and described first NMOS tube 103, and source electrode connects 10V power supply, and drain electrode connects one end of described first resistance 102;
The drain electrode of the first PMOS 101 described in one termination of described first resistance 102, the grid of the drain electrode of the first NMOS tube 103 described in another termination and the grid of described second PMOS 104 and described second NMOS tube 106;
The grid of described first NMOS tube 103 connects the grid of input IN and described first PMOS 101, source ground, and drain electrode connects the grid of one end of described first resistance 102 and the grid of described second PMOS 104 and described second NMOS tube 106;
The grid of described second PMOS 104 connects the grid of one end of described first resistance 102 and the drain electrode of described first NMOS tube 103 and described second NMOS tube 106, and source electrode connects 10V power supply, and drain electrode connects one end of described second resistance 105;
The drain electrode of the second PMOS 104 described in one termination of described second resistance 105, the grid of the drain electrode of the second NMOS tube 106 described in another termination and the collector electrode of a described NPN pipe 107 and described first DMOS pipe 109;
The grid of described second NMOS tube 106 connects the grid of one end of described first resistance 102 and the drain electrode of described first NMOS tube 103 and described second PMOS 104, source ground, drain electrode connects the grid of one end of described second resistance 105 and the collector electrode of a described NPN pipe 107 and described first DMOS pipe 109;
The base stage of a described NPN pipe 107 connects the base stage of described 2nd NPN pipe 108 and the source electrode of collector electrode and described first DMOS pipe 109, collector electrode connects the grid of one end of described second resistance 105 and the drain electrode of described second NMOS tube 106 and described first DMOS pipe 109, grounded emitter;
The base stage of described 2nd NPN pipe 108 and collector electrode are connected together the source electrode of the base stage that connects a described NPN pipe 107 again and described first DMOS pipe 109, grounded emitter;
The grid of described first DMOS pipe 109 connects the collector electrode of one end of described second resistance 105 and the drain electrode of described second NMOS tube 106 and a described NPN pipe 107, source electrode connects the base stage of a described NPN pipe 107 and the base stage of described 2nd NPN pipe 108 and collector electrode, drain electrode connect described 3rd resistance 110 one end and as the output of whole change-over circuit;
One termination 600V power supply of described 3rd resistance 110, the drain electrode of the first DMOS pipe 109 described in another termination as the output of whole change-over circuit.
Described first PMOS 101, described first resistance 102 and described first NMOS tube 103 form the inverter that inverter drive is made up of described second PMOS 104, described second resistance 105 and described second NMOS tube 106 and go to drive described first DMOS pipe 109 again, design pipe sizing can increase gradually, improve driving force; Described first resistance 102 and described second resistance 105 are in order to current limliting is protected between the source and drain of described first PMOS 101 and described second PMOS 104 respectively; Input IN is reverse with output OUT phase place, that is to say that input IN exports OUT when being high level is low level, and exporting OUT when input IN is low level is high level, and the high level of input is different with the voltage of the high level of output, one is 10V voltage, and one is 600V voltage; A described NPN pipe 107 and described 2nd NPN pipe 108 form image current, when the grid voltage of described first DMOS pipe 109 is high level, the path of electric current is formed from 600V power supply to described 3rd resistance 110 and described first DMOS pipe 109 and described 2nd NPN pipe 108, now exporting OUT is low level, the electric current of described 2nd NPN pipe 108 gives a described NPN pipe 107 by mirror image, and when making described second PMOS 104 conducting, electric current flows to ground by described second resistance 105 and a described NPN pipe 107; Described first DMOS pipe 109 has high-pressure process structure and can bear the withstand voltage of 650V.
Claims (1)
1. realize the change-over circuit of low pressure to high pressure, it is characterized in that, comprise the first PMOS, the first resistance, the first NMOS tube, the second PMOS, the second resistance, the second NMOS tube, a NPN pipe, the 2nd NPN pipe, the first DMOS pipe and the 3rd resistance:
The grid of described first PMOS connects the grid of input IN and described first NMOS tube, and source electrode connects 1OV power supply, and drain electrode connects one end of described first resistance;
The drain electrode of the first PMOS described in one termination of described first resistance, the grid of the drain electrode of the first NMOS tube described in another termination and the grid of described second PMOS and described second NMOS tube;
The grid of described first NMOS tube connects the grid of input IN and described first PMOS, source ground, and drain electrode connects the grid of one end of described first resistance and the grid of described second PMOS and described second NMOS tube;
The grid of described second PMOS connects the grid of one end of described first resistance and the drain electrode of described first NMOS tube and described second NMOS tube, and source electrode connects 10V power supply, and drain electrode connects one end of described second resistance;
The drain electrode of the second PMOS described in one termination of described second resistance, the drain electrode of the second NMOS tube described in another termination and the collector electrode of a described NPN pipe and the grid of described first DMOS pipe;
The grid of described second NMOS tube connects the grid of one end of described first resistance and the drain electrode of described first NMOS tube and described second PMOS, source ground, drain one end and the collector electrode of a described NPN pipe and the grid of described first DMOS pipe of connecing described second resistance;
The base stage of a described NPN pipe connects the base stage of described 2nd NPN pipe and the source electrode of collector electrode and described first DMOS pipe, and collector electrode connects the grid of one end of described second resistance and the drain electrode of described second NMOS tube and described first DMOS pipe, grounded emitter;
The base stage of described 2nd NPN pipe and collector electrode are connected together and connect the base stage of a described NPN pipe and the source electrode of described first DMOS pipe again, grounded emitter;
The grid of described first DMOS pipe connects the collector electrode of one end of described second resistance and the drain electrode of described second NMOS tube and a described NPN pipe, source electrode connects the base stage of a described NPN pipe and the base stage of described 2nd NPN pipe and collector electrode, drain electrode connect described 3rd resistance one end and as the output of whole change-over circuit;
One termination 600V power supply of described 3rd resistance, the drain electrode of the first DMOS pipe described in another termination as the output of whole change-over circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520140800.3U CN204392224U (en) | 2015-03-12 | 2015-03-12 | Realize the change-over circuit of low pressure to high pressure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520140800.3U CN204392224U (en) | 2015-03-12 | 2015-03-12 | Realize the change-over circuit of low pressure to high pressure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204392224U true CN204392224U (en) | 2015-06-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520140800.3U Expired - Fee Related CN204392224U (en) | 2015-03-12 | 2015-03-12 | Realize the change-over circuit of low pressure to high pressure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204392224U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107328717A (en) * | 2017-07-06 | 2017-11-07 | 浙江工业大学 | A kind of sensing integrated circuit monitored for blood oxygen concentration |
| CN108169543A (en) * | 2016-12-07 | 2018-06-15 | 中芯国际集成电路制造(上海)有限公司 | High-voltage detecting circuit |
-
2015
- 2015-03-12 CN CN201520140800.3U patent/CN204392224U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108169543A (en) * | 2016-12-07 | 2018-06-15 | 中芯国际集成电路制造(上海)有限公司 | High-voltage detecting circuit |
| CN108169543B (en) * | 2016-12-07 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | High voltage detection circuit |
| CN107328717A (en) * | 2017-07-06 | 2017-11-07 | 浙江工业大学 | A kind of sensing integrated circuit monitored for blood oxygen concentration |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150610 Termination date: 20160312 |