CN204808087U - Current source circuit - Google Patents
Current source circuit Download PDFInfo
- Publication number
- CN204808087U CN204808087U CN201520489428.7U CN201520489428U CN204808087U CN 204808087 U CN204808087 U CN 204808087U CN 201520489428 U CN201520489428 U CN 201520489428U CN 204808087 U CN204808087 U CN 204808087U
- Authority
- CN
- China
- Prior art keywords
- grid
- nmos tube
- pmos
- drain electrode
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a current source circuit. Current source circuit includes first resistance, a NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, fourth NMOS pipe, a PMOS pipe, the 2nd PMOS pipe and the 3rd PMOS pipe.
Description
Technical field
The utility model relates to current source circuit.
Background technology
Devise a kind of current source circuit.
Summary of the invention
The utility model aims to provide a kind of current source circuit.
Current source circuit, comprises the first resistance, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the first PMOS, the second PMOS and the 3rd PMOS:
One end ground connection of described first resistance, the source electrode of the first NMOS tube described in another termination;
The grid of described first NMOS tube connects the grid of described second NMOS tube and the source electrode of drain electrode and described 4th NMOS tube, and drain electrode connects the source electrode of described 3rd NMOS tube, and source electrode connects one end of described first resistance;
The grid of described second NMOS tube and drain electrode are connected together and connect the source electrode of described 4th NMOS tube and the grid of described first NMOS tube again, source ground;
The grid of described 3rd NMOS tube connects the drain electrode of described first PMOS and the grid of described 4th NMOS tube and drain electrode, drain electrode connects the grid of the grid of described first PMOS and the grid of described second PMOS and drain electrode and described 3rd PMOS, and source electrode connects the drain electrode of described first NMOS tube;
The grid of described 4th NMOS tube and drain electrode are connected together the grid of the drain electrode that connects described first PMOS again and described 3rd NMOS tube, and source electrode connects the grid of described second NMOS tube and the grid of drain electrode and described first NMOS tube;
The grid of described first PMOS connects the grid of described second PMOS and drain electrode and the grid of described 3rd PMOS and the drain electrode of described 3rd NMOS tube, drain electrode connects the grid of described 4th NMOS tube and the grid of drain electrode and described 3rd NMOS tube, and source electrode meets supply voltage VCC;
The grid of described second PMOS and the grid and the grid of described 3rd PMOS and the drain electrode of described 3rd NMOS tube that connect described first PMOS again of being connected together that drain, source electrode meets supply voltage VCC;
The grid of described 3rd PMOS connects the drain electrode of the grid of described first PMOS and the grid of described second PMOS and drain electrode and described 3rd NMOS tube, and drain as current output terminal IOUT, source electrode meets supply voltage VCC.
The voltage at described first resistance two ends is the threshold voltage of described second NMOS tube, described first ohmically electric current is the resistance value of threshold voltage divided by described first resistance of described second NMOS tube, this electric current gives described first PMOS and described 3rd PMOS, from the drain electrode output current IO UT of described 3rd PMOS by described second PMOS mirror image again.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of current source circuit of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model content is further illustrated.
Current source circuit, as shown in Figure 1, comprises the first resistance 101, first NMOS tube 102, second NMOS tube 103, the 3rd NMOS tube 104, the 4th NMOS tube 105, first PMOS 106, second PMOS 107 and the 3rd PMOS 108:
One end ground connection of described first resistance 101, the source electrode of the first NMOS tube 102 described in another termination;
The grid of described first NMOS tube 102 connects the grid of described second NMOS tube 103 and the source electrode of drain electrode and described 4th NMOS tube 105, and drain electrode connects the source electrode of described 3rd NMOS tube 104, and source electrode connects one end of described first resistance 101;
The grid of described second NMOS tube 103 and drain electrode are connected together the grid of the source electrode that connects described 4th NMOS tube 105 again and described first NMOS tube 102, source ground;
The grid of described 3rd NMOS tube 104 connects the drain electrode of described first PMOS 106 and the grid of described 4th NMOS tube 105 and drain electrode, drain electrode connects the grid of the grid of described first PMOS 106 and the grid of described second PMOS 107 and drain electrode and described 3rd PMOS 108, and source electrode connects the drain electrode of described first NMOS tube 102;
The grid of described 4th NMOS tube 105 and drain electrode are connected together the grid of the drain electrode that connects described first PMOS 106 again and described 3rd NMOS tube 104, and source electrode connects the grid of described second NMOS tube 103 and the grid of drain electrode and described first NMOS tube 102;
The grid of described first PMOS 106 connects the grid of described second PMOS 107 and drain electrode and the grid of described 3rd PMOS 108 and the drain electrode of described 3rd NMOS tube 104, drain electrode connects the grid of described 4th NMOS tube 105 and the grid of drain electrode and described 3rd NMOS tube 104, and source electrode meets supply voltage VCC;
The grid of described second PMOS 107 and the grid and the grid of described 3rd PMOS 108 and the drain electrode of described 3rd NMOS tube 104 that connect described first PMOS 106 again of being connected together that drain, source electrode meets supply voltage VCC;
The grid of described 3rd PMOS 108 connects the drain electrode of the grid of described first PMOS 106 and the grid of described second PMOS 107 and drain electrode and described 3rd NMOS tube 104, and drain as current output terminal IOUT, source electrode meets supply voltage VCC.
The voltage at described first resistance 101 two ends is the threshold voltage of described second NMOS tube 103, electric current on described first resistance 101 is the resistance value of threshold voltage divided by described first resistance 101 of described second NMOS tube 103, this electric current gives described first PMOS 106 and described 3rd PMOS 108, from the drain electrode output current IO UT of described 3rd PMOS 108 by described second PMOS 107 mirror image again.
Claims (1)
1. current source circuit, is characterized in that: comprise the first resistance, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the first PMOS, the second PMOS and the 3rd PMOS;
One end ground connection of described first resistance, the source electrode of the first NMOS tube described in another termination;
The grid of described first NMOS tube connects the grid of described second NMOS tube and the source electrode of drain electrode and described 4th NMOS tube, and drain electrode connects the source electrode of described 3rd NMOS tube, and source electrode connects one end of described first resistance;
The grid of described second NMOS tube and drain electrode are connected together and connect the source electrode of described 4th NMOS tube and the grid of described first NMOS tube again, source ground;
The grid of described 3rd NMOS tube connects the drain electrode of described first PMOS and the grid of described 4th NMOS tube and drain electrode, drain electrode connects the grid of the grid of described first PMOS and the grid of described second PMOS and drain electrode and described 3rd PMOS, and source electrode connects the drain electrode of described first NMOS tube;
The grid of described 4th NMOS tube and drain electrode are connected together the grid of the drain electrode that connects described first PMOS again and described 3rd NMOS tube, and source electrode connects the grid of described second NMOS tube and the grid of drain electrode and described first NMOS tube;
The grid of described first PMOS connects the grid of described second PMOS and drain electrode and the grid of described 3rd PMOS and the drain electrode of described 3rd NMOS tube, drain electrode connects the grid of described 4th NMOS tube and the grid of drain electrode and described 3rd NMOS tube, and source electrode meets supply voltage VCC;
The grid of described second PMOS and the grid and the grid of described 3rd PMOS and the drain electrode of described 3rd NMOS tube that connect described first PMOS again of being connected together that drain, source electrode meets supply voltage VCC;
The grid of described 3rd PMOS connects the drain electrode of the grid of described first PMOS and the grid of described second PMOS and drain electrode and described 3rd NMOS tube, and drain as current output terminal IOUT, source electrode meets supply voltage VCC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520489428.7U CN204808087U (en) | 2015-07-03 | 2015-07-03 | Current source circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520489428.7U CN204808087U (en) | 2015-07-03 | 2015-07-03 | Current source circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204808087U true CN204808087U (en) | 2015-11-25 |
Family
ID=54592876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520489428.7U Expired - Fee Related CN204808087U (en) | 2015-07-03 | 2015-07-03 | Current source circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204808087U (en) |
-
2015
- 2015-07-03 CN CN201520489428.7U patent/CN204808087U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151125 Termination date: 20160703 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |