CN204808104U

CN204808104U - Zero temperature coefficient's reference voltage source

Info

Publication number: CN204808104U
Application number: CN201520513386.6U
Authority: CN
Inventors: 齐盛
Original assignee: Hangzhou Kuanfu Technology Co Ltd
Current assignee: Hangzhou Kuanfu Technology Co Ltd
Priority date: 2015-07-13
Filing date: 2015-07-13
Publication date: 2015-11-25
Anticipated expiration: 2025-07-13

Abstract

The utility model discloses a zero temperature coefficient's reference voltage source. Zero temperature coefficient's reference voltage source includes a PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, fourth PMOS pipe, the 5th PMOS pipe, a NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe, fourth NMOS pipe and the 8th PMOS pipe. Utilize the utility model provides a zero temperature coefficient's reference voltage source can export zero temperature coefficient's reference voltage.

Description

A kind of reference voltage source of zero-temperature coefficient

Technical field

The utility model relates to reference current source, refers more particularly to the reference voltage source of zero-temperature coefficient.

Background technology

In order to reduce the impact of temperature on reference voltage, devise a kind of reference voltage source of zero-temperature coefficient.

Summary of the invention

The utility model aims to provide a kind of reference voltage source of zero-temperature coefficient.

A reference voltage source for zero-temperature coefficient, comprises the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 6th PMOS, the 7th PMOS, the 4th NMOS tube and the 8th PMOS:

The grid of described first PMOS connects the grid of described 4th PMOS and the grid of described 5th PMOS and drain electrode and the grid of described 7th PMOS and the drain electrode of described second NMOS tube, drain electrode connects the source electrode of described second PMOS and the grid of described 3rd PMOS, and source electrode meets supply voltage VCC;

The grounded-grid of described second PMOS, grounded drain, source electrode connects the drain electrode of described first PMOS and the grid of described 3rd PMOS;

The grid of described 3rd PMOS connects the drain electrode of described first PMOS and the source electrode of described second PMOS, drain electrode connects the grid of the drain electrode of described 4th PMOS and the grid of described first NMOS tube and drain electrode and described second NMOS tube, and source electrode meets supply voltage VCC;

The grid of described 4th PMOS connects the grid of described first PMOS and the grid of described 5th PMOS and drain electrode and the grid of described 7th PMOS and the drain electrode of described second NMOS tube, drain electrode connects the grid of the drain electrode of described 3rd PMOS and the grid of described first NMOS tube and drain electrode and described second NMOS tube, and source electrode meets supply voltage VCC;

The grid of described 5th PMOS and drain electrode are connected together the grid of the grid that connects described first PMOS again and described 4th PMOS and the grid of described 7th PMOS and the drain electrode of described second NMOS tube, and source electrode meets supply voltage VCC;

The grid of described first NMOS tube and the drain electrode and the drain electrode of described 4th PMOS and the grid of described second NMOS tube that connect described 3rd PMOS 3 again of being connected together that drain, source ground;

The grid of described second NMOS tube connects the drain electrode of described 3rd PMOS and the drain electrode of described 4th PMOS and the grid of described first NMOS tube and drain electrode, drain electrode connects the grid of the grid of described first PMOS and the grid of described 4th PMOS and described 5th PMOS and the grid of drain electrode and described 7th PMOS, and source electrode connects the drain electrode of described 3rd NMOS tube;

The grid of described 3rd NMOS tube meets supply voltage VCC, and drain electrode connects the source electrode of described second NMOS tube, and source electrode connects the source electrode of described 6th PMOS;

The grounded-grid of described 6th PMOS, grounded drain, source electrode connects the source electrode of described 3rd NMOS tube;

The grid of described 7th PMOS connects the grid of the grid of described first PMOS and the grid of described 4th PMOS and described 5th PMOS and the drain electrode of drain electrode and described second NMOS tube, drain electrode connects the drain electrode of described 4th NMOS tube and as reference voltage source reference voltage output end VREF, source electrode meets supply voltage VCC;

The grid of described 4th NMOS tube meets supply voltage VCC, and drain electrode connects the drain electrode of described 7th PMOS, and source electrode connects the source electrode of described 8th PMOS;

The grounded-grid of described 8th PMOS, grounded drain, source electrode connects the source electrode of described 4th NMOS tube.

Described first PMOS, described second PMOS and described 3rd PMOS form start-up circuit part, grid conducting by the grounded-grid of described second PMOS of described second PMOS, starting current is had to pass to by described first NMOS tube, described second NMOS tube, described 3rd NMOS tube and described 6th PMOS form the core of current source, starting current is given described second NMOS tube by described first NMOS tube mirror image and then whole current source is started working, the core of current source is passed to again by described 5th PMOS and described 4th PMOS feedback circuit, after start-up circuit provides starting current, after current source normally works, because described first PMOS conducting makes the grid of described 3rd PMOS draw high, the drain electrode of described 3rd PMOS would not have outflow of bus current, and start-up circuit part is closed, electric current in described 3rd NMOS tube and described 6th PMOS is the RDS resistance sum that the threshold voltage of described first NMOS tube is formed divided by described 3rd NMOS tube and described 6th PMOS, the RDS resistance formed due to described 3rd NMOS tube is positive temperature coefficient (PTC), the RDS resistance that described 6th PMOS is formed is negative temperature coefficient, reaches zero-temperature coefficient by regulating the temperature coefficient of these two resistance, electric current in described 3rd NMOS tube and described 6th PMOS gives described 7th pmos current by described 5th PMOS mirror image again, the drain current of described 7th PMOS is added in the RDS resistance sum that formed by described 4th NMOS tube and described 8th PMOS and produces reference voltage V REF, reach zero-temperature coefficient resistance value by the temperature coefficient of the RDS resistance regulating described 4th NMOS tube and described 8th PMOS, so just produce the reference voltage V REF of zero-temperature coefficient.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of the reference voltage source of zero-temperature coefficient of the present utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model content is further illustrated.

A kind of reference voltage source of zero-temperature coefficient, as shown in Figure 1, the first PMOS 101, second PMOS 102, the 3rd PMOS 103, the 4th PMOS 104, the 5th PMOS 105, first NMOS tube 106, second NMOS tube 107, the 3rd NMOS tube 108, the 6th PMOS 109, the 7th PMOS 110, the 4th NMOS tube 111 and the 8th PMOS 112 is comprised:

The grid of described first PMOS 101 connects the grid of described 4th PMOS 104 and the grid of described 5th PMOS 105 and drain electrode and the grid of described 7th PMOS 110 and the drain electrode of described second NMOS tube 107, drain electrode connects the source electrode of described second PMOS 102 and the grid of described 3rd PMOS 103, and source electrode meets supply voltage VCC;

The grounded-grid of described second PMOS 102, grounded drain, source electrode connects the drain electrode of described first PMOS 101 and the grid of described 3rd PMOS 103;

The grid of described 3rd PMOS 103 connects the drain electrode of described first PMOS 101 and the source electrode of described second PMOS 102, drain electrode connects the grid of the drain electrode of described 4th PMOS 104 and the grid of described first NMOS tube 106 and drain electrode and described second NMOS tube 107, and source electrode meets supply voltage VCC;

The grid of described 4th PMOS 104 connects the grid of described first PMOS 101 and the grid of described 5th PMOS 105 and drain electrode and the grid of described 7th PMOS 110 and the drain electrode of described second NMOS tube 107, drain electrode connects the grid of the drain electrode of described 3rd PMOS 103 and the grid of described first NMOS tube 106 and drain electrode and described second NMOS tube 107, and source electrode meets supply voltage VCC;

The grid of described 5th PMOS 105 and drain electrode are connected together the drain electrode of the grid that connects described first PMOS 101 again and the grid of described 4th PMOS 104 and the grid of described 7th PMOS 110 and described second NMOS tube 107, and source electrode meets supply voltage VCC;

The grid of described first NMOS tube 106 and the drain electrode and the drain electrode of described 4th PMOS 104 and the grid of described second NMOS tube 107 that connect described 3rd PMOS 103 again of being connected together that drain, source ground;

The grid of described second NMOS tube 107 connects grid and the drain electrode of the drain electrode of described 3rd PMOS 103 and the drain electrode of described 4th PMOS 104 and described first NMOS tube 106, drain electrode connects the grid of the grid of described first PMOS 101 and the grid of described 4th PMOS 104 and described 5th PMOS 105 and the grid of drain electrode and described 7th PMOS 110, and source electrode connects the drain electrode of described 3rd NMOS tube 108;

The grid of described 3rd NMOS tube 108 meets supply voltage VCC, and drain electrode connects the source electrode of described second NMOS tube 107, and source electrode connects the source electrode of described 6th PMOS 109;

The grounded-grid of described 6th PMOS 109, grounded drain, source electrode connects the source electrode of described 3rd NMOS tube 108;

The grid of described 7th PMOS 110 connects the grid of the grid of described first PMOS 101 and the grid of described 4th PMOS 104 and described 5th PMOS 105 and the drain electrode of drain electrode and described second NMOS tube 107, drain electrode connects the drain electrode of described 4th NMOS tube 111 and as reference voltage source reference voltage output end VREF, source electrode meets supply voltage VCC;

The grid of described 4th NMOS tube 111 meets supply voltage VCC, and drain electrode connects the drain electrode of described 7th PMOS 110, and source electrode connects the source electrode of described 8th PMOS 112;

The grounded-grid of described 8th PMOS 112, grounded drain, source electrode connects the source electrode of described 4th NMOS tube 111.

Described first PMOS 101, described second PMOS 102 and described 3rd PMOS 103 form start-up circuit part, grid conducting by the grounded-grid of described second PMOS 102 of described second PMOS 103, starting current is had to pass to by described first NMOS tube 106, described second NMOS tube 107, described 3rd NMOS tube 108 and described 6th PMOS 109 form the core of current source, starting current is given described second NMOS tube 107 by described first NMOS tube 106 mirror image and then whole current source is started working, the core of current source is passed to again by described 5th PMOS 105 and described 4th PMOS 104 feedback circuit, after start-up circuit provides starting current, after current source normally works, because described first PMOS 101 conducting makes the grid of described 3rd PMOS 103 draw high, the drain electrode of described 3rd PMOS 103 would not have outflow of bus current, and start-up circuit part is closed, electric current in described 3rd NMOS tube 108 and described 6th PMOS 109 is the RDS resistance sum that the threshold voltage of described first NMOS tube 106 is formed divided by described 3rd NMOS tube 108 and described 6th PMOS 109, the RDS resistance formed due to described 3rd NMOS tube 108 is positive temperature coefficient (PTC), the RDS resistance that described 6th PMOS 109 is formed is negative temperature coefficient, reaches zero-temperature coefficient by regulating the temperature coefficient of these two resistance, electric current in described 3rd NMOS tube 108 and described 6th PMOS 109 gives described 7th PMOS 110 electric current by described 5th PMOS 105 mirror image again, the drain current of described 7th PMOS 110 is added in the RDS resistance sum that formed by described 4th NMOS tube 111 and described 8th PMOS 112 and produces reference voltage V REF, reach zero-temperature coefficient resistance value by the temperature coefficient of the RDS resistance regulating described 4th NMOS tube 111 and described 8th PMOS 112, so just produce the reference voltage V REF of zero-temperature coefficient.

Claims

1. a reference voltage source for zero-temperature coefficient, is characterized in that: comprise the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 6th PMOS, the 7th PMOS, the 4th NMOS tube and the 8th PMOS;