CN204808091U - Current source - Google Patents

Abstract

The utility model discloses a current source. Current source includes an operational amplifier, a PMOS pipe, a NMOS pipe, the 2nd NMOS pipe, the 2nd PMOS pipe, the 3rd NMOS pipe and fourth NMOS pipe.

Description

Current source

Technical field

The utility model relates to current source.

Background technology

Devise a kind of current source.

Summary of the invention

The utility model aims to provide a kind of current source.

Current source, comprises the first operational amplifier, the first PMOS, the first NMOS tube, the second NMOS tube, the second PMOS, the 3rd NMOS tube and the 4th NMOS tube:

The positive input termination reference voltage V REF of described first operational amplifier, the source electrode of the first NMOS tube described in negative input termination and the drain electrode of described second NMOS tube, export the grid of the first NMOS tube described in termination;

The grid of described first PMOS and drain electrode are connected together the grid of the drain electrode that connects described first NMOS tube again and described second PMOS, and source electrode meets supply voltage VCC;

The grid of described first NMOS tube connects the output terminal of described first operational amplifier, drain electrode connects the grid of described first PMOS and the grid of drain electrode and described second PMOS, and source electrode connects the negative input end of described first operational amplifier and the drain electrode of described second NMOS tube;

The grid of described second NMOS tube connects the grid of the drain electrode of described second PMOS and the grid of described 3rd NMOS tube and drain electrode and described 4th NMOS tube, drain electrode connects the source electrode of described first NMOS tube and the negative input end of described first operational amplifier, source ground;

The grid of described second PMOS connects the grid of described first PMOS and the drain electrode of drain electrode and described first NMOS tube, drain electrode connects the grid of the grid of described second NMOS tube and the grid of described 3rd NMOS tube and drain electrode and described 4th NMOS tube, and source electrode meets supply voltage VCC;

The grid of described 3rd NMOS tube and the grid and the drain electrode of described second PMOS and the grid of described 4th NMOS tube that connect described second NMOS tube again of being connected together that drain, source ground;

The grid of described 4th NMOS tube connects the drain electrode of the grid of described second NMOS tube and the grid of described 3rd NMOS tube and drain electrode and described second PMOS, drains as current output terminal IOUT, source ground.

Described first operational amplifier and described first NMOS tube form follower, described second NMOS tube is made to be in linear zone between the source-drain electrode that reference voltage V REF is just added in described second NMOS tube, and generation current, then described second PMOS is given by described first PMOS mirror image, described second NMOS tube and described 4th NMOS tube is given again, generation current IOUT by described 3rd NMOS tube mirror image.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of current source of the present utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model content is further illustrated.

Current source, as shown in Figure 1, comprises the first operational amplifier 101, first PMOS 102, first NMOS tube 103, second NMOS tube 104, second PMOS 105, the 3rd NMOS tube 106 and the 4th NMOS tube 107:

The positive input termination reference voltage V REF of described first operational amplifier 101, the source electrode of the first NMOS tube 103 described in negative input termination and the drain electrode of described second NMOS tube 104, export the grid of the first NMOS tube 103 described in termination;

The grid of described first PMOS 102 and drain electrode are connected together the grid of the drain electrode that connects described first NMOS tube 103 again and described second PMOS 105, and source electrode meets supply voltage VCC;

The grid of described first NMOS tube 103 connects the output terminal of described first operational amplifier 101, drain electrode connects the grid of described first PMOS 102 and the grid of drain electrode and described second PMOS 105, and source electrode connects the negative input end of described first operational amplifier 101 and the drain electrode of described second NMOS tube 104;

The grid of described second NMOS tube 104 connects the grid of the drain electrode of described second PMOS 105 and the grid of described 3rd NMOS tube 106 and drain electrode and described 4th NMOS tube 107, drain electrode connects the source electrode of described first NMOS tube 103 and the negative input end of described first operational amplifier 101, source ground;

The grid of described second PMOS 105 connects the grid of described first PMOS 102 and the drain electrode of drain electrode and described first NMOS tube 103, drain electrode connects the grid of the grid of described second NMOS tube 104 and the grid of described 3rd NMOS tube 106 and drain electrode and described 4th NMOS tube 107, and source electrode meets supply voltage VCC;

The grid of described 3rd NMOS tube 106 and the grid and the drain electrode of described second PMOS 105 and the grid of described 4th NMOS tube 107 that connect described second NMOS tube 104 again of being connected together that drain, source ground;

The grid of described 4th NMOS tube 107 connects the drain electrode of the grid of described second NMOS tube 104 and the grid of described 3rd NMOS tube 106 and drain electrode and described second PMOS 105, drains as current output terminal IOUT, source ground.

Described first operational amplifier 101 and described first NMOS tube 103 form follower, described second NMOS tube 104 is made to be in linear zone between the source-drain electrode that reference voltage V REF is just added in described second NMOS tube 104, and generation current, then described second PMOS 105 is given by described first PMOS 102 mirror image, described second NMOS tube 104 and described 4th NMOS tube 107 is given again, generation current IOUT by described 3rd NMOS tube 106 mirror image.

Claims (1)

1. current source, is characterized in that: comprise the first operational amplifier, the first PMOS, the first NMOS tube, the second NMOS tube, the second PMOS, the 3rd NMOS tube and the 4th NMOS tube;

The positive input termination reference voltage V REF of described first operational amplifier, the source electrode of the first NMOS tube described in negative input termination and the drain electrode of described second NMOS tube, export the grid of the first NMOS tube described in termination;

The grid of described first PMOS and drain electrode are connected together the grid of the drain electrode that connects described first NMOS tube again and described second PMOS, and source electrode meets supply voltage VCC;

The grid of described first NMOS tube connects the output terminal of described first operational amplifier, drain electrode connects the grid of described first PMOS and the grid of drain electrode and described second PMOS, and source electrode connects the negative input end of described first operational amplifier and the drain electrode of described second NMOS tube;

The grid of described second NMOS tube connects the grid of the drain electrode of described second PMOS and the grid of described 3rd NMOS tube and drain electrode and described 4th NMOS tube, drain electrode connects the source electrode of described first NMOS tube and the negative input end of described first operational amplifier, source ground;

The grid of described second PMOS connects the grid of described first PMOS and the drain electrode of drain electrode and described first NMOS tube, drain electrode connects the grid of the grid of described second NMOS tube and the grid of described 3rd NMOS tube and drain electrode and described 4th NMOS tube, and source electrode meets supply voltage VCC;

The grid of described 3rd NMOS tube and the grid and the drain electrode of described second PMOS and the grid of described 4th NMOS tube that connect described second NMOS tube again of being connected together that drain, source ground;

The grid of described 4th NMOS tube connects the drain electrode of the grid of described second NMOS tube and the grid of described 3rd NMOS tube and drain electrode and described second PMOS, drains as current output terminal IOUT, source ground.