CN204719588U - A kind of temperature independent current source - Google Patents
A kind of temperature independent current source Download PDFInfo
- Publication number
- CN204719588U CN204719588U CN201520449218.5U CN201520449218U CN204719588U CN 204719588 U CN204719588 U CN 204719588U CN 201520449218 U CN201520449218 U CN 201520449218U CN 204719588 U CN204719588 U CN 204719588U
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- CN
- China
- Prior art keywords
- pmos
- grid
- drain electrode
- nmos tube
- connects
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Abstract
The utility model discloses a kind of temperature independent current source.Temperature independent current source comprises the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the first resistance and the 6th PMOS.The temperature independent current source utilizing the utility model to provide can export temperature independent electric current.
Description
Technical field
The utility model relates to current source, refers more particularly to temperature independent current source.
Background technology
In order to reduce the impact of temperature on output current, devise temperature independent current source.
Summary of the invention
The utility model aims to provide a kind of temperature independent current source.
A temperature independent current source, comprises the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the first resistance and the 6th PMOS:
The grid of described first PMOS connects the grid of described 4th PMOS and the grid of described 5th PMOS and drain electrode and the grid of described 6th PMOS and the drain electrode of described second NMOS tube, drain electrode connects the source electrode of described second PMOS and the grid of described 3rd PMOS, and source electrode meets supply voltage VCC;
The grounded-grid of described second PMOS, grounded drain, source electrode connects the drain electrode of described first PMOS and the grid of described 3rd PMOS;
The grid of described 3rd PMOS connects the drain electrode of described first PMOS and the source electrode of described second PMOS, drain electrode connects the grid of the drain electrode of described 4th PMOS and the grid of described first NMOS tube and drain electrode and described second NMOS tube, and source electrode meets supply voltage VCC;
The grid of described 4th PMOS connects the grid of described first PMOS and the grid of described 5th PMOS and drain electrode and the grid of described 6th PMOS and the drain electrode of described second NMOS tube, drain electrode connects the grid of the drain electrode of described 3rd PMOS and the grid of described first NMOS tube and drain electrode and described second NMOS tube, and source electrode meets supply voltage VCC;
The grid of described 5th PMOS and drain electrode are connected together the grid of the grid that connects described first PMOS again and described 4th PMOS and the grid of described 6th PMOS and the drain electrode of described second NMOS tube, and source electrode meets supply voltage VCC;
The grid of described first NMOS tube and the drain electrode and the drain electrode of described 4th PMOS and the grid of described second NMOS tube that connect described 3rd PMOS again of being connected together that drain, source ground;
The grid of described second NMOS tube connects the drain electrode of described 3rd PMOS and the drain electrode of described 4th PMOS and the grid of described first NMOS tube and drain electrode, drain electrode connects the grid of the grid of described first PMOS and the grid of described 4th PMOS and described 5th PMOS and the grid of drain electrode and described 6th PMOS, and source electrode connects the drain electrode of described 3rd NMOS tube;
The grid of described 3rd NMOS tube meets supply voltage VCC, and drain electrode connects the source electrode of described second NMOS tube, and source electrode connects one end of described first resistance;
The source electrode of the 3rd NMOS tube described in one termination of described first resistance, other end ground connection;
The grid of described 6th PMOS connects the grid of the grid of described first PMOS and the grid of described 4th PMOS and described 5th PMOS and the drain electrode of drain electrode and described second NMOS tube, and drain as current output terminal IOUT, source electrode meets supply voltage VCC.
Described first PMOS, described second PMOS and described 3rd PMOS form start-up circuit part, grid conducting by the grounded-grid of described second PMOS of described second PMOS, have starting current to pass to be managed by a described NPN, described 2nd NPN pipe, described 3rd NPN pipe and described first resistance form the core of current source, starting current is given described 2nd NPN pipe by a described NPN pipe mirror image and then whole current source is started working, the core of current source is passed to again by described 5th PMOS and described 4th PMOS feedback circuit, after start-up circuit provides starting current, after current source normally works, because described first PMOS conducting makes the grid of described 3rd PMOS draw high, the drain electrode of described 3rd PMOS would not have outflow of bus current, and start-up circuit part is closed, described first ohmically electric current is the RDS resistance sum that the threshold voltage of described first NMOS tube is formed divided by described first resistance and described 3rd NMOS tube, the RDS resistance formed due to described 3rd NMOS tube is positive temperature coefficient (PTC), described first resistance will arrange the polycrystalline POLY resistance of negative temperature coefficient, reach zero-temperature coefficient by regulating the temperature coefficient of these two resistance, described first ohmically electric current gives described 6th pmos current IOUT by described 5th PMOS mirror image again.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of temperature independent current source of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model content is further illustrated.
A kind of temperature independent current source, as shown in Figure 1, the first PMOS 101, second PMOS 102, the 3rd PMOS 103, the 4th PMOS 104, the 5th PMOS 105, first NMOS tube 106, second NMOS tube 107, the 3rd NMOS tube 108, first resistance 109 and the 6th PMOS 110 is comprised:
The grid of described first PMOS 101 connects the grid of described 4th PMOS 104 and the grid of described 5th PMOS 105 and drain electrode and the grid of described 6th PMOS 110 and the drain electrode of described second NMOS tube 107, drain electrode connects the source electrode of described second PMOS 102 and the grid of described 3rd PMOS 103, and source electrode meets supply voltage VCC;
The grounded-grid of described second PMOS 102, grounded drain, source electrode connects the drain electrode of described first PMOS 101 and the grid of described 3rd PMOS 103;
The grid of described 3rd PMOS 103 connects the drain electrode of described first PMOS 101 and the source electrode of described second PMOS 102, drain electrode connects the grid of the drain electrode of described 4th PMOS 104 and the grid of described first NMOS tube 106 and drain electrode and described second NMOS tube 107, and source electrode meets supply voltage VCC;
The grid of described 4th PMOS 104 connects the grid of described first PMOS 101 and the grid of described 5th PMOS 105 and drain electrode and the grid of described 6th PMOS 110 and the drain electrode of described second NMOS tube 107, drain electrode connects the grid of the drain electrode of described 3rd PMOS 103 and the grid of described first NMOS tube 106 and drain electrode and described second NMOS tube 107, and source electrode meets supply voltage VCC;
The grid of described 5th PMOS 105 and drain electrode are connected together the drain electrode of the grid that connects described first PMOS 101 again and the grid of described 4th PMOS 104 and the grid of described 6th PMOS 110 and described second NMOS tube 107, and source electrode meets supply voltage VCC;
The grid of described first NMOS tube 106 and the drain electrode and the drain electrode of described 4th PMOS 104 and the grid of described second NMOS tube 107 that connect described 3rd PMOS 103 again of being connected together that drain, source ground;
The grid of described second NMOS tube 107 connects grid and the drain electrode of the drain electrode of described 3rd PMOS 103 and the drain electrode of described 4th PMOS 104 and described first NMOS tube 106, drain electrode connects the grid of the grid of described first PMOS 101 and the grid of described 4th PMOS 104 and described 5th PMOS 105 and the grid of drain electrode and described 6th PMOS 110, and source electrode connects the drain electrode of described 3rd NMOS tube 108;
The grid of described 3rd NMOS tube 108 meets supply voltage VCC, and drain electrode connects the source electrode of described second NMOS tube 107, and source electrode connects one end of described first resistance 109;
The source electrode of the 3rd NMOS tube 108 described in one termination of described first resistance 109, other end ground connection;
The grid of described 6th PMOS 110 connects the grid of the grid of described first PMOS 101 and the grid of described 4th PMOS 104 and described 5th PMOS 105 and the drain electrode of drain electrode and described second NMOS tube 107, drain electrode is as current output terminal IOUT, and source electrode meets supply voltage VCC.
Described first PMOS 101, described second PMOS 102 and described 3rd PMOS 103 form start-up circuit part, grid conducting by the grounded-grid of described second PMOS 102 of described second PMOS 103, starting current is had to pass to by a described NPN pipe 106, described 2nd NPN pipe 107, described 3rd NPN pipe 108 and described first resistance 109 form the core of current source, starting current is given described 2nd NPN pipe 107 by described NPN pipe 106 mirror image and then whole current source is started working, the core of current source is passed to again by described 5th PMOS 105 and described 4th PMOS 104 feedback circuit, after start-up circuit provides starting current, after current source normally works, because described first PMOS 101 conducting makes the grid of described 3rd PMOS 103 draw high, the drain electrode of described 3rd PMOS 103 would not have outflow of bus current, and start-up circuit part is closed, electric current on described first resistance 109 is the RDS resistance sum that the threshold voltage of described first NMOS tube 106 is formed divided by described first resistance 109 and described 3rd NMOS tube 108, the RDS resistance formed due to described 3rd NMOS tube 108 is positive temperature coefficient (PTC), described first resistance 109 will arrange the polycrystalline POLY resistance of negative temperature coefficient, reach zero-temperature coefficient by regulating the temperature coefficient of these two resistance, electric current on described first resistance 109 gives described 6th PMOS 110 electric current I OUT by described 5th PMOS 105 mirror image again.
Claims (1)
1. a temperature independent current source, is characterized in that: comprise the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the first resistance and the 6th PMOS;
The grid of described first PMOS connects the grid of described 4th PMOS and the grid of described 5th PMOS and drain electrode and the grid of described 6th PMOS and the drain electrode of described second NMOS tube, drain electrode connects the source electrode of described second PMOS and the grid of described 3rd PMOS, and source electrode meets supply voltage VCC;
The grounded-grid of described second PMOS, grounded drain, source electrode connects the drain electrode of described first PMOS and the grid of described 3rd PMOS;
The grid of described 3rd PMOS connects the drain electrode of described first PMOS and the source electrode of described second PMOS, drain electrode connects the grid of the drain electrode of described 4th PMOS and the grid of described first NMOS tube and drain electrode and described second NMOS tube, and source electrode meets supply voltage VCC;
The grid of described 4th PMOS connects the grid of described first PMOS and the grid of described 5th PMOS and drain electrode and the grid of described 6th PMOS and the drain electrode of described second NMOS tube, drain electrode connects the grid of the drain electrode of described 3rd PMOS and the grid of described first NMOS tube and drain electrode and described second NMOS tube, and source electrode meets supply voltage VCC;
The grid of described 5th PMOS and drain electrode are connected together the grid of the grid that connects described first PMOS again and described 4th PMOS and the grid of described 6th PMOS and the drain electrode of described second NMOS tube, and source electrode meets supply voltage VCC;
The grid of described first NMOS tube and the drain electrode and the drain electrode of described 4th PMOS and the grid of described second NMOS tube that connect described 3rd PMOS again of being connected together that drain, source ground;
The grid of described second NMOS tube connects the drain electrode of described 3rd PMOS and the drain electrode of described 4th PMOS and the grid of described first NMOS tube and drain electrode, drain electrode connects the grid of the grid of described first PMOS and the grid of described 4th PMOS and described 5th PMOS and the grid of drain electrode and described 6th PMOS, and source electrode connects the drain electrode of described 3rd NMOS tube;
The grid of described 3rd NMOS tube meets supply voltage VCC, and drain electrode connects the source electrode of described second NMOS tube, and source electrode connects one end of described first resistance;
The source electrode of the 3rd NMOS tube described in one termination of described first resistance, other end ground connection;
The grid of described 6th PMOS connects the grid of the grid of described first PMOS and the grid of described 4th PMOS and described 5th PMOS and the drain electrode of drain electrode and described second NMOS tube, and drain as current output terminal IOUT, source electrode meets supply voltage VCC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520449218.5U CN204719588U (en) | 2015-06-24 | 2015-06-24 | A kind of temperature independent current source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520449218.5U CN204719588U (en) | 2015-06-24 | 2015-06-24 | A kind of temperature independent current source |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204719588U true CN204719588U (en) | 2015-10-21 |
Family
ID=54318566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520449218.5U Expired - Fee Related CN204719588U (en) | 2015-06-24 | 2015-06-24 | A kind of temperature independent current source |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204719588U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107291136A (en) * | 2016-04-11 | 2017-10-24 | 成都锐成芯微科技股份有限公司 | Low-power dissipation power supply power supply circuit |
-
2015
- 2015-06-24 CN CN201520449218.5U patent/CN204719588U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107291136A (en) * | 2016-04-11 | 2017-10-24 | 成都锐成芯微科技股份有限公司 | Low-power dissipation power supply power supply circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151021 Termination date: 20160624 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |