CN204721044U - With the battery charger of current limiting - Google Patents
With the battery charger of current limiting Download PDFInfo
- Publication number
- CN204721044U CN204721044U CN201520420343.3U CN201520420343U CN204721044U CN 204721044 U CN204721044 U CN 204721044U CN 201520420343 U CN201520420343 U CN 201520420343U CN 204721044 U CN204721044 U CN 204721044U
- Authority
- CN
- China
- Prior art keywords
- pmos
- resistance
- nmos tube
- grid
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a kind of battery charger with current limiting.Battery charger with current limiting comprises the first comparator, the first NMOS tube, the first operational amplifier, the first PMOS, the second NMOS tube, the first resistance, the second resistance and the second PMOS.The battery charger of the band current limiting utilizing the utility model to provide can carry out current limliting to rechargeable battery electric current.
Description
Technical field
The utility model relates to battery charger, refers more particularly to the battery charger of band current limiting.
Background technology
In battery charging process, electric current is crossed conference and battery is burnt out or aging quickening, devises the battery charger of band current limiting for this reason.
Summary of the invention
The utility model aims to provide a kind of battery charger with current limiting.
With the battery charger of current limiting, comprise the first comparator, the first NMOS tube, the first operational amplifier, the first PMOS, the second NMOS tube, the first resistance, the second resistance and the second PMOS:
The positive input termination reference voltage V REF2 of described first comparator, one end of the second resistance described in negative input termination and the source electrode of described second PMOS, export the grid of the first NMOS tube described in termination;
The grid of described first NMOS tube connects the output of described first comparator, and drain electrode meets reference voltage V REF1, source ground;
The positive input termination reference voltage V REF1 of described first operational amplifier, one end of the first resistance described in negative input termination and the source electrode of described second NMOS tube;
Connect the grid of described second PMOS and the drain electrode of described second NMOS tube together with the grid of described first PMOS connects with drain electrode, source electrode meets power supply VCC;
The grid of described second NMOS tube connects the output of described first operational amplifier, drain electrode connects the grid of described first PMOS and the grid of drain electrode and described second PMOS, and source electrode connects one end of described first resistance and the negative input end of described first operational amplifier;
The negative input end of the first operational amplifier described in one termination of described first resistance and the source electrode of described second NMOS tube, other end ground connection;
One termination power VCC of described second resistance, the negative input end of the first comparator described in another termination and the source electrode of described second PMOS;
The grid of described second PMOS connects the grid of described first PMOS and the drain electrode of drain electrode and described second NMOS tube, and source electrode connects one end of described second resistance and the negative input end of described first comparator, and drain electrode connects battery.
Described first operational amplifier and described second NMOS tube form follower, described first ohmically voltage is reference voltage V REF1, described first ohmically electric current equals the resistance value of reference voltage V REF1 divided by described first resistance, this electric current is exactly I1, and then produce I2 to described second pmos current by described first PMOS image current, adjustment electric current I 2 can be carried out by regulating the ratio of the breadth length ratio of described first PMOS and the breadth length ratio of described second PMOS; Electric current I 2 pairs of batteries charge; Described second ohmically electric current is consistent with charging current I2, the situation of reflection charging current I2; When charging current I2 is excessive, just increase in described second ohmically pressure drop, the source voltage of described second PMOS just reduces, when this voltage be reduced to be less than reference voltage V REF2 time, compare by the first comparator the output producing high level and control conducting is carried out to described first NMOS tube, the reference voltage V REF1 of the positive input termination being connected to the first operational amplifier is dragged down, so just make to reduce at described first ohmically voltage, electric current I 1 reduces, and charging current I2 also just reduces.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the battery charger of band current limiting of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model content is further illustrated.
With the battery charger of current limiting, as shown in Figure 1, the first comparator 101, first NMOS tube 102, first operational amplifier 103, first PMOS 104, second NMOS tube 105, first resistance 106, second resistance 107 and the second PMOS 108 is comprised:
The positive input termination reference voltage V REF2 of described first comparator 101, one end of the second resistance 107 described in negative input termination and the source electrode of described second PMOS 108, export the grid of the first NMOS tube 102 described in termination;
The grid of described first NMOS tube 102 connects the output of described first comparator 101, and drain electrode meets reference voltage V REF1, source ground;
The positive input termination reference voltage V REF1 of described first operational amplifier 103, one end of the first resistance 106 described in negative input termination and the source electrode of described second NMOS tube 105;
Connect the grid of described second PMOS 108 and the drain electrode of described second NMOS tube 105 together with the grid of described first PMOS 104 connects with drain electrode, source electrode meets power supply VCC;
The grid of described second NMOS tube 105 connects the output of described first operational amplifier 103, drain electrode connects the grid of described first PMOS 104 and the grid of drain electrode and described second PMOS 108, and source electrode connects one end of described first resistance 106 and the negative input end of described first operational amplifier 103;
The negative input end of the first operational amplifier 103 described in one termination of described first resistance 106 and the source electrode of described second NMOS tube 105, other end ground connection;
One termination power VCC of described second resistance 107, the negative input end of the first comparator 101 described in another termination and the source electrode of described second PMOS 108;
The grid of described second PMOS 108 connects the grid of described first PMOS 104 and the drain electrode of drain electrode and described second NMOS tube 105, and source electrode connects one end of described second resistance 107 and the negative input end of described first comparator 101, and drain electrode connects battery.
Described first operational amplifier 103 and described second NMOS tube 105 form follower, described first ohmically voltage is reference voltage V REF1, electric current on described first resistance 106 equals the resistance value of reference voltage V REF1 divided by described first resistance 106, this electric current is exactly I1, and then produce I2 to described second PMOS 108 electric current by described first PMOS 104 image current, adjustment electric current I 2 can be carried out by regulating the ratio of the breadth length ratio of described first PMOS 104 and the breadth length ratio of described second PMOS 108; Electric current I 2 pairs of batteries charge; Electric current on described second resistance 107 is consistent with charging current I2, the situation of reflection charging current I2; When charging current I2 is excessive, pressure drop on described second resistance 107 just increases, the source voltage of described second PMOS 108 just reduces, when this voltage be reduced to be less than reference voltage V REF2 time, compare by the first comparator 101 output producing high level and control conducting is carried out to described first NMOS tube 102, the reference voltage V REF1 of the positive input termination being connected to the first operational amplifier 103 is dragged down, the voltage on described first resistance 106 is so just made to reduce, electric current I 1 reduces, and charging current I2 also just reduces.
Claims (1)
1. be with the battery charger of current limiting, it is characterized in that: comprise the first comparator, the first NMOS tube, the first operational amplifier, the first PMOS, the second NMOS tube, the first resistance, the second resistance and the second PMOS;
The positive input termination reference voltage V REF2 of described first comparator, one end of the second resistance described in negative input termination and the source electrode of described second PMOS, export the grid of the first NMOS tube described in termination;
The grid of described first NMOS tube connects the output of described first comparator, and drain electrode meets reference voltage V REF1, source ground;
The positive input termination reference voltage V REF1 of described first operational amplifier, one end of the first resistance described in negative input termination and the source electrode of described second NMOS tube;
Connect the grid of described second PMOS and the drain electrode of described second NMOS tube together with the grid of described first PMOS connects with drain electrode, source electrode meets power supply VCC;
The grid of described second NMOS tube connects the output of described first operational amplifier, drain electrode connects the grid of described first PMOS and the grid of drain electrode and described second PMOS, and source electrode connects one end of described first resistance and the negative input end of described first operational amplifier;
The negative input end of the first operational amplifier described in one termination of described first resistance and the source electrode of described second NMOS tube, other end ground connection;
One termination power VCC of described second resistance, the negative input end of the first comparator described in another termination and the source electrode of described second PMOS;
The grid of described second PMOS connects the grid of described first PMOS and the drain electrode of drain electrode and described second NMOS tube, and source electrode connects one end of described second resistance and the negative input end of described first comparator, and drain electrode connects battery.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520420343.3U CN204721044U (en) | 2015-06-15 | 2015-06-15 | With the battery charger of current limiting |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520420343.3U CN204721044U (en) | 2015-06-15 | 2015-06-15 | With the battery charger of current limiting |
Publications (1)
Publication Number | Publication Date |
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CN204721044U true CN204721044U (en) | 2015-10-21 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201520420343.3U Expired - Fee Related CN204721044U (en) | 2015-06-15 | 2015-06-15 | With the battery charger of current limiting |
Country Status (1)
Country | Link |
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CN (1) | CN204721044U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107346909A (en) * | 2017-05-12 | 2017-11-14 | 南京中感微电子有限公司 | A kind of charging circuit and battery |
-
2015
- 2015-06-15 CN CN201520420343.3U patent/CN204721044U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107346909A (en) * | 2017-05-12 | 2017-11-14 | 南京中感微电子有限公司 | A kind of charging circuit and battery |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151021 Termination date: 20160615 |