CN103490657A - Low-loss-type tri-electrical-level photovoltaic inverter - Google Patents
Low-loss-type tri-electrical-level photovoltaic inverter Download PDFInfo
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- CN103490657A CN103490657A CN201310496758.4A CN201310496758A CN103490657A CN 103490657 A CN103490657 A CN 103490657A CN 201310496758 A CN201310496758 A CN 201310496758A CN 103490657 A CN103490657 A CN 103490657A
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- mosfet pipe
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
Abstract
The invention discloses a low-loss-type tri-electrical-level photovoltaic inverter. The low-loss-type tri-electrical-level photovoltaic inverter comprises an input voltage, a capacitor C1, a capacitor C2, a first Mosfet tube, a second Mosfet tube, a third Mosfet tube, a fourth Mosfet tube, a first triode and a second triode; the first Mosfet tube, the second Mosfet tube, the third Mosfet tube, the fourth Mosfet tube, the first triode and the second triode are respectively connected with a first diode, a second diode, a third diode, a fourth diode, a fifth diode and a sixth diode in parallel. According to the invention, at the output of Vdc/2 and -Vdc/2, only a power device is conducted with the current. When zero electrical level is output, the conduction loss is reduced through a parallel channel formed by four CoolMosfets. Two CoolMosfets in each parallel channel are in reverse serial connection, so that the conduction voltage drop of zero electrical level is reduced.
Description
Technical field
The present invention relates to inverter, relate in particular to low-loss formula three level photovoltaic inverters.
Background technology
The tradition tri-level circuit, it can export three level, with two level circuits, compares and has lower loss, can reduce the harmonic wave of output current simultaneously, reduce the output filter size, as shown in Figure 1, still when circuit output Vdc/2,0, during-Vdc/2, tube current is not positive and negative, and electric current all needs, through two power devices, to have higher conduction loss.
Summary of the invention
The technical problem to be solved in the present invention is traditional positive and negative all needs through two power devices of tri-level circuit electric current, and conduction loss is higher, and a kind of lossy three level photovoltaic inverters are provided for this reason.
Technical scheme of the present invention is: low-loss formula three level photovoltaic inverters, it comprises input voltage, capacitor C 1 and capacitor C 2, it also comprises a Mosfet pipe, the 2nd Mosfet pipe, the 3rd Mosfet pipe and the 4th Mosfet pipe, the source electrode of a described Mosfet pipe is connected with the source electrode of the 2nd Mosfet pipe, the drain electrode of described the 3rd Mosfet pipe is connected with the drain electrode of the 4th Mosfet pipe, the drain electrode of the source electrode of a described Mosfet pipe and the 3rd Mosfet pipe is connected in parallel between capacitor C 1 and capacitor C 2, the drain electrode of described the 2nd Mosfet pipe is connected with the collector electrode of the second triode with the emitter of the first triode respectively, the source electrode of described the 4th Mosfet pipe is connected with the collector electrode of the second triode with the emitter of the first triode respectively, the collector electrode of described the first triode is connected with the positive pole of input voltage, the emitter of described the second triode is connected with the negative pole of input voltage, the collector electrode of the emitter of described the first triode and the second triode is connected with capacitor C 3 by inductance L, a described Mosfet pipe, the 2nd Mosfet pipe, the 3rd Mosfet pipe, the 4th Mosfet pipe, be parallel with respectively the first diode on the first triode and the second triode, the second diode, the 3rd diode, the 4th diode, the 5th diode and the 6th diode, the anodic bonding of described the first diode is between capacitor C 1 and capacitor C 2 and ground connection, its negative electrode is connected with the negative electrode of the second diode, the negative electrode of the anode of the second diode and the 4th diode be connected configuration node and this node respectively with the first triode, the second triode is connected with inductance L, the anode of described the 3rd diode is connected with the anode of the 4th diode.
A Mosfet pipe described in such scheme, the 2nd Mosfet pipe, the 3rd Mosfet pipe and the 4th Mosfet pipe are the N channel-types.
A Mosfet pipe described in such scheme, the 2nd Mosfet pipe, the 3rd Mosfet pipe and the 4th Mosfet pipe are the CoolMosfet pipes.
The invention has the beneficial effects as follows that it is at output Vdc/2 ,-Vdc/2, only have a power device On current.The more important thing is, when the output zero level, by the parallel port formed by four CoolMosfet, reduce conduction loss.Simultaneously, two CoolMosfet in each parallel port are differential concatenation, have avoided using the body diode of CoolMosfet, thereby have greatly reduced the conduction voltage drop of zero level.
The accompanying drawing explanation
Fig. 1 is traditional three level topological diagrams;
Fig. 2 is topological diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
As shown in Figure 2, the present invention includes input voltage, capacitor C 1 and capacitor C 2, it also comprises a Mosfet pipe, the 2nd Mosfet pipe, the 3rd Mosfet pipe and the 4th Mosfet pipe, the source electrode of a described Mosfet pipe is connected with the source electrode of the 2nd Mosfet pipe, the drain electrode of described the 3rd Mosfet pipe is connected with the drain electrode of the 4th Mosfet pipe, the drain electrode of the source electrode of a described Mosfet pipe and the 3rd Mosfet pipe is connected in parallel between capacitor C 1 and capacitor C 2, the drain electrode of described the 2nd Mosfet pipe is connected with the collector electrode of the second triode with the emitter of the first triode respectively, the source electrode of described the 4th Mosfet pipe is connected with the collector electrode of the second triode with the emitter of the first triode respectively, the collector electrode of described the first triode is connected with the positive pole of input voltage, the emitter of described the second triode is connected with the negative pole of input voltage, the collector electrode of the emitter of described the first triode and the second triode is connected with capacitor C 3 by inductance L, a described Mosfet pipe, the 2nd Mosfet pipe, the 3rd Mosfet pipe, the 4th Mosfet pipe, be parallel with respectively the first diode on the first triode and the second triode, the second diode, the 3rd diode, the 4th diode, the 5th diode and the 6th diode, the anodic bonding of described the first diode is between capacitor C 1 and capacitor C 2 and ground connection, its negative electrode is connected with the negative electrode of the second diode, the negative electrode of the anode of the second diode and the 4th diode be connected configuration node and this node respectively with the first triode, the second triode is connected with inductance L, the anode of described the 3rd diode is connected with the anode of the 4th diode.
Operation principle of the present invention is as follows: suppose that power factor is 1, when positive half cycle, circuit can export 0 and Vdc/2, four Mosfet pipes in the middle of opening, and while closing other switch, circuit output 0.Now, electric current process S1c-1 ,-2, S2c-1 ,-2 flow to load.Wherein, S1c-1 ,-2 is reverse-conduction current, and S2c-1 ,-2 is the forward conduction electric current.When closing S2c-1 ,-2 two switches, maintain S1c-1, and-2 two switches are open-minded, and while opening S1, the positive pole that electric current is input voltage through S1 from positive bus-bar flows to load simultaneously, and load is in parallel with capacitor C 3.
Four Mosfet pipes in the present invention can be N channel-type field effect transistor, are preferably the CoolMosfet pipe, the area of wafer, thickness is all little than common process, and conducting resistance only has 1/10 of traditional handicraft, and RDS is less, switching speed is faster, and distributed constant is less, and VTH is little.
The above is exemplarily described the present invention by reference to the accompanying drawings; obviously specific implementation of the present invention is not subject to the restrictions described above; as long as adopted the improvement of the various unsubstantialities that method of the present invention design and technical scheme carry out; or without improving, design of the present invention and technical scheme are directly applied to other occasion, all within protection scope of the present invention.
Claims (3)
1. low-loss formula three level photovoltaic inverters, it comprises input voltage, capacitor C 1 and capacitor C 2, it is characterized in that it also comprises a Mosfet pipe, the 2nd Mosfet pipe, the 3rd Mosfet pipe and the 4th Mosfet pipe, the source electrode of a described Mosfet pipe is connected with the source electrode of the 2nd Mosfet pipe, the drain electrode of described the 3rd Mosfet pipe is connected with the drain electrode of the 4th Mosfet pipe, the drain electrode of the source electrode of a described Mosfet pipe and the 3rd Mosfet pipe is connected in parallel between capacitor C 1 and capacitor C 2, the drain electrode of described the 2nd Mosfet pipe is connected with the collector electrode of the second triode with the emitter of the first triode respectively, the source electrode of described the 4th Mosfet pipe is connected with the collector electrode of the second triode with the emitter of the first triode respectively, the collector electrode of described the first triode is connected with the positive pole of input voltage, the emitter of described the second triode is connected with the negative pole of input voltage, the collector electrode of the emitter of described the first triode and the second triode is connected with capacitor C 3 by inductance L, a described Mosfet pipe, the 2nd Mosfet pipe, the 3rd Mosfet pipe, the 4th Mosfet pipe, be parallel with respectively the first diode on the first triode and the second triode, the second diode, the 3rd diode, the 4th diode, the 5th diode and the 6th diode, the anodic bonding of described the first diode is between capacitor C 1 and capacitor C 2 and ground connection, its negative electrode is connected with the negative electrode of the second diode, the negative electrode of the anode of the second diode and the 4th diode be connected configuration node and this node respectively with the first triode, the second triode is connected with inductance L, the anode of described the 3rd diode is connected with the anode of the 4th diode.
2. low-loss formula three level photovoltaic inverters as claimed in claim 1, is characterized in that a described Mosfet pipe, the 2nd Mosfet pipe, the 3rd Mosfet pipe and the 4th Mosfet pipe are the N channel-types.
3. low-loss formula three level photovoltaic inverters as claimed in claim 1 or 2, is characterized in that a described Mosfet pipe, the 2nd Mosfet pipe, the 3rd Mosfet pipe and the 4th Mosfet pipe are the CoolMosfet pipes.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310496758.4A CN103490657A (en) | 2013-10-22 | 2013-10-22 | Low-loss-type tri-electrical-level photovoltaic inverter |
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| CN201310496758.4A CN103490657A (en) | 2013-10-22 | 2013-10-22 | Low-loss-type tri-electrical-level photovoltaic inverter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105024573A (en) * | 2015-07-03 | 2015-11-04 | 上海交通大学 | CoolMosfet T-type three-level topological circuit and inverter |
| CN107046378A (en) * | 2017-04-06 | 2017-08-15 | 哈尔滨理工大学 | A kind of two-way Z sources three-level inverter |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769399A (en) * | 2012-06-29 | 2012-11-07 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level inverter circuit and inverter |
| CN203193538U (en) * | 2013-03-20 | 2013-09-11 | 上海谐振电气科技有限公司 | Three-level inverter for new energy |
| CN203491924U (en) * | 2013-10-22 | 2014-03-19 | 安徽金峰新能源股份有限公司 | Low-loss three-level photovoltaic inverter |
-
2013
- 2013-10-22 CN CN201310496758.4A patent/CN103490657A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769399A (en) * | 2012-06-29 | 2012-11-07 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level inverter circuit and inverter |
| CN203193538U (en) * | 2013-03-20 | 2013-09-11 | 上海谐振电气科技有限公司 | Three-level inverter for new energy |
| CN203491924U (en) * | 2013-10-22 | 2014-03-19 | 安徽金峰新能源股份有限公司 | Low-loss three-level photovoltaic inverter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105024573A (en) * | 2015-07-03 | 2015-11-04 | 上海交通大学 | CoolMosfet T-type three-level topological circuit and inverter |
| CN107046378A (en) * | 2017-04-06 | 2017-08-15 | 哈尔滨理工大学 | A kind of two-way Z sources three-level inverter |
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Application publication date: 20140101 |