JP2010135981A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit capable of setting the threshold of an input signal for changing the voltage of an output signal into an optional value. <P>SOLUTION: A voltage division circuit 9 is configured of resistors R1 and R2 connected in series between an input terminal 2 of the input signal Sin and an input terminal 3 of a reference potential. A transistor T1 is turned on/off on the basis of a detection voltage Vdet output from the voltage division circuit 9. A transistor T2 and a resistor R5 of an output circuit 8 are connected in series between a power line 10 for supplying a power supply voltage VDDB and a ground line 4. The transistor T2 is turned on/off in accordance with turning-on/off of the transistor T1 and outputs the power supply voltage EDDB or an output signal Sout of 0V from the collector. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a level shift circuit that shifts the level of an input signal and outputs it to a circuit that operates under a different power supply system.

For example, in an in-vehicle electronic control device, a digital circuit such as a CPU that operates with a relatively low power supply voltage and an interface circuit with an external device that operates with a relatively high power supply voltage are mixed. A level shift circuit is required to transmit a signal such as a logic signal between circuits operating under such different power supply systems. This level shift circuit is composed of, for example, a plurality of MOS transistors, and changes the voltage value of the output signal depending on whether or not the voltage value of the input signal exceeds a predetermined threshold (for example, Patent Document 1). reference).
Japanese Patent Laid-Open No. 10-028044

  However, when a logic signal is transmitted between the circuits via the level shift circuit of the conventional configuration, the following problems arise. That is, in the conventional level shift circuit, the threshold value is set by the threshold voltage between the gate and source of the MOS transistor. Therefore, this threshold value is determined by the element characteristics of the MOS transistor and cannot be set to an arbitrary value.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a level shift circuit capable of setting a threshold value of an input signal for changing a voltage value of an output signal to an arbitrary value. There is.

  According to the first aspect, the resistor interposed between the input terminal for inputting the input signal output from the circuit operating at the first power supply voltage and the reference terminal for inputting the reference potential is provided. The voltage dividing circuit has a voltage output according to the voltage value of the input signal. The output circuit sets the voltage value of the second power supply potential by turning on and off the switching element interposed between the power supply line for supplying the second power supply potential and the reference terminal based on the divided voltage. A signal having a voltage value of a reference potential or a reference potential is output. The threshold for the voltage value of the input signal for determining the voltage value of the output signal can be determined by setting the voltage dividing ratio in the voltage dividing circuit. Therefore, according to the configuration of this means, the threshold value can be set to an arbitrary value by setting the resistance value of the resistor constituting the voltage dividing circuit.

  According to the second aspect of the present invention, the voltage dividing ratio changing means for changing the voltage dividing ratio of the voltage dividing circuit according to the on / off of the switching element is provided. As a result, the threshold value when the voltage value of the input signal increases can be made different from the threshold value when the voltage value of the input signal decreases. That is, it is possible to give hysteresis to the detection operation of the input signal, and even when an input signal on which noise is superimposed is input, a signal having the same logic as the input signal can be output.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIG.
FIG. 1 schematically shows the electrical configuration of the level shift circuit. The level shift circuit 1 is formed, for example, in a semiconductor integrated circuit device (IC) mounted on a control board in an electronic control unit (Electronic Control Unit) of a vehicle. Although not shown, two independent power supply ICs constituting, for example, a series regulator are mounted on the control board. These two power supply ICs are supplied with a battery voltage from a vehicle-mounted battery, generate a power supply voltage VDDA and a power supply voltage VDDB, respectively, and supply them to the control IC.

  In this control IC, the power supply voltage VDDA is 3.3 V, for example, and is mainly used in a digital circuit such as a CPU, and the power supply voltage VDDB is, for example, 5 V, and is mainly used in an interface circuit with an external device. . For this reason, the control IC requires the level shift circuit 1 for converting from a 3.3V system logic level to a 5V system logic level. In the present embodiment, the power supply voltage VDDA and the power supply voltage VDDB correspond to the first power supply voltage and the second power supply voltage, respectively.

  An input signal Sin generated in a logic circuit (digital circuit) operating under the power supply voltage VDDA is applied to the level shift circuit 1 via the input terminal 2. The input terminal 3 (corresponding to the reference terminal) is an input terminal for the reference potential GND (0 V) and is connected to the ground line 4. These input terminals 2 and 3 are connected to the logic circuit and the like. The level shift circuit 1 outputs an output signal Sout obtained by level shifting the input signal Sin via the output terminal 5. The output terminal 6 is a reference potential output terminal and is connected to the ground line 4. These output terminals 5 and 6 are connected to the above-described interface circuit operating under the power supply voltage VDDB.

  The level shift circuit 1 includes an input detection circuit 7 and an output circuit 8. The input detection circuit 7 includes an NPN transistor T1 and resistors R1 to R3. Between the input terminals 2 and 3, resistors R1 and R2 are connected in series. A voltage dividing circuit 9 is constituted by a series circuit of these resistors R1 and R2. The interconnection node Na between the resistors R1 and R2 is connected to the base of the transistor T1. The emitter of the transistor T2 is connected to the ground line 4, and the collector is connected to one terminal of the resistor R3. The other terminal of the resistor R3 is an output node of the input detection circuit 7.

  The resistance values of the resistors R1 and R2 are set so that the voltage Vdet of the node Na coincides with the base-emitter forward voltage VF of the transistor T1 when the voltage value of the input signal Sin is about 50% of the power supply voltage VDDA. Has been. In this embodiment, the threshold voltage Vth is about 50% of the power supply voltage VDDA. That is, the transistor T1 turns on when the voltage value of the input signal Sin is equal to or higher than the threshold voltage Vth, and turns off when it is lower than the threshold voltage Vth.

  The output circuit 8 outputs an output signal Sout whose voltage value changes according to the on / off state of the transistor T1 of the input detection circuit 7. The output circuit 8 includes a PNP transistor T2 (corresponding to a switching element) and resistors R4 and R5. An output node of the input detection circuit 7 is connected to the power supply line 10 via a resistor R4. A power supply voltage VDDB is applied between the power supply line 10 and the ground line 4. A transistor T2 and a resistor R5 are connected in series between the power supply line 10 and the ground line 4. The base of the transistor T 2 is connected to the output node of the input detection circuit 7, and the collector is connected to the output terminal 5.

Next, the operation of the level shift circuit 1 will be described.
When the voltage value of the input signal Sin is 0V (L level), the detection voltage Vdet is 0V, so the transistor T1 is off. As a result, since the potential of the output node of the input detection circuit 7 becomes substantially equal to the power supply voltage VDDB, the transistor T2 is also turned off. Therefore, the output signal Sout output from the output terminal 5 is approximately 0V.

  Subsequently, when the voltage value of the input signal Sin increases and reaches the threshold voltage Vth, the detection voltage Vdet coincides with the forward voltage VF, so that the transistor T1 is turned on. As a result, the potential of the output node of the input detection circuit 7 becomes almost 0 V, so that the transistor T2 is also turned on. Accordingly, the output signal Sout output from the output terminal 5 is substantially equal to the power supply voltage VDDB.

  This state continues until the voltage value of the input signal Sin drops below the threshold voltage Vth. Therefore, when the voltage value of the input signal Sin is the power supply voltage VDDA (H level), the output signal Sout output from the output terminal 5 is substantially equal to the power supply voltage VDDB. Thereafter, when the voltage value of the input signal Sin becomes lower than the threshold voltage Vth, the detection voltage Vdet is lower than the forward voltage VF, so that the transistor T1 is turned off. As a result, the output signal Sout output from the output terminal 5 becomes approximately 0V.

  As described above, the level shift circuit 1 of the present embodiment has the L level (0V to VDDA) where the voltage value of the input signal Sin output from the circuit operating under the power supply voltage VDDA is less than the threshold voltage Vth. In the case of a voltage less than 50%), an output signal Sout having an L level logic (0 V) in a circuit operating under the power supply voltage VDDB is output. On the other hand, when the voltage value of the input signal Sin is H level equal to or higher than the threshold voltage Vth (voltage 50% or higher of VDDA), the logic of H level (power voltage VDDB) in the circuit operating under the power supply voltage VDDB The output signal Sout is output.

  The threshold voltage Vth for the input signal Sin for determining the voltage value (voltage level, logic level) of the output signal Sout is set by the voltage dividing ratio by the voltage dividing circuit 9, that is, the resistance ratio of the resistors R1 and R2. Yes. Therefore, according to the configuration of the present embodiment, the threshold voltage Vth can be set to an arbitrary value by setting the resistance values of the resistors R1 and R2.

  In the above description with reference to FIG. 1, the input signal Sin having a logic level (voltage value) in a circuit operating under a relatively low power supply voltage VDDA (3.3 V) is level-shifted to obtain a relatively high power supply voltage VDDB ( The case where the output signal Sout having the logic level (voltage value) in the circuit operating under 5V) has been described. The level shift circuit 1 of this embodiment is not limited to such a level shift from a low voltage to a high voltage, but can also perform a level shift from a high voltage to a low voltage. That is, the input signal Sin having a logic level in a circuit operating under the power supply voltage VDDB can be level-shifted to an output signal Sout having a logic level in a circuit operating under the power supply voltage VDDA.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a diagram corresponding to FIG. 1 showing the electrical configuration of the level shift circuit of the present embodiment. Note that the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The level shift circuit 21 is different from the level shift circuit 1 of the first embodiment in that an input detection circuit 22 is provided instead of the input detection circuit 7.

  The input detection circuit 22 includes a PNP transistor T21 and a resistor R21. The resistor R21 is connected so as to be interposed between the input terminal 2 and the resistor R1. The emitter and collector of the transistor T21 are connected to both terminals of the resistor R21. The base of the transistor T21 is connected to the other terminal of the resistor R3. In the present embodiment, the voltage dividing circuit 23 is configured by a series circuit of resistors R21, R1, and R2. The transistor T21 corresponds to a voltage dividing ratio changing unit. With such a configuration, the transistor T21 is turned on when the transistor T1 is turned on and turned off when the transistor T1 is turned off. And the detection voltage Vdet changes as follows according to ON / OFF of the transistor T21.

That is, when the transistor T21 is on, both terminals of the resistor R21 are short-circuited, and the voltage Vdet (on) at this time is expressed by the following equation (1). However, in the expression (1), the voltage value of the input signal Sin is expressed as Sin as it is, and the resistance values of the resistors R1 and R2 are expressed as R1 and R2 as they are.
Vdet (on) = Sin · R2 / (R1 + R2) (1)

On the other hand, when the transistor T21 is off, the resistors R21, R1, and R2 are connected in series between the input terminals 2 and 3. The voltage Vdet (off) at this time is expressed by the following equation (2). However, in the equation (2), the resistance value of the resistor R21 is expressed as R21 as it is.
Vdet (off) = Sin · R2 / (R21 + R1 + R2) (2)

  The resistance values of the resistors R21, R1, and R2 are such that when the voltage value of the input signal Sin is about 75% of the power supply voltage VDDA, the detection voltage Vdet (on) matches the forward voltage VF of the transistor T1, and the power supply voltage VDDA The detection voltage Vdet (off) is set so as to coincide with the forward voltage VF at about 25%. In this embodiment, a voltage value of about 75% of the power supply voltage VDDA is set as the threshold voltage Vth (on), and a voltage value of about 25% of the power supply voltage VDDA is set as the threshold voltage Vth (off). That is, the transistor T1 is turned on when the voltage value of the input signal Sin is equal to or higher than the threshold voltage Vth (on) in the off state, and the voltage value of the input signal Sin is threshold voltage Vth (off) in the on state. Turns off when less than.

Next, the operation of the level shift circuit 21 will be described with reference to FIG.
FIG. 2 shows voltage waveforms at various parts of the level shift circuit 21. Each waveform represents (a) input signal Sin, (b) detection voltage Vdet, and (c) output signal Sout in order from the top. When the voltage value of the input signal Sin is 0V (L level) (time t0), the transistor T1 is off because the detection voltage Vdet is 0V. As a result, the potential of the output node of the input detection circuit 22 becomes substantially equal to the power supply voltage VDDB, so that the transistor T2 is also turned off. Therefore, the output signal Sout output from the output terminal 5 is approximately 0V.

  Subsequently, when the voltage value of the input signal Sin increases and reaches the threshold voltage Vth (on) (time t1), the detection voltage Vdet matches the forward voltage VF, so that the transistor T1 is turned on. As a result, the potential of the output node of the input detection circuit 22 becomes almost 0 V, so that the transistor T2 is turned on. Therefore, the output signal Sout output from the output terminal 5 rises from 0V toward the power supply voltage VDDB. At this time, since the transistor T21 is turned on, the voltage dividing ratio in the voltage dividing circuit 23 is changed, and the detection voltage Vdet increases.

  This state continues until the voltage value of the input signal Sin drops below the threshold voltage Vth (off). Therefore, when the voltage value of the input signal Sin is the power supply voltage VDDA (H level) (time t2 to t3), the output signal Sout output from the output terminal 5 is substantially equal to the power supply voltage VDDB. Thereafter, when the voltage value of the input signal Sin becomes less than the threshold voltage Vth (off) (time t4), the detection voltage Vdet is lower than the forward voltage VF, so that the transistor T1 is turned off. As a result, the output signal Sout output from the output terminal 5 decreases from the power supply voltage VDDB toward 0V. At this time, since the transistor T21 is turned off, the voltage dividing ratio in the voltage dividing circuit 23 is changed and the detection voltage Vdet is lowered.

  As described above, the level shift circuit 21 of the present embodiment is a circuit that operates under the power supply voltage VDDB when the voltage value of the input signal Sin output from the circuit that operates under the power supply voltage VDDA is L level. An output signal Sout having an L level logic (0 V) is output. On the other hand, when the input signal Sin is at the H level, an output signal Sout having an H level logic (power supply voltage VDDB) in the circuit operating under the power supply voltage VDDB is output.

  Also with the level shift circuit 21 having such a configuration, the same operations and effects as those of the first embodiment can be obtained. Further, the input detection circuit 22 is configured to have hysteresis in the detection operation of the input signal Sin (the generation operation of the detection voltage Vdet). As a result, even if noise is superimposed on the input signal Sin in the path until it is supplied to the level shift circuit 21, it is less likely to be affected. That is, even when the input signal Sin on which noise is superimposed is input, the output signal Sout having the same logic as that of the input signal Sin can be output. Further, the hysteresis can be set to an arbitrary value by setting the resistance values of the resistors R21, R1, and R2.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram corresponding to FIG. 1 showing the electrical configuration of the level shift circuit of the present embodiment. Note that the same parts as those in the above embodiments are denoted by the same reference numerals and description thereof is omitted. The level shift circuit 31 is different from the level shift circuit 21 of the second embodiment in that an N channel type MOS transistor M1 is provided instead of the NPN type transistor T1, and the PNP type transistors T2 and T21 are replaced. The difference is that P-channel MOS transistors M2 and M21 are provided.

  In the present embodiment, the MOS transistor M2 corresponds to a switching element, and the MOS transistor M21 corresponds to a voltage dividing ratio changing unit. As described above, the same operation and effect as in the second embodiment can be obtained also by the configuration of the present embodiment in which the transistors for configuring the level shift circuit are changed from bipolar transistors to MOS transistors.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a diagram corresponding to FIG. 1 showing the electrical configuration of the level shift circuit of the present embodiment. Note that the same parts as those in the above embodiments are denoted by the same reference numerals and description thereof is omitted. The level shift circuit 41 is different from the level shift circuit 21 of the second embodiment in that a diode D41 is provided instead of the resistor R21. In the present embodiment, the voltage dividing circuit 42 is configured by a series circuit of a diode D41 and resistors R1 and R2.

In the level shift circuit 41 having such a configuration, when the transistor T21 is on, both terminals of the diode D41 are short-circuited, and the voltage Vdet (on) at this time is the same as in the second embodiment. It is represented by the formula (1). On the other hand, when the transistor T21 is off, the diode D41 and the resistors R1 and R2 are connected in series between the input terminals 2 and 3. The voltage Vdet (off) at this time is expressed by the following equation (3). However, in the expression (3), the forward voltage of the diode D41 is represented by VF.
Vdet (off) = (Sin−VF) · R2 / (R1 + R2) (3)

  The resistance values of the resistors R1 and R2 are such that when the voltage value of the input signal Sin is about 75% of the power supply voltage VDDA, the detection voltage Vdet (on) matches the forward voltage VF of the transistor T1, and about 25 of the power supply voltage VDDA. %, The detection voltage Vdet (off) is set to coincide with the forward voltage VF. Accordingly, in the level shift circuit 41, the transistor T1 is turned on and off in the same manner as the level shift circuit 21 of the second embodiment, and an output signal Sout corresponding to this is output. Even with such a configuration, the same operations and effects as those of the second embodiment can be obtained.

(Fifth embodiment)
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram corresponding to FIG. 1 showing the electrical configuration of the level shift circuit of the present embodiment. Note that the same parts as those in the above embodiments are denoted by the same reference numerals and description thereof is omitted. The level shift circuit 51 is different from the level shift circuit 21 of the second embodiment in that a Zener diode D51 is provided instead of the resistor R21. In the present embodiment, the voltage dividing circuit 52 is configured by a series circuit of a Zener diode D51 and resistors R1 and R2.

When the transistor T21 is on, the level shift circuit 51 having such a configuration is in a state where both terminals of the Zener diode D51 are short-circuited, and the voltage Vdet (on) at this time is the same as in the second embodiment. It is represented by the above formula (1). On the other hand, when the transistor T21 is off, a Zener diode D51 and resistors R1 and R2 are connected in series between the input terminals 2 and 3. The voltage Vdet (off) at this time is expressed by the following equation (4). However, in the equation (4), the Zener voltage of the Zener diode D51 is represented by Vz.
Vdet (off) = (Sin−Vz) · R2 / (R1 + R2) (4)

  The resistance values of the resistors R1 and R2 are such that when the voltage value of the input signal Sin is about 75% of the power supply voltage VDDA, the detection voltage Vdet (on) matches the forward voltage VF of the transistor T1, and about 25 of the power supply voltage VDDA. %, The detection voltage Vdet (off) is set to coincide with the forward voltage VF. Accordingly, in the level shift circuit 51, the transistor T1 is turned on and off in the same manner as the level shift circuit 21 of the second embodiment, and an output signal Sout corresponding to this is output. Even with such a configuration, the same operations and effects as those of the second embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The values of the threshold voltages Vth, Vth (on), and Vth (off) can be changed as appropriate. The transistor T1 may be changed to a PNP type, and the transistors T2 and T21 may be changed to an NPN type. Further, the MOS transistor M1 may be changed to a P-channel type, and the MOS transistors M2 and M21 may be changed to an N-channel type. In that case, the connection form of each transistor may be changed so that the on / off operation is performed as before the change. The first power supply voltage and the second power supply voltage are not limited to the power supply voltage VDDA and the power supply voltage VDDB.

The level shift circuit of the present invention can be applied to applications other than the use of converting a signal having a logic level in a digital circuit into a signal having a logic level in an interface circuit. For example, it can also be used for the purpose of converting a signal output from a circuit operating under a battery voltage supplied from a vehicle-mounted battery into a signal having a logic level in a logic circuit inside the IC. That is, the signal output from a circuit operating under a high power supply voltage is converted to a signal of a circuit operating under a low power supply voltage (for example, an input buffer), or output from a circuit operating under a low power supply voltage The present invention can be applied to all applications (for example, a driver circuit) for converting a generated signal into a signal of a circuit that operates under a high power supply voltage.
The level shift circuit of the present invention is not limited to an on-vehicle electronic control device, but can be applied to other devices that require signal transmission between circuits operating under different power supply systems.

FIG. 1 is an electrical configuration diagram of a level shift circuit showing a first embodiment of the present invention. FIG. 1 equivalent diagram showing a second embodiment of the present invention Diagram showing the voltage waveform of each part FIG. 1 equivalent view showing a third embodiment of the present invention FIG. 1 equivalent view showing a fourth embodiment of the present invention FIG. 1 equivalent view showing a fifth embodiment of the present invention

Explanation of symbols

  In the drawings, 1, 21, 31, 41 and 51 are level shift circuits, 2 is an input terminal, 3 is an input terminal (reference terminal), 8 is an output circuit, 9, 23, 42 and 52 are voltage dividing circuits, 10 is The power supply line, M2 is a MOS transistor (switching element), M21 is a MOS transistor (voltage division ratio changing means), R1 and R2 are resistors, T2 is a transistor (switching element), and T21 is a transistor (voltage division ratio changing means).

Claims (2)

An input signal output from a circuit operating with a first power supply voltage between the first power supply potential and the reference potential is input between a second power supply potential different from the first power supply potential and the reference potential. A level shift circuit for converting a level into a signal of a circuit operating with a second power supply voltage,
A voltage dividing circuit having a resistance interposed between an input terminal for inputting the input signal and a reference terminal for inputting the reference potential;
A switching element that is interposed between a power supply line for supplying the second power supply potential and the reference terminal and that is turned on / off based on a divided voltage output from the voltage dividing circuit; And a level shift circuit comprising: an output circuit that outputs a signal having the second power supply potential or a signal having the reference potential.   2. The level shift circuit according to claim 1, further comprising a voltage dividing ratio changing means for changing a voltage dividing ratio of the voltage dividing circuit in accordance with on / off of the switching element.

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