JP2006086905A - Slew rate adjusting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output buffer circuit having a slew rate adjusting circuit which is not influenced by an external resistor. <P>SOLUTION: Since the output of the circuit can be changed while controlling the potential of a pull-up resistor or pull-down resistor by applying a bias to the gate of an output transistor other than an output transistor changing at a constant slew rate to turn it on, out of a PMOS transistor 10 and an NMOS transistor 11 constituting output transistors of the slew rate adjusting circuit, the output can be changed from its an "H" level to an "L" level and from the "L" level to the "H" level at the constant slew rate, even if the pull-up resistor or the pull-down resistor is connected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an output buffer circuit mounted on a semiconductor integrated circuit.

In the USB (Universal Serial Bus) standard, which is a communication standard for peripheral devices of personal computers, a slew rate control type output buffer circuit is used.
(Patent Document 1) describes a slew rate control type output buffer circuit shown in FIG. This is a circuit for outputting an output signal corresponding to the level of the internal input terminals PEN, NEN to the output terminal 1, and is formed by PMOS transistors 12, 10, 23, a current source 4, a capacitor 14, and the like, and the internal input terminals PEN, When NEN changes from “H” level to “L” level, the first NMOS transistor 11 is turned on so that the potential of the output terminal 1 is changed from “H” level to “L” level at a constant slew rate. The control circuit, NMOS transistors 13 and 6, 22 and current source 7 and capacitor 14 are formed. When the internal input terminals PEN and NEN are changed from "L" level to "H" level, the potential of the output terminal 1 is changed. And a second control circuit that turns on the PMOS transistor 10 so as to change from the “L” level to the “H” level at a constant slew rate.

The first control circuit is configured as follows.
The source of the PMOS transistor 12 is connected to the power supply VDD, and the drain of the PMOS transistor 12 is connected to the drain of the NMOS transistor 22 and the gate of the PMOS transistor 10. The source of the PMOS transistor 23 is connected to the connection point 51, and the drain of the PMOS transistor 23 is connected to the gate of the NMOS transistor 11. The current source 4 is connected to the source of the PMOS transistor 5, and the drain of the PMOS transistor 5 is connected to the connection point 51. One end of the capacitor 14 is connected to the output terminal 1 and the drain of the PMOS transistor 10 and the drain of the NMOS transistor 11, and the other end of the capacitor 14 is connected to the connection point 51.

  When the internal input terminals PEN and NEN change from the “H” level to the “L” level, the PMOS transistor 10 is rapidly turned off, and the current of the current source 4 flows to the capacitor 14 through the PMOS transistor 5, thereby outputting the output terminal 1. The NMOS transistor 11 is turned on so as to change the potential at the “H” level to the “L” level at a constant slew rate.

The second control circuit is configured as follows.
The source of the NMOS transistor 13 is connected to the power supply VSS, and the drain of the NMOS transistor 13 is connected to the drain of the PMOS transistor 23 and the gate of the NMOS transistor 11. The source of the NMOS transistor 22 is connected to the connection point 51, and the drain of the NMOS transistor 22 is connected to the gate of the PMOS transistor 10. The current source 7 is connected to the source of the NMOS transistor 6, and the drain of the NMOS transistor 6 is connected to the connection point 51.

  When the internal input terminals PEN and NEN change from the “L” level to the “H” level, the NMOS transistor 11 is rapidly turned off, and the current of the current source 7 flows from the capacitor 14 through the NMOS transistor 6, thereby causing the output terminal 1. The PMOS transistor 10 is turned on so as to change the potential at the “L” level to the “H” level at a constant slew rate.

Thus, by simultaneously setting the internal input terminals PEN and NEN to the “H” level or “L” level, the change in the output voltage of the output terminal 1 can be adjusted to a constant slew rate.
JP 2000-49585 (page 12, FIG. 1)

  However, if the output terminal 1 is pulled up to the power supply VDD by a pull-up resistor, when the internal input terminals PEN and NEN change from “L” level to “H” level, the NMOS transistors 13, 6 and 22 and the current source 7 The second control circuit formed by the capacitor 14 causes the output terminal 1 to “H” at a time earlier than the time when the potential of the output terminal 1 changes from “L” level to “H” level at a constant slew rate. Reach the level.

  That is, since the output terminal 1 side of the capacitor 14 is raised to the “H” level through the pull-up resistor connected to the output terminal 1, an extra potential rise occurs at the output terminal 1, and the potential rise per unit time increases. A problem occurs.

  Further, when the output terminal 1 is pulled down to the power supply VSS by a pull-down resistor, the PMOS transistors 12, 5, 23 and the current source 4 and the capacitance when the internal input terminals PEN, NEN are changed from "H" level to "L" level. 14, the output terminal 1 is set to the “L” level earlier than the time when the potential of the output terminal 1 changes from the “H” level to the “L” level at a constant slew rate. To reach.

  That is, since the output terminal 1 side of the capacitor 14 is lowered to the “L” level through the pull-down resistor connected to the output terminal 1, an extra potential drop occurs at the output terminal 1, and the potential drop per unit time increases. The problem occurs.

  The present invention solves the above-described conventional problems, and provides a slew rate adjustment circuit that can always operate at a constant slew rate even when a pull-up resistor or a pull-down resistor is connected to the output terminal 1. For the purpose.

  In order to achieve this object, in the slew rate adjusting circuit of the present invention, the first output transistor is connected between the first power supply and the output terminal, and the second output transistor is connected between the output power supply and the second power supply. A first switch circuit for turning on / off the gate of the first output transistor, and a second switch circuit for turning on / off the gate of the second output transistor, A slew rate adjusting circuit having a slew rate adjusting capacitor connected to the output terminal, wherein a potential difference is provided between the gate of the first output transistor and the gate of the second output transistor by a first potential difference generating circuit. And a first means for connecting the capacity for adjusting the slew rate to the gate and drain of the first output transistor, and the gate and the front of the second output transistor. The gate of the first output transistor is characterized in that a second means for connecting said capacitance to the gate and drain of said given the potential difference by the second difference generating circuit second output transistor.

  According to this configuration, a pull-up resistor or a pull-down resistor is provided by applying a bias to the gate of an output transistor other than the output transistor that is changing at a constant slew rate, among the PMOS transistor and the NMOS transistor constituting the output transistor. Since the potential of the resistor can be controlled, even when a pull-up resistor or pull-down resistor is connected, it changes from “H” level to “L” level and from “L” level to “H” level at a constant slew rate. Can be made.

Hereinafter, the slew rate adjusting circuit of the present invention will be described based on each embodiment shown in FIGS.
(First embodiment)
1 to 3 show a slew rate adjusting circuit according to the first embodiment of the present invention.

  In FIG. 1, 1 is an output terminal connected to the drain of a PMOS transistor 10 as an output transistor and the drain of an NMOS transistor 11 as an output transistor, and the output terminal 1 is pulled up to a power supply VDD via a resistor 50. Yes.

The source of the PMOS transistor 10 is connected to the power supply VDD, and the source of the NMOS transistor 11 is connected to the power supply VSS.
A circuit for controlling the PMOS transistor 10 and the NMOS transistor 11 is as follows.

  The PMOS transistor 12 whose drain is connected to the gate of the PMOS transistor 10 has a source connected to the current source 8 and a drain connected to the source of the PMOS transistor 32. The drain of the PMOS transistor 32 is connected to the power supply VSS. The gate of the PMOS transistor 12 is connected to the internal input terminal PEN.

  The gate of the PMOS transistor 32 is connected to the drain of the PMOS transistor 5 whose gate is connected to the internal input terminal NEN and the source of the PMOS transistor 47. The gate of the PMOS transistor 5 is connected to the internal input terminal NEN. The gates of the PMOS transistors 46 and 47 are connected to the internal input terminal NEN. The drain of the PMOS transistor 47 is connected to the source of the PMOS transistor 46 whose gate is connected to the internal input terminal NEN, and the drain of the PMOS transistor 47 and the source of the PMOS transistor 46 are connected via the slew rate adjusting capacitor 14. It is connected to the output terminal 1. Here, one end of the capacitor 14 is referred to as a connection point 52 for explanation.

  The drain of the PMOS transistor 46 is connected to the source of the PMOS transistor 34 whose gate is connected to the internal input terminal PEN. The drain of the PMOS transistor 34 is connected to the gate of the NMOS transistor 11. The gate of the PMOS transistor 34 is connected to the internal input terminal PEN.

  In the control circuit formed by the PMOS transistors 12, 32, 5, 47, 46, and 34, the current sources 4 and 8, and the capacitor 14, the internal input terminals PEN and NEN are changed from the “H” level to the “L” level. The NMOS transistor 11 as an output transistor is controlled so that the potential of the output terminal 1 is changed from “H” level to “L” level at a constant slew rate. PMOS transistors 5, 12, and 32 and current sources 4 and 8 constituting the first switch circuit for turning on / off the transistor, the gate of the PMOS transistor 10 and the gate of the NMOS transistor 11 are given a potential difference by the PMOS transistor 32, and the PMOS First means for connecting the capacitor 14 to the gate and drain of the transistor 10 is provided. The PMOS transistor 47,46,34 which can be divided by its operating state.

  Further, in the slew rate adjusting circuit of FIG. 1, the source of the NMOS transistor 13 is connected to the power supply VSS via the current source 9, and the drain of the NMOS transistor 13 is connected to the source of the NMOS transistor 33 and the gate of the NMOS transistor 11. Yes. The drain of the NMOS transistor 33 is connected to the power supply VDD. The gate of the NMOS transistor 33 is connected to the source of the PMOS transistor 33. The gate of the NMOS transistor 13 is connected to the internal input terminal NEN.

  The source of the NMOS transistor 45 is connected to the gate of the NMOS transistor 33 and the drain of the NMOS transistor 6. The source of the NMOS transistor 6 is connected to the power source VSS via the current source 7. The gate of the NMOS transistor 6 is connected to the internal input terminal PEN.

  The drain of the NMOS transistor 45 is connected to the connection point 52 and the source of the NMOS transistor 44. The drain of the NMOS transistor 44 is connected to the source of the NMOS transistor 31 and the gate of the PMOS transistor 32. The drain of the NMOS transistor 31 is connected to the gate of the PMOS transistor 10. The gate of the NMOS transistor 31 is connected to the internal input terminal NEN. The gates of the NMOS transistors 44 and 45 are connected to the internal input terminal PEN.

  In the control circuit formed by the NMOS transistors 13, 33, 6, 44, 45, 31 and the current sources 7, 9 and the capacitor 14, the internal input terminals PEN and NEN are changed from the “L” level to the “H” level. The second switch circuit that controls the gate of the NMOS transistor 11 to turn on and off is configured to control the potential of the output terminal 1 to change from “L” level to “H” level at a constant slew rate. NMOS transistors 6, 33, and current sources 7, 9, the gate of the NMOS transistor 11 and the gate of the PMOS transistor 10 are given a potential difference by the NMOS transistor 33, and the capacitor 14 is connected to the gate and drain of the NMOS transistor 11. The NMOS transistors 31, 44, 45 constituting the second means for It can be classified by.

The operation of the slew rate adjusting circuit configured as described above will be described with reference to FIGS.
FIG. 2 shows the operation immediately after the internal input terminals PEN and NEN change from the “L” level to the “H” level. FIG. 3 shows the state of FIG. 2 with time.

  When the internal input terminals PEN and NEN become “H” level at time T0 shown in FIG. 3, the NMOS transistors 6, 13, 31, 33, 44, and 45 are turned on, and the gate of the PMOS transistor 10 that is the output transistor is turned on. The NMOS transistor 31 and the NMOS transistor 44 are connected to the connection point 52, and the capacitor 14 is connected to the drain gate of the PMOS transistor 10. Further, the connection point 52 is connected to the current source 7 through the NMOS transistor 45 and the NMOS transistor 6.

  Therefore, if a minute current flowing from the gate capacitance of the PMOS transistor 10 is ignored, a current equal to that of the current source 7 with IC = I7 flows to the capacitance 14, so that the gate potential of the PMOS transistor 10 decreases to the threshold voltage VGS10.

  At this time, the gate of the NMOS transistor 33 is connected to the connection point 52 via the NMOS transistor 45, and the current I 9 of the current source 9 flows from the source of the NMOS transistor 33 via the NMOS transistor 13. A potential difference of VGS33 is generated between the sources. Therefore, the gate of the NMOS transistor 11 is applied with the reduced voltage VGS33 with respect to the PMOS transistor 10. This state is shown from time T0 to time T1 in FIG.

  Next, when the gate potential of the PMOS transistor 10 reaches the threshold voltage VGS10, the current IC flowing through the capacitor 14 is supplied from a part of the drain current IP10 of the PMOS transistor 10, and the potential of the PMOS transistor 10 is almost equal. Transition to a period that remains constant. This period is shown as time T1 to time T2 in FIG. In the period from time T1 to time T2 in FIG. 3, the reduced voltage of VGS33 is applied to the PMOS transistor 10 at the gate of the NMOS transistor 11 as in the period from time T0 to time T1. For this reason, a bias voltage is applied to the gate of the NMOS transistor 11, and the NMOS transistor 11 tries to pass the drain current IN11. In the conventional slew rate adjusting circuit in which the NMOS transistor 11 is completely turned off, the slew rate is changed because the voltage at the output terminal 1 is rapidly increased by the resistor 50 during the period from time T1 to time T2 in FIG. According to the configuration of FIG. 1, since the slew rate of the output terminal 1 is controlled by causing the drain current IN11 of the NMOS transistor 11 to flow the IR current through the resistor 50, a rapid voltage rise at the output terminal 1 does not occur.

  When the internal input terminals PEN and NEN are changed from the “H” level to the “L” level, the output terminal 1 changes from the “H” level to the “L” level. In this case, the slew rate is the output terminal. It changes in the same manner as when 1 changes from “L” level to “H” level.

(Second Embodiment)
FIG. 4 shows a slew rate adjusting circuit according to the second embodiment of the present invention.
In FIG. 4, each of the NMOS transistors 31, 44, 45 in FIG. 1 of the (first embodiment) is configured by connecting an NMOS transistor and a PMOS transistor in parallel, and the control voltage is turned on at “H” level. It consists of gates 31a, 44a and 45a. Further, in FIG. 4, each of the PMOS transistors 47, 46, and 34 in FIG. 1 of the (first embodiment) is configured by connecting an NMOS transistor and a PMOS transistor in parallel, and is turned on when the control voltage is “L” level. Transfer gates 47a, 46a, 34a. In FIG. 4, the drain of the PMOS transistor 5 and the drain of the NMOS transistor 6 are connected to the connection point 52. Others are the same as FIG.

  Thus, by configuring the NMOS transistor and the PMOS transistor with the transfer gate, the on-resistance is lowered, and the PMOS transistor 10 and the NMOS transistor 11 that are output transistors can be controlled with higher accuracy.

  Also, transfer gate for inputs and outputs may be a current flows from either two-way such for a high degree of freedom in connection of the current source 4 and the current source 7 is adjusted slew rate current flows to the capacitor 14 Become.

  The operation of the second embodiment of the present invention configured as described above is the same as that described in the first embodiment, and the pull-up resistor 50 is connected to the output terminal 1. However, the slew rate is kept constant.

(Third embodiment)
FIG. 5 shows a slew rate adjusting circuit according to the third embodiment of the present invention.
FIG. 5 is different from FIG. 4 showing (second embodiment) only in the following points.

  That is, in FIG. 4 of the (second embodiment), the drain of the PMOS transistor 5 and the drain of the NMOS transistor 6 are connected to the connection point 52. In FIG. 5, however, the drain of the PMOS transistor 5 is connected to the NMOS transistor. The gate of the NMOS transistor 6 is connected to the gate of the PMOS transistor 32.

  The operation of the (third embodiment) of the present invention thus configured operates in the same manner as described in the (first embodiment), and a pull-up resistor 50 is connected to the output terminal 1. Even so, the slew rate is kept constant.

  In each of the above embodiments, the PMOS transistor 32 gives the potential difference VGS32 to the gate of the PMOS transistor 10 and the gate of the NMOS transistor 11, and the slew rate adjusting capacitor 14 is connected to the gate and drain of the PMOS transistor 10. The first potential difference generating circuit for generating a potential difference may be configured by replacing the PMOS transistor 32 with a bipolar PNP transistor 32B as shown in FIG. it can. Further, in each of the above embodiments, the NMOS transistor 33 gives the potential difference VGS33 to the gate of the NMOS transistor 11 and the gate of the PMOS transistor 10 and connects the capacitor 14 to the gate and drain of the NMOS transistor 11, but this potential difference is generated. The potential difference generating circuit 2 can be configured by replacing the NMOS transistor 33 with a bipolar NPN transistor 33B as shown in FIG. 6 and a potential difference between the base and the emitter in which current flows through the emitter. This can be similarly performed in FIG. 4 showing the (second embodiment) and FIG. 5 showing the (third embodiment).

  In each of the above embodiments, the case where the pull-up resistor is connected to the output terminal 1 has been described. However, according to the present invention, even when the pull-down resistor is connected or when the pull-down resistor and the pull-up resistor are connected simultaneously. The slew rate can be kept constant. If the internal input terminal PEN is set to “L” level and the internal input terminal NEN is set, the output terminal 1 can be set to a high impedance state.

  The present invention can be used in a line driver circuit, particularly a driver circuit that drives a data line at a predetermined slew rate in a USB (Universal Serial Bus).

Circuit diagram of slew rate adjustment circuit of (first embodiment) of the present invention Operation explanatory diagram of the same embodiment Time chart of the same embodiment Circuit diagram of slew rate adjusting circuit of (second embodiment) of the present invention Circuit diagram of slew rate adjusting circuit of (third embodiment) of the present invention The circuit diagram of another embodiment which comprised the 1st, 2nd potential difference generation circuit in this invention with the bipolar transistor. Circuit diagram of conventional slew rate adjustment circuit

Explanation of symbols

PEN internal input terminal NEN internal input terminal 1 output terminal 4, 7, 8, 9 current source 14 capacity 10, 12, 23, 32, 47, 46, 34, 5 PMOS transistors 11, 22, 31, 44, 45, 33 , 13 NMOS transistor 50 Resistor VG5 Gate voltage VG10 of NMOS transistor 11 Gate voltage VGS33 of PMOS transistor 10 Gate-source voltage VGS32 of NMOS transistor 33 Gate-source voltages 31a, 44a, 45a of PMOS transistor 32 Transfer gates 34a, 47a, 46a which are turned on at the H level The transfer gates which are turned on when the control voltage is the "L" level

Claims (4)

A first output transistor is connected between the first power supply and the output terminal, a second output transistor is connected between the output terminal and the second power supply, and the gate of the first output transistor is connected to the first output transistor. A slew rate having a first switch circuit for turning on / off and a second switch circuit for turning on / off the gate of the second output transistor, and a slew rate adjusting capacitor connected to the output terminal An adjustment circuit,
The gate of the first output transistor and the gate of the second output transistor are given a potential difference by a first potential difference generation circuit, and the capacitor for adjusting the slew rate is connected to the gate and drain of the first output transistor. First means to:
Second means for connecting the capacitor to the gate and drain of the second output transistor by applying a potential difference between the gate of the second output transistor and the gate of the first output transistor by a second potential difference generation circuit. A slew rate adjustment circuit. The first output transistor is a P-type MOSFET having a source connected to the first power supply and a drain connected to the output terminal,
2. The slew rate adjusting circuit according to claim 1, wherein the second output transistor is an N-type MOSFET having a source connected to the second power supply and a drain connected to the output terminal. The first potential difference generation circuit is a potential difference between the gate and the source of the operating P-type MOSFET in which a current flows through the source,
2. The slew rate adjusting circuit according to claim 1, wherein the second potential difference generating circuit is a potential difference between the gate and the source of the N-type MOSFET in operation in which a current flows through the source. The first potential difference generating circuit is a potential difference between the base and the emitter of the active bipolar PNP transistor in which current flows through the emitter,
2. A slew rate adjusting circuit according to claim 1, wherein said second potential difference generating circuit is a potential difference between the base and emitter of a bipolar NPN transistor in operation in which a current flows through the emitter.

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