KR20140086675A - Data output circuit - Google Patents

Data output circuit Download PDF

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Publication number
KR20140086675A
KR20140086675A KR1020120157427A KR20120157427A KR20140086675A KR 20140086675 A KR20140086675 A KR 20140086675A KR 1020120157427 A KR1020120157427 A KR 1020120157427A KR 20120157427 A KR20120157427 A KR 20120157427A KR 20140086675 A KR20140086675 A KR 20140086675A
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South Korea
Prior art keywords
voltage
transistor
back bias
pull
bias voltage
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KR1020120157427A
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Korean (ko)
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장채규
왕종현
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에스케이하이닉스 주식회사
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Priority to KR1020120157427A priority Critical patent/KR20140086675A/en
Publication of KR20140086675A publication Critical patent/KR20140086675A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

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Abstract

The present invention relates to a data output circuit for reducing leakage current while operating in a low voltage environment. A pull-up transistor for pulling up the output node when the logic value of output data output to the output node is high; A pull-down transistor for pulling down the output node when the logic value of the output data is low; And a back bias voltage regulator for regulating a back bias voltage of the pull-up transistor and the pull-down transistor according to a logical value of the output data.

Figure P1020120157427

Description

DATA OUTPUT CIRCUIT [0002]

The present invention relates to a data output circuit for reducing leakage current while operating at a low voltage.

Semiconductor devices are becoming increasingly faster, more highly integrated, and have lower power consumption. In order to increase the speed and power consumption of semiconductor devices, devices used in semiconductor devices must operate without problems even at low voltages. If a general device not designed to be used at a low voltage is used, there is a problem that it is not operated properly in a low voltage environment. Leakage current problems can also occur in devices designed to operate at low voltages. For example, a conventional transistor has a problem that a threshold voltage is high and thus does not operate in response to a low voltage. In the case of a low voltage transistor, there is a problem that a leakage current increases due to a low threshold voltage.

1 is a configuration diagram of a conventional data output circuit.

As shown in Fig. 1, the data output circuit includes an output node OUT, a pull-up transistor P, and a pull-down transistor N. [

The pull-up transistor P1 is turned on when the output data output to the output node OUT is high and pulls up the output node OUT. The pull-down transistor N is turned on when the output data output to the output node OUT is low to pull-down drive the output node OUT. When the input data to the input node IN is taken as a reference, the pull-up transistor P is turned on to pull-up the output node OUT when the input data is low, and the pull- And the output node OUT is pulled down.

Here, when the absolute value of the threshold voltage of the pull-up transistor P and the pull-down transistor N is relatively large (in the case of not a low-voltage transistor), the transistor does not turn on well in response to input data in operation at a low voltage. The voltage level corresponding to the high of the input data is not high enough to turn on the pull-down transistor N sufficiently and the voltage level corresponding to the low of the input data is not low enough to turn on the pull-up transistor P sufficiently. Therefore, the input data is not properly output to the output node OUT.

Further, when the absolute value of the threshold voltage of the pull-up transistor P and the pull-down transistor N is relatively small (in the case of the low voltage transistor), there is no problem in driving the output node OUT in response to the input data at the time of operation at the low voltage There is a problem that it is difficult to block the leakage current because the magnitude of the absolute value of the threshold voltage is small.

For reference, VDD and VSS represent the power supply voltage and the ground voltage, respectively.

The present invention provides a data output circuit that operates at a low voltage by reducing the absolute value of the threshold voltage of a transistor driving an output node upon data output.

The present invention also provides a data output circuit that reduces the leakage current by increasing the absolute value of the threshold voltage of a transistor that does not drive an output node during data output.

A data output circuit according to the present invention comprises an output node; A pull-up transistor for pulling up the output node when the logic value of output data output to the output node is high; A pull-down transistor for pulling down the output node when the logic value of the output data is low; And a back bias voltage regulator for regulating a back bias voltage of the pull-up transistor and the pull-down transistor according to a logic value of the output data.

Further, a data output circuit according to the present invention includes an output node; A PMOS transistor for pulling up the output node when a logic value of output data output to the output node is high; An NMOS transistor for pulling down the output node when the logic value of the output data is low; And applying a voltage lower than the voltage applied to the source of the PMOS transistor to the back bias voltage of the PMOS transistor when the logic value of the output data is high and a voltage lower than a voltage applied to the source of the PMOS transistor Wherein when the logic value of the output data is low, a voltage higher than a voltage applied to the source of the NMOS transistor is applied to the back bias voltage of the NMOS transistor, And a back bias voltage regulator for applying a voltage higher than the voltage applied to the source of the transistor to the back bias voltage of the PMOS transistor.

Further, a data output circuit according to the present invention includes an output node; A PMOS transistor for pulling up the output node when a logic value of output data output to the output node is high; An NMOS transistor for pulling down the output node when the logic value of the output data is low; And applying a voltage lower than the voltage applied to the source of the PMOS transistor to the back bias voltage of the PMOS transistor when the logic value of the output data is high and a voltage equal to the voltage applied to the source of the PMOS transistor Wherein when the logic value of the output data is low, a voltage higher than a voltage applied to the source of the NMOS transistor is applied to the back bias voltage of the NMOS transistor, And a back bias voltage regulator for applying a voltage equal to the voltage applied to the source of the transistor to the back bias voltage of the PMOS transistor.

Further, a data output circuit according to the present invention includes an input node; Output node; A pull-up transistor for pulling up the output node when the logic value of input data input to the input node is low; A pull-down transistor for pulling up the output node when the logic value of the input data is high; And a back bias voltage regulator for regulating a back bias voltage of the pull-up transistor and the pull-up transistor in response to the input data.

In this technique, since the absolute value of the threshold voltage of the transistor driving the output node is decreased in data output, even when the absolute value of the voltage level corresponding to the logic value of the input data is small, the driving transistor is sufficiently turned on to drive the output node, It works without problems.

In addition, the present technique increases the absolute value of the threshold voltage of a transistor that does not drive the output node during data output, effectively turning off the transistor and effectively blocking the leakage current.

1 is a configuration diagram of a conventional data output circuit,
2 is a configuration diagram of a data output circuit according to an embodiment of the present invention,
3 is a configuration diagram of a data output circuit according to another embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

2 is a configuration diagram of a data output circuit according to an embodiment of the present invention.

2, the data output circuit includes a pull-up transistor P for pulling up the output node OUT when the logic value of the output data output to the output node OUT and the output node OUT is high, Down transistor N for pulling down the output node OUT when the logical value of the output data is low and the pull-down transistor N for adjusting the back bias voltage of the pull-up transistor P and the pull- And a back bias voltage regulator 210.

The data output circuit will be described with reference to Fig.

The pull-up transistor P pulls up the output node OUT when the output data is high. The pull-up transistor P is a PMOS transistor having a source S connected to the power source voltage VDD, a drain D connected to the output node OUT, and a gate G connected to the input node IN . A voltage is applied to the bulk of the pull-up transistor P through the 'B' terminal of the pull-up transistor P. For reference, the voltage applied to the bulk of the transistor is the back bias voltage.

The pull-down transistor N pulls down the output node OUT when the output data is low. The pull-down transistor N is an NMOS transistor in which a base voltage VSS is applied to a source S, a drain D is connected to an output node OUT, and a gate G is connected to an input node IN . A voltage is applied to the bulk of the pull-down transistor N through the 'B' terminal of the pull-down transistor N.

The back bias voltage regulator 210 adjusts the absolute value of the threshold voltage of the pull-up transistor P and the pull-down transistor N according to the logic value of the output data. The back bias voltage regulator 210 makes the absolute value of the threshold voltage of the transistor driving the output node OUT small according to the logical value of the output data so as to drive the output node OUT more well, The absolute value of the threshold voltage of the transistor which does not drive the transistor is increased to reduce the leakage current.

If the logic value of the output data is high, the back bias voltage regulator 210 controls the pull-up transistor N so that the absolute value of the threshold voltage of the pull-up transistor P becomes small and the absolute value of the threshold voltage of the pull- The back bias voltage of the transistor P and the pull-down transistor N is adjusted. If the absolute value of the threshold voltage of the pull-up transistor P is made small, the pull-up transistor P is turned on more effectively because the pull-up transistor P pulls up the output node OUT when the logic value of the output data is high. (OUT) is pulled up more strongly. Thus, the logic value of the output data transitions to a higher and faster state. At this time, the pull-down transistor N, which is not related to driving the output node OUT, can reduce the leakage current through the pull-down transistor N since the absolute value of the threshold voltage becomes large.

On the other hand, when the logic value of the output data is low, the back bias voltage regulator 210 controls the pull-down transistor N so that the absolute value of the threshold voltage of the pull-down transistor N becomes small and the absolute value of the threshold voltage of the pull- (N) and the pull-up transistor (P). When the logic value of the output data is low, the pull-down transistor N pulls down the output node OUT so that if the absolute value of the threshold voltage of the pull-down transistor N is made small, the pull- (OUT) is more strongly pulled down. Thus, the logic value of the output data transitions to a lower speed. At this time, the absolute value of the threshold voltage of the pull-up transistor (P) irrespective of driving the output node (OUT) becomes large, so that the leakage current through the pull-up transistor (P) can be reduced.

The back bias voltage regulator 210 regulates the absolute value of the threshold voltage of the pull-up transistor P and the pull-down transistor N by adjusting the back bias voltage of the pull-up transistor P and the pull- Hereinafter, the operation of the back bias regulator 210 will be described focusing on the method of adjusting the back bias voltage of the pull-up transistor P and the pull-down transistor N. FIG.

The back bias voltage regulator 210 controls the back bias voltage of the PMOS transistor P when the logic value of the output data is high and the back bias voltage of the PMOS transistor P is the voltage of the source S of the PMOS transistor P, And the back bias voltage of the NMOS transistor N is equal to the voltage applied to the source S of the NMOS transistor N or the back bias voltage of the NMOS transistor N The voltage applied to the B node of N is lower than the voltage applied to the source S of the NMOS transistor N. [ The absolute value of the threshold voltage of the PMOS transistor P is reduced when a voltage lower than the voltage applied to the source S is applied with the back bias voltage. The absolute value of the threshold voltage becomes large when the emmos transistor N applies a voltage equal to the voltage applied to the source S or a voltage lower than the voltage applied to the source S with the back bias voltage.

The back bias voltage regulator 210 also causes the back bias voltage of the NMOS transistor N to be higher than the voltage applied to the source S of the NMOS transistor N when the logic value of the output data is low, The back bias voltage of the PMOS transistor P is equal to the voltage applied to the source S of the PMOS transistor P or the back bias voltage of the PMOS transistor P is applied to the source S). The absolute value of the threshold voltage becomes small when the emmos transistor N applies a voltage higher than the voltage applied to the source S with the back bias voltage. The absolute value of the threshold voltage becomes large when the PMOS transistor P applies a voltage equal to the voltage applied to the source S or a voltage higher than the voltage applied to the source S with the back bias voltage.

The back bias voltage regulator 210 outputs a voltage V1 lower than the voltage applied to the source S of the PMOS transistor P to the back bias voltage V of the PMOS transistor P when the logical value of the output data is high. V2 higher than the voltage applied to the source S of the PMOS transistor P or higher than the voltage applied to the source S of the PMOS transistor P when the logic value of the output data is low, ) To the back bias voltage of the PMOS transistor (P).

When the logic value of the output data is high, the back bias voltage regulator 210 outputs a voltage equal to or higher than a voltage applied to the source S of the NMOS transistor N, (V3) lower than the voltage applied to the source (S) of the MOS transistor (N) when the logic value of the output data is low V4) to the back bias voltage of the NMOS transistor (N).

2, the first voltage regulator 211 includes a resistor R1 and transistors P1 and N1 and the second voltage regulator 212 includes a resistor R2 and transistors P2 and N2. .

When the input data input to the input node IN is low, the output data is high. When the input data is low, the first voltage regulator 211 turns on the NMOS transistor N1 and turns off the PMOS transistor P1. Therefore, 'V1' generated by dividing the power supply voltage VDD by the law of voltage distribution is transferred to the back bias voltage of the PMOS transistor P. In the second voltage regulator 212, the NMOS transistor N2 is turned on and the PMOS transistor P2 is turned off. Therefore, 'V3' carries the back bias voltage of the NMOS transistor (N).

When the input data input to the input node IN is high, the output data is low. When the input data is low, the first voltage regulator 211 turns on the PMOS transistor P1 and turns off the NMOS transistor N1. Therefore, 'V2' is transferred to the back bias voltage of the PMOS transistor P. The PMOS transistor P2 is turned on in the second voltage regulator 212 and the NMOS transistor N2 is turned off. Accordingly, 'V4' generated by dividing the power supply voltage VDD by the law of voltage distribution transfers the back bias voltage of the NMOS transistor N.

The input data input to the input node IN is directly transferred to the gate G of the PMOS transistor P and the NMOS transistor N. However, May be delayed by a predetermined delay value and then transferred to the gates G of the PMOS transistor P and the NMOS transistor N. [ In this case, a delay circuit for delaying the signal between the input node IN, the PMOS transistor P, and the gate G of the NMOS transistor N may be included.

The data output circuit according to the present invention reduces the absolute value of the threshold voltage of the transistor driving the output node at the time of data output so that even if the absolute value of the voltage level corresponding to the logic value of the input data is small, So that it operates without problems even at low voltage. Further, the absolute value of the threshold voltage of the transistor not driving the output node is increased, and the transistor is turned off more reliably to effectively block the leakage current.

3 is a configuration diagram of a data output circuit according to another embodiment of the present invention.

3, the data output circuit includes an input node IN, an output node OUT, and an output node OUT when the logic value of the input data IN_DATA input to the input node IN is low. Pull-up transistor P for pull-up driving and pull-down transistor N for pulling down output node OUT when the logic value of input data IN_DATA is high and pull-up transistor P in response to input data IN_DATA And a back bias voltage regulator 310 for regulating a back bias voltage of the pull-down transistor N.

The data output circuit will be described with reference to FIG.

The configuration and operation of the data output circuit of Fig. 3 are almost similar to those of the data output circuit of Fig. However, the configuration of the back bias voltage regulator 310 is different from the configuration of the back bias voltage regulator 210 of FIG.

The back bias voltage regulator 310 adjusts the back bias voltage of the pull-up transistor P and the pull-down transistor N in response to the input data IN_DATA input to the input node IN, The absolute value of the threshold voltage of the transistor N is adjusted.

When the logic value of the input data is low, the back bias voltage regulator 310 controls the pull-up transistor N so that the absolute value of the threshold voltage of the pull-up transistor P becomes small and the absolute value of the threshold voltage of the pull- P and the pull-down transistor N. When the logic value of the input data IN_DATA is high, the absolute value of the threshold voltage of the pull-down transistor P becomes small and the threshold voltage of the pull- The back bias voltage of the pull-down transistor N and the pull-up transistor P is adjusted so that the absolute value of the pull-

The back bias voltage regulator 310 adjusts the back bias voltage of the pull-up transistor P and the pull-down transistor N in response to the input data IN_DATA so that the threshold voltage of the pull- Adjust the absolute value. Hereinafter, the operation of the back bias regulator 310 will be described with a focus on a method of adjusting the back bias voltage of the pull-up transistor P and the pull-down transistor N. FIG.

The back bias voltage regulator 310 controls the back bias voltage of the PMOS transistor P to be lower than the voltage applied to the source S of the PMOS transistor P when the logic value of the input data IN_DATA is low. And the back bias voltage of the NMOS transistor N is equal to the voltage applied to the source S of the NMOS transistor N or the back bias voltage of the NMOS transistor N To be lower than the voltage applied to the source (S).

When the logic value of the input data IN_DATA is high, the back bias voltage regulator 310 controls the back bias voltage of the NMOS transistor N to be higher than the voltage applied to the source S of the NMOS transistor N And the back bias voltage of the PMOS transistor P is equal to the voltage applied to the source S of the PMOS transistor P or the back bias voltage of the PMOS transistor P is the same as the voltage applied to the PMOS transistor P, To be higher than the voltage applied to the source (S).

The back bias voltage regulator 310 outputs a voltage V1 lower than the voltage applied to the source S of the PMOS transistor P when the logic value of the input data IN_DATA is low, And is applied to the source S of the PMOS transistor P when the logic value of the input data IN_DATA is high or equal to the voltage applied to the source S of the PMOS transistor P And a first voltage regulator 211 for transferring a voltage V2 higher than the voltage V2 to the back bias voltage of the PMOS transistor P.

When the logic value of the input data IN_DATA is low, the back bias voltage regulator 310 adjusts the voltage of the source S of the NMOS transistor N equal to the voltage applied to the source S of the NMOS transistor N, (V3) lower than the voltage applied to the MOS transistor N to the back bias voltage of the NMOS transistor N and to the source S of the NMOS transistor N when the logic value of the input data IN_DATA is low And a second voltage regulator 212 for transferring a voltage V4 higher than the applied voltage to the back bias voltage of the NMOS transistor N. [

In the embodiment of FIG. 3, the first voltage regulator 211 includes two PMOS transistors P1 and P2, and the second voltage regulator 212 includes two NMOS transistors N1 and N2. do.

When the input data IN_DATA is low, 'P1' is turned on and 'P2' is turned off in the first voltage regulator 211. Therefore, 'V1' is transmitted as the back bias voltage of the PMOS transistor P. In the second voltage regulator 212, 'N2' is turned on and 'N1' is turned off. Therefore, 'V3' carries the back bias voltage of the NMOS transistor (N).

When the input data IN_DATA is low, 'P2' is turned on and 'P1' is turned off in the first voltage regulator 211. Therefore, 'V2' is transferred to the back bias voltage of the PMOS transistor P. In the second voltage regulator 212, 'N1' is turned on and 'N2' is turned off. Therefore, 'V4' carries the back bias voltage of the NMOS transistor (N).

The effect of the data output circuit of Fig. 3 is the same as that of the data output circuit of Fig. 2, the back bias voltage regulator 210 operates on the basis of the logical value of the output data. In FIG. 3, the back bias voltage regulator 310 operates in response to the input data IN_DATA .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

Claims (14)

Output node;
A pull-up transistor for pulling up the output node when the logic value of output data output to the output node is high;
A pull-down transistor for pulling down the output node when the logic value of the output data is low; And
And a back bias voltage regulator for regulating a back bias voltage of the pull-up transistor and the pull-up transistor according to a logic value of the output data,
And a data output circuit.
The method according to claim 1,
The back bias voltage regulator
Up transistor and the pull-down transistor so that the absolute value of the threshold voltage of the pull-up transistor becomes smaller and the absolute value of the threshold voltage of the pull-down transistor becomes larger when the logic value of the output data is high,
Up transistor and a pull-up transistor to adjust a back bias voltage of the pull-up transistor so that an absolute value of a threshold voltage of the pull-down transistor becomes smaller and an absolute value of a threshold voltage of the pull- Circuit.
3. The method of claim 2,
Wherein the pull-up transistor is a PMOS transistor and the pull-down transistor is an NMOS transistor.
The method of claim 3,
The back bias voltage regulator
The back bias voltage of the PMOS transistor is lower than the voltage applied to the source of the PMOS transistor when the logic value of the output data is high and the back bias voltage of the PMOS transistor is applied to the source of the NMOS transistor So that the voltage becomes lower than the applied voltage,
When the logic value of the output data is low, the back bias voltage of the NMOS transistor is made higher than the voltage applied to the source of the NMOS transistor and the back bias voltage of the PMOS transistor is applied to the source of the PMOS transistor So that the voltage becomes higher than the applied voltage.
5. The method of claim 4,
The back bias voltage regulator
When the logic value of the output data is high, a voltage lower than the voltage applied to the source of the PMOS transistor is transferred to the back bias voltage of the PMOS transistor, and when the logic value of the output data is low, A first voltage regulator for delivering a voltage higher than the voltage applied to the source to the back bias voltage of the PMOS transistor; And
When the logic value of the output data is high, a voltage lower than the voltage applied to the source of the NMOS transistor is transferred to the back bias voltage of the NMOS transistor, and when the logic value of the output data is low, A second voltage regulator for transferring a voltage higher than the voltage applied to the source to the back bias voltage of the NMOS transistor,
And a data output circuit.
The method of claim 3,
The back-
The back bias voltage of the NMOS transistor is made equal to the voltage applied to the source of the NMOS transistor when the logic value of the output data is high,
And the back bias voltage of the PMOS transistor is equal to the voltage applied to the source of the PMOS transistor when the logic value of the output data is low.
The method according to claim 6,
The back bias voltage regulator
When the logic value of the output data is high, a voltage lower than the voltage applied to the source of the PMOS transistor is transferred to the back bias voltage of the PMOS transistor, and when the logic value of the output data is low, A first voltage regulator for transferring a voltage equal to a voltage applied to the source to the back bias voltage of the PMOS transistor; And
When the logic value of the output data is high, a voltage equal to the voltage applied to the source of the NMOS transistor is transferred to the back bias voltage of the NMOS transistor, and when the logic value of the output data is low, A second voltage regulator for transferring a voltage higher than the voltage applied to the source to the back bias voltage of the NMOS transistor,
And a data output circuit.
Output node;
A PMOS transistor for pulling up the output node when a logic value of output data output to the output node is high;
An NMOS transistor for pulling down the output node when the logic value of the output data is low; And
Wherein when the logic value of the output data is high, a voltage lower than a voltage applied to the source of the PMOS transistor is applied as a back bias voltage of the PMOS transistor, and a voltage lower than a voltage applied to the source of the NMOS transistor And when a logic value of the output data is low, a voltage higher than a voltage applied to the source of the NMOS transistor is applied as a back bias voltage of the NMOS transistor, A back bias voltage regulating unit for applying a voltage higher than the voltage applied to the source of the PMOS transistor to the back bias voltage of the PMOS transistor,
And a data output circuit.
Output node;
A PMOS transistor for pulling up the output node when a logic value of output data output to the output node is high;
An NMOS transistor for pulling down the output node when the logic value of the output data is low; And
When the logic value of the output data is high, a voltage lower than the voltage applied to the source of the PMOS transistor is applied as the back bias voltage of the PMOS transistor, and a voltage equal to the voltage applied to the source of the PMOS transistor is applied to the And when a logic value of the output data is low, a voltage higher than a voltage applied to the source of the NMOS transistor is applied as a back bias voltage of the NMOS transistor, A back bias voltage regulating unit for applying a voltage equal to the voltage applied to the source of the PMOS transistor to the back bias voltage of the PMOS transistor,
And a data output circuit.
An input node;
Output node;
A pull-up transistor for pulling up the output node when the logic value of input data input to the input node is low;
A pull-down transistor for pulling up the output node when the logic value of the input data is high; And
And a back bias voltage regulator for regulating a back bias voltage of the pull-up transistor and the pull-up transistor in response to the input data,
And a data output circuit. 11. The method of claim 10,
The back bias voltage regulator
Up transistor and the pull-down transistor so that the absolute value of the threshold voltage of the pull-up transistor becomes smaller and the absolute value of the threshold voltage of the pull-down transistor becomes larger when the logic value of the input data is low,
Up transistor and the pull-up transistor to adjust the back bias voltage of the pull-up transistor so that the absolute value of the threshold voltage of the pull-down transistor becomes smaller and the absolute value of the threshold voltage of the pull-up transistor becomes larger when the logic value of the input data is high, Circuit.
12. The method of claim 11,
Wherein the pull-up transistor is a PMOS transistor and the pull-down transistor is an NMOS transistor.
13. The method of claim 12,
The back bias voltage regulator
The back bias voltage of the PMOS transistor is lower than the voltage applied to the source of the PMOS transistor when the logic value of the input data is low and the back bias voltage of the NMOS transistor is applied to the source of the NMOS transistor So that the voltage becomes lower than the applied voltage,
When the logic value of the input data is high, the back bias voltage of the NMOS transistor is made higher than the voltage applied to the source of the NMOS transistor and the back bias voltage of the PMOS transistor is applied to the source of the PMOS transistor So that the voltage becomes higher than the applied voltage.
13. The method of claim 12,
The back-
The back bias voltage of the NMOS transistor is equal to the voltage applied to the source of the NMOS transistor when the logic value of the input data is low,
And the back bias voltage of the PMOS transistor becomes equal to the voltage applied to the source of the PMOS transistor when the logic value of the input data is high.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170082956A (en) * 2016-01-07 2017-07-17 에스케이하이닉스 주식회사 Semiconductor device
CN107251434A (en) * 2015-02-25 2017-10-13 高通股份有限公司 The output driver prevented with reverse power supply

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107251434A (en) * 2015-02-25 2017-10-13 高通股份有限公司 The output driver prevented with reverse power supply
CN107251434B (en) * 2015-02-25 2020-08-18 高通股份有限公司 Output driver with reverse supply prevention
KR20170082956A (en) * 2016-01-07 2017-07-17 에스케이하이닉스 주식회사 Semiconductor device
US9722579B1 (en) 2016-01-07 2017-08-01 SK Hynix Inc. Semiconductor device

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