JPH03225402A - Constant voltage generating circuit - Google Patents
Constant voltage generating circuitInfo
- Publication number
- JPH03225402A JPH03225402A JP2018981A JP1898190A JPH03225402A JP H03225402 A JPH03225402 A JP H03225402A JP 2018981 A JP2018981 A JP 2018981A JP 1898190 A JP1898190 A JP 1898190A JP H03225402 A JPH03225402 A JP H03225402A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- resistor
- circuit
- voltage
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005513 bias potential Methods 0.000 claims abstract description 10
- 230000007257 malfunction Effects 0.000 abstract description 8
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
- G05F3/222—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
- G05F3/227—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage producing a current or voltage as a predetermined function of the supply voltage
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
- Control Of Electrical Variables (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
定電圧発生回路、特に、複数の電源電圧を使用するバイ
ポーラＣＭＯ３回路に定電圧を供給する回路の構成に関
し、
温度や電源電圧等の変化にかかわらず常に定電圧の供給
を可能にし、ひいては誤動作の防止を図ることを目的と
し、
外部電源電圧のラインに接続された第１の電源ラインと
、該第１の電源ラインと異なる電圧を有する少なくとも
１つの第２の電源ラインと、該第１および第２の電源ラ
インの間でダーリントン接続された複数のトランジスタ
を有するレベルシフト回路と、該レベルシフト回路にお
ける最終段のトランジスタのベースと一方の電源ライン
との間に接続された抵抗器と、該抵抗器と他方の電源ラ
インの間に接続され、該抵抗器に流れる電流を所定のバ
イアス電位により制御する回路とを具備するように構成
する。[Detailed Description of the Invention] [Summary] Regarding the configuration of a constant voltage generation circuit, especially a circuit that supplies a constant voltage to a bipolar CMO3 circuit that uses multiple power supply voltages, it is possible to always maintain a constant voltage regardless of changes in temperature, power supply voltage, etc. A first power supply line connected to an external power supply voltage line and at least one second power supply line having a voltage different from that of the first power supply line are connected to the external power supply voltage line in order to enable voltage supply and prevent malfunctions. a level shift circuit having a plurality of transistors Darlington-connected between a power supply line and the first and second power supply lines, and a base of a final stage transistor in the level shift circuit and one power supply line. and a circuit connected between the resistor and the other power supply line to control the current flowing through the resistor using a predetermined bias potential.
［産業上の利用分野］
本発明は、定電圧発生回路に関し、特に、複数の電源電
圧を使用するバイポーラＣＭＯ３回路に定電圧を供給す
る回路の構成に関する。[Industrial Field of Application] The present invention relates to a constant voltage generation circuit, and particularly to the configuration of a circuit that supplies a constant voltage to a bipolar CMO3 circuit that uses a plurality of power supply voltages.
同一チンブ内にバイポーラトランジスタとＭＯＳトラン
ジスタを混在したバイポーラＣＭＯＳ１１造の半導体デ
バイスは、通常、外部から供給される単一の電源電圧に
より動作するよう構成されている。また、複数の電源を
使用する場合も同様に外部端子から電源電圧を供給する
ようになっている。この場合、外部から複数の電源電圧
を与えるため、端子数が増加し、また、各電源電圧相互
間のばらつきは互いに無関係なので、動作マージンを十
分にとる必要がある。A bipolar CMOS 11 semiconductor device in which bipolar transistors and MOS transistors are mixed in the same chip is usually configured to operate with a single power supply voltage supplied from the outside. Furthermore, when using multiple power supplies, power supply voltages are similarly supplied from external terminals. In this case, since a plurality of power supply voltages are applied from the outside, the number of terminals increases, and variations among the power supply voltages are unrelated to each other, so it is necessary to provide a sufficient operating margin.
第２図にはバイポーラＣＭＯ３回路の一構成例が示され
る。同図に示す回路は、エミッタ結合型論理（ＥＣＬ）
ゲートで直接ＣＭＯＳゲートを動作させる場合の構成を
示している。FIG. 2 shows an example of the configuration of a bipolar CMO3 circuit. The circuit shown in the figure is emitter-coupled logic (ECL)
This shows a configuration in which the CMOS gate is directly operated by the gate.
なお、以下の記述において特に規定しない限り、「トラ
ンジスタ」とはｎｐｎ型バイポーラトランジスタを指す
ものとする。Note that in the following description, unless otherwise specified, the term "transistor" refers to an npn-type bipolar transistor.
ＥＣＬゲートは、それぞれ入力信号ＶＩＮ、基準電圧信
号ＶＩ？ＥＦに応答する１対のエミッタ結合されたトラ
ンジスタＴｌ、Ｔ２と、該トランジスタの各コレクタと
グランドラインＧＮＤ （ＯＶ）の間にそれぞれ接続さ
れた抵抗器Ｒ１，Ｒ２と、該トランジスタの共通エミッ
タにコレクタが接続され所定のバイアス電圧ｖＣ３に応
答するトランジスタＴ３と、該トランジスタＴ３のエミ
ッタと負電位の電源ラインＶＥＥＩＯ間に接続された抵
抗器Ｒ３と、グランドラインＧＮＤにコレクタが接続さ
れトランジスタＴ２のコレクタ電位に応答するトランジ
スタＴ４と、該トランジスタＴ４のエミッタと電源ライ
ンＶＥＥＩＯ間に接続された抵抗器Ｒ４とから構成され
ている。なお、トランジスタＴ３と抵抗器Ｒ３は定電流
源を構成し、その電流値はＩ ＝ （ＶＣ５−ＶＥＥＩ
Ｖ ＭＥ）／Ｒ３Ｔ：表される。ココで、■、はト
ランジスタＴ３のベース・エミッタ間電圧を表す。The ECL gate receives an input signal VIN and a reference voltage signal VI?, respectively. A pair of emitter-coupled transistors Tl, T2 responsive to EF, resistors R1, R2 respectively connected between the collectors of the transistors and the ground line GND (OV), and a collector connected to the common emitter of the transistors. A transistor T3 is connected to the transistor T3 and responds to a predetermined bias voltage vC3, a resistor R3 is connected between the emitter of the transistor T3 and a negative potential power line VEEIO, and the collector is connected to the ground line GND and the collector potential of the transistor T2 is , and a resistor R4 connected between the emitter of the transistor T4 and the power supply line VEEIO. Note that the transistor T3 and the resistor R3 constitute a constant current source, and the current value is I = (VC5-VEEI
VME)/R3T: Represented. Here, ■ represents the voltage between the base and emitter of the transistor T3.
また、ＣＭＯＳゲートは、グランドラインＧＮＤと負電
位の電源ラインＶＥＥ２（＞ＶＥＥ１）の間に直列に接
続され、それぞれＥＣＬゲートの出力（トランジスタＴ
４のエミッタ電位ＶＡ）に応答するｐチャネルＭＯ３）
ランジスタＱｐおよびｎチャネルＭＯＳトランジスタｇ
ｎから構成されている。Further, the CMOS gates are connected in series between the ground line GND and the negative potential power line VEE2 (>VEE1), and the outputs of the ECL gates (transistors T
p-channel MO3) responsive to emitter potential VA) of 4)
Transistor Qp and n-channel MOS transistor g
It is composed of n.
ＥＣＬとＣＭＯ３の論理レベルは互いに異なるため、双
方のゲートを接続する場合にはレベル変換回路を間に挿
入する必要があるが、上記構成において、ＥＣＬゲート
の電源電圧ＶＥＥＩが通常の５．２ｖである時にＣＭＯ
Ｓゲートの電源電圧ＶＥＥ２を−３，ＯＶで動作させれ
ば、レベル変化回路は不要となる。Since the logic levels of ECL and CMO3 are different from each other, it is necessary to insert a level conversion circuit between them when connecting both gates. However, in the above configuration, the power supply voltage VEEI of the ECL gate is the normal 5.2V. CMO at one time
If the power supply voltage VEE2 of the S gate is operated at -3.OV, the level change circuit becomes unnecessary.
この場合、ＥＣＬゲートの電源電圧ＶＥＥＩは外部から
供給され、ＣＭＯＳゲートの電源電圧ＶＥＥ２は、例え
ば第３図に示される定電圧発生回路により供給される。In this case, the power supply voltage VEEI of the ECL gate is supplied from the outside, and the power supply voltage VEE2 of the CMOS gate is supplied, for example, by a constant voltage generation circuit shown in FIG.
図示の回路は、グランドラインＧＮＤと１を源ラインＶ
ＥＥＩＯ間に直列に接続された抵抗器Ｒ５、ダイオード
ＤＩ、Ｄ２および抵抗器Ｒ６から構成され、ｔａ電圧Ｖ
ＥＥ２はダイオードＤＩのアノード端子から取り出され
る。The illustrated circuit connects the ground line GND and 1 to the source line V
It consists of a resistor R5, diodes DI, D2, and a resistor R6 connected in series between EEIO, and the ta voltage V
EE2 is taken out from the anode terminal of diode DI.
〔発明が解決しようとする課題］
第２図の構成において、ＥＣＬゲートの出力ＶＡはグラ
ンドレベルＧＮＤから決定され、その“Ｌ”レベルの電
位ＶＡ （Ｌ）は、
ＶＡ（Ｌ） ＝（Ｒ２・Ｉ ＋ ＶＩＥ）で表される。[Problems to be Solved by the Invention] In the configuration shown in FIG. 2, the output VA of the ECL gate is determined from the ground level GND, and its "L" level potential VA (L) is expressed as VA (L) = (R2 · I + VIE).
ただし、■１はトランジスタＴ４のベース・エミッタ間
電圧を表す。ＥＣＬゲートの出力ＶＡカその“Ｌ″レベ
ルある時、次段のＣＭＯＳゲートではｐチャネルＭＯ３
）ランジスタＱｐがオンし、ｎチャネルＭＯ３Ｉ−ラン
ジスタＱｎはカットオフ状態となっていなければならな
い。従って、ＣＭＯＳゲートを上記“ビレベルの電位Ｖ
Ａ （Ｌ）で安定に動作させるためには、該電位ＶＡ
（Ｌ）と電源電圧ＶＥＥ２の電位差がｎチャネルＭＯ３
）ランジスタＱｎのスレッショルド電圧ｖｔｈよりも小
さいという条件が必須である。この条件は温度や電源電
圧ＶＥＥＩが変化した場合でも満足されなければならな
い。However, ■1 represents the voltage between the base and emitter of the transistor T4. When the output VA of the ECL gate is at “L” level, the next stage CMOS gate outputs p-channel MO3.
) The transistor Qp must be turned on and the n-channel MO3I-transistor Qn must be in the cut-off state. Therefore, the CMOS gate is connected to the above-mentioned “bi-level potential V”.
In order to operate stably at A (L), the potential VA
(L) and power supply voltage VEE2 is the n-channel MO3
) It is essential that the voltage is smaller than the threshold voltage vth of the transistor Qn. This condition must be satisfied even when the temperature or power supply voltage VEEI changes.
ところが第３図に示されるような回路で電源電圧ＶＥＥ
Ｉ、ＶＥＥ２を供給した場合、温度や電源電圧の変化に
対してダイオードＤＩ 、 Ｄ２のＶ−１特性が変化し
、そのために上記条件を常に満足できないという可能性
がある。つまり、ＥＣＬゲートの出力Ｖ八がその”ビレ
ヘルにある時、ｎチャネルＭＯＳトランジスタＱｎもオ
ン状態となり（誤動作）、グランドラインＧＮＤからト
ランジスタＱｐおよびＱｎを介して電源ラインＶＥＥ２
に多大な電流が流れ（ＤＣバス）、場合によってはチッ
プが劣化あるいは破壊するという可能性がある。However, in the circuit shown in Figure 3, the power supply voltage VEE
When I and VEE2 are supplied, the V-1 characteristics of the diodes DI and D2 change with changes in temperature and power supply voltage, and therefore there is a possibility that the above conditions cannot always be satisfied. In other words, when the output V8 of the ECL gate is at that level, the n-channel MOS transistor Qn is also turned on (malfunction), and the power supply line VEE2 is connected from the ground line GND through the transistors Qp and Qn.
A large amount of current flows through the chip (DC bus), and depending on the case, there is a possibility that the chip may deteriorate or be destroyed.
本発明は、かかる従来技術における課題に鑑み創作され
たもので、温度や電源電圧等の変化にかかわらず常に定
電圧の供給を可能にし、ひいては誤動作の防止を図るこ
とができる定電圧発生回路を提供することを目的として
いる。The present invention was created in view of the problems in the prior art, and provides a constant voltage generation circuit that can always supply a constant voltage regardless of changes in temperature, power supply voltage, etc., and can further prevent malfunctions. is intended to provide.
上記課題を解決するため、本発明によれば、複数の電源
電圧を使用するバイポーラＣＭＯ３回路に定電圧を供給
する回路であって、外部電源電圧のラインに接続された
第１の電源ラインと、該第１の電源ラインと異なる電圧
を有する少なくとも１つの第２の電源ラインと、該第１
および第２の電源ラインの間でダーリントン接続された
複数のトランジスタを有するレベルシフト回路と、該レ
ベルシフト回路における最終段のトランジスタのベース
と一方の電源ラインとの間に接続された抵抗器と、該抵
抗器と他方の電源ラインの間に接続され、該抵抗器に流
れる電流を所定のバイアス電位により制御する回路とを
具備することを特徴とする定電圧発生回路が提供される
。In order to solve the above problems, the present invention provides a circuit that supplies a constant voltage to a bipolar CMO3 circuit using a plurality of power supply voltages, the first power supply line being connected to an external power supply voltage line; at least one second power line having a different voltage than the first power line;
and a level shift circuit having a plurality of transistors Darlington-connected between second power supply lines, and a resistor connected between the base of the final stage transistor in the level shift circuit and one power supply line; There is provided a constant voltage generation circuit characterized by comprising a circuit connected between the resistor and the other power supply line and controlling the current flowing through the resistor with a predetermined bias potential.
上述した構成によれば、抵抗器が接続されている方の電
源ライン（第２の電源ラインとする）の電位は、他方の
電源ライン（第１の電源ライン）の電位から、ダーリン
トン接続された複数のトランジスタの各ベース・エミッ
タ間電圧と、所定のバイアス電位に基づき電流を制御さ
れた該抵抗器における電圧降下により決定される。その
ため、仮に温度が上昇して各トランジスタのベース・エ
ミッタ間電圧が小さくなったり、あるいは外部電源電圧
（第１の電源ラインの電位）が変動しても、抵抗器に流
れる電流が制御されることにより、第２の電源ラインの
電位は安定化される。According to the above-described configuration, the potential of the power supply line to which the resistor is connected (referred to as the second power supply line) is connected to the potential of the other power supply line (the first power supply line) through a Darlington connection. It is determined by the base-emitter voltage of each of the plurality of transistors and the voltage drop across the resistor whose current is controlled based on a predetermined bias potential. Therefore, even if the temperature rises and the voltage between the base and emitter of each transistor decreases, or the external power supply voltage (potential of the first power supply line) fluctuates, the current flowing through the resistor will be controlled. As a result, the potential of the second power supply line is stabilized.
つまり、ＥＣＬゲートと同等の対温度・電源電圧特性を
実現しているため、温度や電源電圧の変化にかかわらず
常に定電圧を供給することが可能となる。そのため、バ
イポーラＣＭＯ３回路における誤動作の可能性を排除す
ることができる。In other words, since it has achieved the same temperature versus power supply voltage characteristics as an ECL gate, it is possible to always supply a constant voltage regardless of changes in temperature or power supply voltage. Therefore, the possibility of malfunction in the bipolar CMO3 circuit can be eliminated.
なお、本発明の他の構成上の特徴および作用の詳細につ
いては、添付図面を参照しつつ以下に記述される実施例
を用いて説明する。Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.
第１図には本発明の一実施例としての定電圧発生回路の
構成が示される。FIG. 1 shows the configuration of a constant voltage generating circuit as an embodiment of the present invention.
図示の回路は大別して、レベルシフト回路ＬＳと、抵抗
器Ｒ１２と、該抵抗器に流れる電流を所定のバイアス電
位（図中ＶＢで示される）により制御する電流制御回路
ＣＳとから構成されている。The illustrated circuit is roughly divided into a level shift circuit LS, a resistor R12, and a current control circuit CS that controls the current flowing through the resistor using a predetermined bias potential (indicated by VB in the figure). .
レベルシフト回路ＬＳは、負の電源ラインＶＥＥＩとＶ
ＥＥ２ （νＥＥ２ ＞ ＶＥＥＩ ） （７）間でダ
ーリントン接続すした２つのトランジスタＴ１１、Ｔ１
２と、トランジスタＴ１１のベース（トランジスタＴ１
２のエミッタ）と電源ラインＶＥＥＩＯ間に接続された
抵抗器Ｒ１１とを有している。また、抵抗器Ｒ１２は、
トランジスタＴ１２のベースと電源ラインＶＥＥＩＯ間
に接続されている。なお、電源ラインＶＥＥＩは外部か
ら供給される電源電圧のラインに接続されている。The level shift circuit LS connects the negative power supply lines VEEI and V
EE2 (νEE2 > VEEI) (7) Two transistors T11 and T1 connected by Darlington between
2 and the base of transistor T11 (transistor T1
2 emitter) and a resistor R11 connected between the power supply line VEEIO and the power supply line VEEIO. Moreover, the resistor R12 is
It is connected between the base of transistor T12 and power supply line VEEIO. Note that the power supply line VEEI is connected to a power supply voltage line supplied from the outside.
電流制御回路ＣＳは、抵抗器Ｒ１２の一端（トランジス
タＴ１２のベース）にコレクタが接続され上記バイアス
電位ＶＢに応答するトランジスタＴ１３と、該トランジ
スタのエミッタおよびベースと電源ラインＶＥＥＩＯ間
にそれぞれ接続された抵抗器Ｒ１３およびＲ１４と、グ
ランドラインＧＮＤ （ＯＶ） とトランジスタＴ１３
のベースの間に直列に接続されたトランジスタＴ１４．
Ｔ１５．Ｔ１６と、トランジスタＴ１５のコレクタ・
ベース間およびベース・エミッタ間にそれぞれ接続され
た抵抗器Ｒ１５，Ｒ１６と、グランドラインＧＮＤとト
ランジスタＴ１４のベースの間に接続された抵抗器Ｒ１
７と、トランジスタＴ１４のベースにコレクタが接続さ
れ所定のバイアス電圧νＣ３に応答するトランジスタＴ
１７ と、該トランジスタのエミッタと電源ラインＶＥ
ＥＩＯ間に接続された抵抗器Ｒ１８とから構成されてい
る。The current control circuit CS includes a transistor T13 whose collector is connected to one end of the resistor R12 (base of the transistor T12) and which responds to the bias potential VB, and a resistor connected between the emitter and base of the transistor and the power supply line VEEIO. transistors R13 and R14, ground line GND (OV) and transistor T13
A transistor T14. connected in series between the bases of T14.
T15. T16 and the collector of transistor T15.
Resistors R15 and R16 are connected between the bases and between the base and emitter, respectively, and resistor R1 is connected between the ground line GND and the base of the transistor T14.
7 and a transistor T whose collector is connected to the base of the transistor T14 and which responds to a predetermined bias voltage νC3.
17, the emitter of the transistor and the power supply line VE
It consists of a resistor R18 connected between EIO and EIO.
なお、抵抗器Ｒ１５，Ｒ１６の抵抗比は、電源ラインＶ
ＥＥＩの電位が変動して上昇した時にトランジスタＴ１
３がカントオフするのを防止できるような値に選定され
ている。Note that the resistance ratio of resistors R15 and R16 is
When the potential of EEI fluctuates and rises, transistor T1
The value is selected to prevent the number 3 from canting off.
上記構成において電源ラインνＥＥ２の電位は、電源ラ
インＶＥＥＩの電位から、トランジスタＴ１１、ＴＩ２
の各ベース・エミンタ間電圧■、と、トランジスタＴ１
３により電流を制御された抵抗器Ｒ１２における電圧降
下により決定される。In the above configuration, the potential of the power supply line νEE2 varies from the potential of the power supply line VEEI to the transistors T11 and TI2.
Each base-eminter voltage ■, and the transistor T1
The current is determined by the voltage drop across resistor R12, whose current is controlled by R12.
温度が上昇した場合、トランジスタＴ１１、Ｔ１２のＶ
ＩＩＥは小さくなるが、それに応じてトランジスタＴ１
３のベース電位ＶＢも上昇するため、該トランジスタＴ
Ｉ３を流れる電流が増加する。その結果、抵抗器Ｒ１に
おける電圧降下が大きくなり、電源ラインＶＥＥ２の電
位は安定する。When the temperature rises, the V of transistors T11 and T12
IIE becomes smaller, but transistor T1 accordingly
Since the base potential VB of the transistor T3 also rises, the base potential VB of the transistor T
The current flowing through I3 increases. As a result, the voltage drop across resistor R1 increases, and the potential of power supply line VEE2 becomes stable.
電源ラインＶＥＲＩの電位が変動（低下）した場合、ト
ランジスタＴ１３のベース電位ＶＢは該グランドライン
の電位に対してほとんど一定であるので、該電位ＶＥＥ
Ｉが低下した分だけトランジスタＴ１３を流れる電流が
増加し、やはり、電源ラインνＥＥ２の電位は安定する
。一方、電源ラインＶＥＥＩの電位が変動（上昇）した
場合には、上記温度が上昇した場合と同様の状態（トラ
ンジスタＴ１１、Ｔ１２の■１が小さくなった状態）と
なるため、やはり、電源ラインＶＥＥ２の電位は安定す
る。When the potential of the power supply line VERI fluctuates (decreases), the base potential VB of the transistor T13 is almost constant with respect to the potential of the ground line, so the potential VEE
The current flowing through the transistor T13 increases by the amount that I decreases, and the potential of the power supply line νEE2 becomes stable. On the other hand, when the potential of the power supply line VEEI fluctuates (increases), the same state as when the temperature rises (the state in which ■1 of the transistors T11 and T12 becomes smaller) occurs, so the power supply line VEE2 The potential of becomes stable.
このように本実施例の回路構成によれば、レベルシフト
回路ＬＳおよび抵抗器Ｒ１２はＥＣＬゲートと同等の対
温度・電源電圧特性を実現しているため、温度や電源電
圧の変化にかかわらず常に定電圧（ＶＥＨ２）を供給す
ることができる。従って、本実施の定電圧発生回路を例
えば第２図に示されるようなバイポー５０Ｍ０３回路に
適用した場合、従来形に見られたような誤動作の可能性
を排除することができる。In this way, according to the circuit configuration of this embodiment, the level shift circuit LS and resistor R12 realize the same temperature and power supply voltage characteristics as the ECL gate, so they can always be used regardless of changes in temperature or power supply voltage. A constant voltage (VEH2) can be supplied. Therefore, when the constant voltage generating circuit of this embodiment is applied to, for example, a bipolar 50M03 circuit as shown in FIG. 2, the possibility of malfunctions seen in the conventional type can be eliminated.
以上説明したように本発明によれば、複数の電源電圧を
使用するバイポー５０Ｍ０３回路に対し、温度や電源電
圧等の変化にかかわらず常に定電圧を供給することがで
きる。これは、バイポー５０Ｍ０３回路における誤動作
の防止に寄与するものである。As described above, according to the present invention, a constant voltage can always be supplied to a bipolar 50M03 circuit that uses a plurality of power supply voltages, regardless of changes in temperature, power supply voltage, etc. This contributes to preventing malfunctions in the bipolar 50M03 circuit.
第１図は本発明の一実施例としての定電圧発生回路の構
成を示す回路図、
第２図はバイポー５０Ｍ０３回路の一構成例を示す回路
図、
第３図は典型的な定電圧発生回路の構成を示す回路図、
である。
（符号の説明）
ＣＳ・・・電流制御回路、ＬＳ・・・レベルシフト回路
、Ｔ１１、Ｔ１２・・・ｎｐｎ型バイポーラトランジス
タ、１？１２・・・抵抗器、ＶＥＥＩ、ＶＥＥ２・・・
電源電圧（ライン）ＶＢ・・・所定のバイアス電位。Fig. 1 is a circuit diagram showing the configuration of a constant voltage generation circuit as an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of the configuration of a bipolar 50M03 circuit, and Fig. 3 is a typical constant voltage generation circuit. This is a circuit diagram showing the configuration of . (Explanation of symbols) CS...Current control circuit, LS...Level shift circuit, T11, T12...npn type bipolar transistor, 1?12...Resistor, VEEI, VEE2...
Power supply voltage (line) VB...predetermined bias potential.
Claims (1)
電圧を供給する回路であって、 外部電源電圧のラインに接続された第１の電源ライン（
ＶＥＥ１）と、 該第１の電源ラインと異なる電圧を有する少なくとも１
つの第２の電源ライン（ＶＥＥ２）と、該第１および第
２の電源ラインの間でダーリントン接続された複数のト
ランジスタ（Ｔ１１、Ｔ１２）を有するレベルシフト回
路（ＬＳ）と、 該レベルシフト回路における最終段のトランジスタ（Ｔ
１２）のベースと一方の電源ラインとの間に接続された
抵抗器（Ｒ１２）と、 該抵抗器と他方の電源ラインの間に接続され、該抵抗器
に流れる電流を所定のバイアス電位（ＶＢ）により制御
する回路（ＣＳ）とを具備することを特徴とする定電圧
発生回路。[Claims] A circuit that supplies a constant voltage to a bipolar CMOS circuit that uses a plurality of power supply voltages, the circuit comprising: a first power supply line connected to an external power supply voltage line (
VEE1) and at least one line having a different voltage than the first power supply line.
a level shift circuit (LS) having a second power supply line (VEE2) and a plurality of transistors (T11, T12) connected in Darlington between the first and second power supply lines; The final stage transistor (T
A resistor (R12) is connected between the base of 12) and one power supply line, and a resistor (R12) is connected between the resistor and the other power supply line, and the current flowing through the resistor is set to a predetermined bias potential (VB ) A constant voltage generation circuit characterized by comprising a circuit (CS) controlled by.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018981A JPH03225402A (en) | 1990-01-31 | 1990-01-31 | Constant voltage generating circuit |
| EP19910300695 EP0440434A3 (en) | 1990-01-31 | 1991-01-30 | Constant voltage generating circuit |
| KR1019910001684A KR920000022A (en) | 1990-01-31 | 1991-01-31 | Constant voltage generator |
| US07/648,849 US5130637A (en) | 1990-01-31 | 1991-01-31 | Constant voltage generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018981A JPH03225402A (en) | 1990-01-31 | 1990-01-31 | Constant voltage generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03225402A true JPH03225402A (en) | 1991-10-04 |
Family
ID=11986786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018981A Pending JPH03225402A (en) | 1990-01-31 | 1990-01-31 | Constant voltage generating circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5130637A (en) |
| EP (1) | EP0440434A3 (en) |
| JP (1) | JPH03225402A (en) |
| KR (1) | KR920000022A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016057962A (en) * | 2014-09-11 | 2016-04-21 | 株式会社デンソー | Reference voltage circuit and power supply circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2806489B1 (en) | 2000-03-15 | 2002-06-28 | St Microelectronics Sa | REFERENCE VOLTAGE SUPPLY CIRCUIT |
| US20150349554A1 (en) | 2014-06-03 | 2015-12-03 | Traxxas Lp | Battery connection method and apparatus |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3781648A (en) * | 1973-01-10 | 1973-12-25 | Fairchild Camera Instr Co | Temperature compensated voltage regulator having beta compensating means |
| US4339707A (en) * | 1980-12-24 | 1982-07-13 | Honeywell Inc. | Band gap voltage regulator |
| US4453121A (en) * | 1981-12-21 | 1984-06-05 | Motorola, Inc. | Reference voltage generator |
| US4446383A (en) * | 1982-10-29 | 1984-05-01 | International Business Machines | Reference voltage generating circuit |
| JPS6269719A (en) * | 1985-09-24 | 1987-03-31 | Toshiba Corp | Level conversion logic circuit |
| JPS62191907A (en) * | 1986-02-19 | 1987-08-22 | Hitachi Ltd | Semiconductor circuit |
| US4794317A (en) * | 1987-12-18 | 1988-12-27 | Texas Instruments Incorporated | ECL-to-CMOS level conversion for use in ECL-BiCMOS circuit |
-
1990
- 1990-01-31 JP JP2018981A patent/JPH03225402A/en active Pending
-
1991
- 1991-01-30 EP EP19910300695 patent/EP0440434A3/en not_active Withdrawn
- 1991-01-31 KR KR1019910001684A patent/KR920000022A/en not_active Application Discontinuation
- 1991-01-31 US US07/648,849 patent/US5130637A/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016057962A (en) * | 2014-09-11 | 2016-04-21 | 株式会社デンソー | Reference voltage circuit and power supply circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| US5130637A (en) | 1992-07-14 |
| EP0440434A3 (en) | 1992-01-15 |
| KR920000022A (en) | 1992-01-10 |
| EP0440434A2 (en) | 1991-08-07 |
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