JP2011228944A - Flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flip-flop circuit that can reduce a power consumption of a semiconductor integrated circuit and reduce a chip area.SOLUTION: A node A as an output terminal of a master latch 1 and a node F as an output terminal of a slave latch 2 are connected to each other by an NMOS transistor NT1 as a pass transistor whose conduction is controlled by a clock signal CK, and a node C as an output terminal of the master latch 1 and a node E as an output terminal of the slave latch 2 are connected to each other by an NMOS transistor NT2 as a pass transistor whose conduction is controlled by the clock signal CK.

Description

  The present invention relates to a flip-flop circuit.

  Since the flip-flop circuit is a basic circuit constituting a sequential circuit, many flip-flop circuits are used in a semiconductor integrated circuit. Therefore, if the number of gates for forming the flip-flop circuit can be reduced, the effect of reducing the number of gates in the semiconductor integrated circuit is great. If the number of gates of the semiconductor integrated circuit can be reduced, the chip area of the semiconductor integrated circuit can be reduced, and advantages such as improvement in manufacturing yield and reduction in chip cost can be obtained.

  Therefore, conventionally, a flip-flop circuit has been proposed in which the number of gates is reduced by sharing a part of the feedback circuit that constitutes each latch between the master latch and the slave latch that constitute the flip-flop circuit. (For example, refer to Patent Document 1).

  By the way, the current consumption during the operation of the CMOS flip-flop circuit is mainly the charge / discharge current of the gate capacitance and drain capacitance of the MOS transistor constituting the circuit. This charge / discharge current depends on the frequency of the input clock and the rate of change of the input data.

  In general, in a logic LSI, the rate at which data input to a flip-flop circuit changes every clock cycle is often about 10% to 30%. Therefore, the average frequency of the input data is about 5% to 15% of the clock frequency. That is, the average frequency of the input data is generally much lower than the clock frequency. For this reason, when reducing the number of gates of the flip-flop circuit, reducing the number of MOS transistors to which a clock is input has a greater effect of reducing current consumption.

  However, the proposed method for reducing the number of gates in the flip-flop circuit is to reduce the number of gates in the data circuit, and that the reduction in the number of gates has little effect on the reduction in the current consumption of the entire semiconductor integrated circuit. There was a problem.

JP-A-7-135449 (page 3-4, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a flip-flop circuit that can reduce the power consumption and the chip area of a semiconductor integrated circuit.

  According to one aspect of the present invention, a first AND-NOR type logic gate circuit to which a data signal is input, and a second AND-NOR type to which its output signal inverted by a first inverter is input. A master latch configured by stakingly connecting logic gate circuits, a third AND-NOR logic gate circuit to which an output signal of the second logic gate circuit is input, and an output of the first inverter A slave latch configured by slidably connecting a fourth AND-NOR type logic gate circuit to which a signal is input, and the first AND-NOR type logic gate circuit and the third AND- A first P-channel transistor to which an output signal of the second AND-NOR logic gate circuit connected to a power supply terminal in parallel with the NOR logic gate circuit is input; A second P-channel transistor to which a clock signal is input is shared, and is parallel to the power supply terminal between the second AND-NOR logic gate circuit and the fourth AND-NOR logic gate circuit. A flip-flop circuit that is connected to a third P-channel transistor to which the output signal of the first inverter is input and a fourth P-channel transistor to which the clock signal is input. And a first N whose conduction is controlled by the clock signal between the output terminal of the second AND-NOR type logic gate circuit and the output terminal of the fourth AND-NOR type logic gate circuit. A channel-type pass transistor is connected, and the clock terminal is connected between the output terminal of the first inverter and the output terminal of the third AND-NOR logic gate circuit. Flip-flop circuit in which the second N-channel pass transistor conduction is controlled by the click signal, characterized in that it is connected is provided.

  According to another aspect of the present invention, a first AND-NOR type logic gate circuit to which a data signal is input and a second output signal to which the output signal inverted by the first inverter is input are provided. A master latch constituted by AND-NOR logic gate circuits connected to each other, a third AND-NOR logic gate circuit to which an output signal of the second logic gate circuit is input, and the first A slave latch configured by slidably connecting a fourth AND-NOR logic gate circuit to which an output signal of the inverter is input; and the first AND-NOR logic gate circuit and the third The first P-channel type transistor to which the output signal of the second AND-NOR type logic gate circuit connected in parallel to the power supply terminal is input to the AND-NOR type logic gate circuit. And a second P-channel transistor to which a clock signal is input are shared, and a power source is connected between the second AND-NOR logic gate circuit and the fourth AND-NOR logic gate circuit. Flip shared by a third P-channel transistor to which the output signal of the first inverter is input and a fourth P-channel transistor to which the clock signal is input, connected in parallel to the terminal One end of a first N-channel type pass transistor whose conduction is controlled by a clock signal is connected to an output terminal of the first AND-NOR type logic gate circuit to be connected to the second AND- A second N-channel type pass transistor whose conduction is controlled by an output signal of the NOR type logic gate circuit, and the second AND-NOR type logic gate; A third N-channel pass transistor connected to an output terminal of the circuit and controlled in conduction by an output signal of the first inverter, and the other end of the first N-channel pass transistor is connected to A fourth N-channel pass transistor connected to an output terminal of the third AND-NOR type logic gate circuit and controlled in conduction by an output signal of the second AND-NOR type logic gate circuit; and 4 and an AND-NOR type logic gate circuit connected to the output terminal of the AND gate and connected in common to a fifth N-channel type pass transistor whose conduction is controlled by the output signal of the first inverter. A flip-flop circuit is provided.

  According to the present invention, it is possible to reduce the power consumption and the chip area of the semiconductor integrated circuit.

1 is a circuit diagram showing an example of the configuration of a flip-flop circuit according to Embodiment 1 of the present invention; FIG. 6 is a circuit diagram illustrating an example of a configuration of a flip-flop circuit according to a second embodiment of the invention. FIG. 6 is a circuit diagram illustrating an example of a configuration of a flip-flop circuit according to a third embodiment of the invention. FIG. 6 is a circuit diagram showing an example of the configuration of a flip-flop circuit according to a fourth embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an example of a configuration of a flip-flop circuit according to a fifth embodiment of the invention. FIG. 10 is a circuit diagram illustrating an example of a configuration of a flip-flop circuit according to a sixth embodiment of the present invention. The circuit diagram of the logic gate level of the flip-flop circuit corresponding to a low voltage operation. FIG. 10 is a circuit diagram illustrating an example of a configuration of a flip-flop circuit according to a seventh embodiment of the invention. FIG. 10 is a circuit diagram illustrating an example of a configuration of a flip-flop circuit according to an eighth embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an example of a configuration of a flip-flop circuit according to a ninth embodiment of the present invention. FIG. 3 is a circuit diagram of a logic gate level of a flip-flop circuit disclosed in the applicant's prior application. The circuit diagram which shows the example of a structure of the flip-flop circuit disclosed by the prior application of the present applicant.

  The flip-flop circuit of the present invention relates to the improvement of the prior application (Japanese Patent Application No. 2010-32560) by the present applicant. Therefore, before describing the embodiment of the present invention, the flip-flop circuit disclosed in the prior application will be described.

  FIG. 11 is a circuit diagram of the logic gate level of the flip-flop circuit disclosed in the above-mentioned prior application.

  The flip-flop circuit shown in FIG. 11 is a D-type flip-flop circuit including a master latch 100 and a slave latch 200.

  The master latch 100 is composed of AND-NOR type composite gates ANR11 and ANR12 that are connected to each other and an inverter IV11 connected to the output of the composite gate ANR12, and the slave latch 200 is composed of an AND-NOR type composite gate ANR21. It is composed of a stacking circuit of ANR22.

  In the master latch 100, the clock signal CK and the output signal A of the composite gate ANR12 are input to the AND gate of the composite gate ANR11, and the data signal D is input to the NOR gate of the composite gate ANR11. Further, the clock signal CK and the output signal C of the inverter IV11 which is an inverted signal of its own output signal A are input to the AND gate of the composite gate ANR12, and the output signal B of the composite gate ANR11 is input to the NOR gate of the composite gate ANR12. Entered.

  In the slave latch 200, the output signal A and the clock signal CK of the composite gate ANR12 are input to the AND gate of the composite gate ANR21, and the output signal C and the clock signal CK of the inverter IV11 are input to the AND gate of the composite gate ANR22. The output signal E of the composite gate ANR21 is input to the NOR gate of the composite gate ANR22, and the output signal F of the composite gate ANR22 is input to the NOR gate of the composite gate ANR21.

  FIG. 12 shows an example in which the flip-flop circuit shown in FIG. 11 is configured as a CMOS circuit, and is an example of a flip-flop circuit devised in order to reduce power consumption in the above-mentioned prior application.

  In the flip-flop circuit shown in FIG. 12, the NMOS transistor N115 to which the clock signal CK is input to the gate terminal is shared between the composite gate ANR11 and the composite gate ANR12 of the master latch 100, and combined with the composite gate ANR21 of the slave latch 200. An NMOS transistor N215 to which the clock signal CK is input to the gate terminal is shared between the gates ANR22. Further, between the master latch 100 and the slave latch 200, a circuit composed of the PMOS transistor P211 and the PMOS transistor P212 is shared, and a circuit composed of the PMOS transistor P214 and the PMOS transistor P215 is shared. Here, the clock signal CK is input to the gate terminals of the PMOS transistor P212 and the PMOS transistor P214.

  In the flip-flop circuit shown in FIG. 12, the current consumed by the change in the level of the clock signal is reduced by reducing the number of transistors to which the clock signal CK is input to the gate terminal.

  The present invention further improves the flip-flop circuit of the prior application of the present applicant shown in FIG. 12 by reducing the number of transistors and power consumption.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  1 is a circuit diagram showing an example of the configuration of a flip-flop circuit according to a first embodiment of the present invention. When the circuit shown in FIG. 1 is compared with the circuit of the prior application shown in FIG. 12, the circuit portion constituted by NMOS transistors N211, N213, and N215 in FIG. 12 is changed to a circuit constituted by NMOS transistors NT1 and NT2 in FIG. It has been converted. By this conversion, the number of transistors in this circuit portion can be reduced by one.

  The NMOS transistor NT1 is a pass transistor connected between the output terminal A (node A) of the composite gate ANR11 and the output terminal F (node F) of the composite gate ANR22, and its conduction is controlled by the clock signal CK. .

  Similarly, the NMOS transistor NT2 is a pass transistor connected between the output terminal C (node C) of the inverter IV11 and the output terminal E (node E) of the composite gate ANR21, and its conduction is controlled by the clock signal CK. Is done.

  Here, the circuit portion constituted by the NMOS transistors N211, N213, and N215 of FIG. 12 operates as follows when the clock signal CK changes to the 'H' (high) level.

  That is, when the clock signal CK changes to the “H” level and the node A is at the “L” level and the node C is at the “H” level, the NMOS transistors N211 and N215 are turned on and the node F is L '(low) level. As a result, the NMOS transistor N214 to which the signal of the node F is input is turned off. Further, the NMOS transistor N213 to which the signal of the node A is input is also turned off because the node A is at the “L” level. Therefore, the node E becomes the “H” level.

  On the other hand, when the node A is at the “H” level and the node C is at the “L” level when the clock signal CK changes to the “H” level, the operation is the reverse of the above-described operation, and the node F becomes “ It becomes H level and node E becomes L level.

  Further, when the clock signal CK is at the “L” level, the NMOS transistor N215 becomes non-conductive. In this case, the node F is controlled at the “L” level by the NMOS transistor N212, and the node E is at the NMOS transistor N214. To control the 'L' level.

  On the other hand, the circuit portion constituted by the NMOS transistors NT1 and NT2 of FIG. 1 operates as follows when the clock signal CK changes to the 'H' (high) level.

  When the clock signal CK changes to the “H” level and the node A is at the “L” level and the node C is at the “H” level, both the PMOS transistors P21 and P22 are non-conductive, that is, the P channel side is off. Therefore, the level of the node A is transmitted to the node F by the NMOS transistor NT1 which is a pass transistor, and the node F becomes the “L” level. Further, the level of the node C is transmitted to the node E by the NMOS transistor NT2 which is a pass transistor. At this time, an instantaneous through current flows through the NMOS transistor N24 until the node F changes to the “L” level. However, when the node F reaches the “L” level, the NMOS transistor N24 becomes non-conductive, and the node E Becomes 'H' level.

  On the other hand, when the node A is at the “H” level and the node C is at the “L” level when the clock signal CK changes to the “H” level, the operation is the reverse of the above-described operation, and the node F becomes “ It becomes H level and node E becomes L level.

  When the clock signal CK is at the “L” level, the NMOS transistors NT1 and NT2 are both non-conductive. In this case, the node F is controlled to be at the “L” level by the NMOS transistor N22. The NMOS transistor N24 controls the “L” level.

  As described above, the circuit portion constituted by the NMOS transistors NT1 and NT2 of this embodiment performs the same operation as the circuit portion constituted by N211, N213, and N215 of the prior application circuit of FIG.

  According to this embodiment, the number of transistors can be reduced by one as compared with the circuit of the prior application shown in FIG.

  FIG. 2 is a circuit diagram showing an example of the configuration of the flip-flop circuit according to the second embodiment of the present invention. The flip-flop circuit of this embodiment is obtained by removing the NMOS transistor N11 from the flip-flop circuit of the first embodiment shown in FIG. Hereinafter, the deletion of the NMOS transistor N11 will be described.

  In the flip-flop circuit according to the first embodiment, the NMOS transistors N15 and N11, as can be seen from the logic circuit diagram of FIG. 11, when the clock signal CK is at “H” level and the node A is at “L” level, Even if the node B changes from the “H” level to the “L” level due to the change of the input signal D and N12 becomes non-conductive, the node A is held at the “L” level.

  On the other hand, in the flip-flop circuit of the first embodiment, when the node A is at the “L” level and the clock signal CK rises to the “H” level, the node F is at the “L” level and the node E is at the “H” level. Thus, the NMOS transistor N22 becomes conductive. As a result, the node A is connected to the ground potential power supply via the NMOS transistor N22 and the NMOS transistor NT1.

  Therefore, even if the NMOS transistor N11 is deleted from the circuit of FIG. 1, the ‘L’ level of the node A is held when the clock signal CK is ‘H’ level.

  According to this embodiment, one transistor can be further reduced from the flip-flop circuit according to the first embodiment.

  FIG. 3 is a circuit diagram showing an example of the configuration of the flip-flop circuit according to the third embodiment of the present invention.

  The flip-flop circuit of the present embodiment is different from the flip-flop circuit of the second embodiment in that a pass transistor whose conduction is controlled by the output signal of the node A instead of connecting one end of the NMOS transistor NT2 to the node C. The point is that the node B is connected via the NMOS transistor NT3. By changing the connection, the NMOS transistor N15 can be eliminated from the flip-flop circuit according to the second embodiment, and the number of transistors to which the clock signal CK is input to the gate terminal can be reduced. This reduction also reduces the total number of transistors. Hereinafter, the change of the connection destination of the NMOS transistor NT2 will be described.

  In a period in which the clock signal CK is at the ‘L’ level, the signal polarity of the node A is related to the inverted polarity of the node B, and the signal polarity of the node C is related to the inverted polarity of the node A. This inversion relationship is valid as long as the clock signal CK changes from “L” to “H” as long as it is within the data hold time with respect to the clock. Therefore, the signal polarities of the node B and the node C are the same within the hold time described above.

  In the circuit of FIG. 2, the node E is changed from the “H” level to the “L” level because the node C is at the “L” level and the clock signal CK is changed from “L” to “H”. The connection between the node E and the node C through the NMOS transistor NT2 can be replaced with the connection between the node E and the node B through the NMOS transistor NT2. In addition, since the node A is at the “H” level within this hold time, the NMOS transistor NT3 whose conduction is controlled by the output signal of the node A is conducting, and the node is connected via the NMOS transistor NT2 and the NMOS transistor NT3. The circuit of FIG. 3 in which E and node B are connected performs the same function.

  In the circuit of FIG. 3, after the node E changes to the “L” level, an instantaneous through current is generated as described in the first embodiment, but the node F changes from the “L” level to the “H” level. Change to level.

  In the circuit of FIG. 3, even if the data hold period elapses after the clock signal CK rises from 'L' to 'H' and the data input signal D changes, the node B and the high voltage power supply In this path, since both the PMOS transistors P24 and P25 are non-conductive, the node B does not become the “H” level. Since the node B is supplied with the 'L' level of the node E through the conducting NMOS transistors NT2 and NT3, the node B has the L 'level during the period when the clock signal CK is at the' H 'level. Retained. Accordingly, the state of the slave latch 2 does not change during the period in which the clock signal CK is at the “H” level after changing at the instant when the clock signal CK rises.

  In the circuit of FIG. 3, when the node B is at the “H” level, the node A is at the “L” level, and the node C is at the “H” level, the clock signal CK changes from “L” to “H”. Since the NMOS transistor NT1 becomes conductive, the node F is pulled to the “L” level by the output of the node A. At this time, since the NMOS transistor NT3 is non-conductive, the node E changes to the 'H' level without causing an instantaneous through current.

  Thereafter, when the data input signal D changes to the “H” level after the lapse of the data hold time, the node B changes to the “L” level. However, since both the PMOS transistors P21 and P22 are non-conductive, the node A continues to maintain the 'L' level due to the 'L' level of the node F supplied via the NMOS transistor NT1. As a result, the node C also keeps the “H” level.

  When the clock signal CK becomes ‘L’, the NMOS transistor NT <b> 2 becomes non-conductive, so that the level of the node B changes depending on the level of the data input signal D. This is equivalent to the operation when the NMOS transistor N15 is turned off in FIG. That is, the flip-flop circuit of this embodiment performs an operation equivalent to that of the flip-flop circuit of the second embodiment.

  According to this embodiment, one transistor can be further reduced from the flip-flop circuit according to the second embodiment. In addition, since one transistor for inputting a clock signal to the gate terminal is reduced, power consumption accompanying a change in the clock signal can be reduced.

  In each of the above embodiments, two pass transistors (NMOS transistors NT1 and NT2) whose conduction is controlled by the clock signal CK have been used. However, in this embodiment, the number of pass transistors is reduced to one. An example is shown.

  FIG. 4 is a circuit diagram showing an example of the configuration of a flip-flop circuit according to Embodiment 4 of the present invention.

  The flip-flop circuit of this embodiment is a pass transistor in which one end of an NMOS transistor NT11 which is a pass transistor whose conduction is controlled by a clock signal CK is connected to the node B and its conduction is controlled by an output signal of the node A. The NMOS transistor NT12 and the pass transistor NMOS transistor NT13 connected to the node A and controlled in conduction by the output signal of the node C are connected in common. The other end of the NMOS transistor NT11 is connected to the node E and connected to the node A. The NMOS transistor NT14 which is a pass transistor whose conduction is controlled by the output signal and the NMOS transistor NT15 which is connected to the node F and whose conduction is controlled by the output signal of the node C are commonly connected.

  In this embodiment, when the clock signal CK is at the “H” level, the node B is at the “L” level, the node A is at the “H” level, and the node C is at the “L” level, the NMOS transistors NT12, NT11, NT14 are Conduction is established and a conduction path is formed between node B and node E. On the other hand, when the clock signal CK is at the “H” level, if the node B is at the “H” level, the node A is at the “L” level, and the node C is at the “H” level, the NMOS transistors NT13, NT11, and NT15 are turned on. Thus, a conduction path is formed between node A and node F.

  As described above, in this embodiment, when the clock signal CK is at the “H” level, a conduction path connecting the node B and the node E or a conduction path connecting the node A and the node F between the master latch 10 and the slave latch 20. Either is always formed. In this embodiment, this conduction path is used to form a feedback loop of the master latch 10 and the data holding operation of the master latch 10 is performed.

  That is, data read to the master latch 10 when the clock signal CK is at the “L” level and transferred to the slave latch 20 when the clock signal CK is at the “H” level are fed back to the master latch 10 through the above-described conduction path, 10 is held.

  According to the present embodiment, since the number of transistors to which the clock signal is input to the gate terminal is one less than that of the flip-flop circuit of the third embodiment, the power consumption accompanying the change of the clock signal is further reduced. can do.

  FIG. 5 is a circuit diagram showing an example of the configuration of a flip-flop circuit according to the fifth embodiment of the present invention.

  In the flip-flop circuit of this embodiment, the NMOS transistor NT12 and the NMOS transistor NT14 replace the connection terminal of the NMOS transistor NT11 with respect to the flip-flop circuit of the fourth embodiment.

  In this embodiment, as in the fourth embodiment, when the clock signal CK is at the “H” level, the node B is at the “L” level, the node A is at the “H” level, and the node C is at the “L” level, the NMOS When transistors NT12, NT11, and NT14 are turned on to form a conduction path between node B and node E, node B is at 'H' level, node A is at 'L' level, and node C is at 'H' level NMOS transistors NT13, NT11, NT15 are rendered conductive, and a conduction path is formed between node A and node F.

  In this embodiment, the same operation as that of the fourth embodiment is performed, and the same effect as that of the fourth embodiment is obtained.

  In each of the above-described embodiments, an example in which the number of NMOS transistors whose conduction is controlled by the clock signal CK is shown. However, in this embodiment, an example in which the number of PMOS transistors is further reduced is shown.

  FIG. 6 is a circuit diagram showing an example of the configuration of a flip-flop circuit according to Embodiment 6 of the present invention. The flip-flop circuit of this embodiment is different from the flip-flop circuit of the fourth embodiment shown in FIG. 4 between the drain terminal of the PMOS transistor P21 and the drain terminal of the PMOS transistor P25 instead of the PMOS transistor P22 and the PMOS transistor P24. In addition, a PMOS transistor PT1, which is a pass transistor whose conduction is controlled by the clock signal CK, is connected.

  In the circuit of FIG. 4, when the clock signal CK is at the “H” level, the PMOS transistors P22 and P24 are non-conductive, and the PMOS transistors P22 and P24 are used to supply the “H” level to the master latch 10 and the slave latch 20. Does not contribute.

  Similarly, in the circuit of FIG. 6, when the clock signal CK is at “H” level, the PMOS transistor PT1 is non-conductive, and the PMOS transistor PT1 contributes to supply of “H” level to the master latch 10 and the slave latch 20A. do not do.

  On the other hand, in the circuit of FIG. 4, when the clock signal CK is at the “L” level, the PMOS transistors P22 and P24 are turned on, and the PMOS transistors P22 and P24 supply the “H” level to the master latch 10 and the slave latch 20. .

  On the other hand, in the circuit of FIG. 6, when the clock signal CK is at “L” level, the PMOS transistor PT1 becomes conductive, and a conduction path is formed connecting the drain terminal of the PMOS transistor P21 and the drain terminal of the PMOS transistor P25. The At this time, since the signals input to the gate terminals of the PMOS transistor P21 and the PMOS transistor P25 are in reverse phase, either the PMOS transistor P21 or the PMOS transistor P25 is always turned on, and the drain terminal thereof is set to the “H” level. Supply. This 'H' level is transmitted to the counterpart drain terminal via the PMOS transistor PT1.

  Accordingly, even in the circuit of FIG. 6, when the clock signal CK is at the “L” level, the “H” level is supplied to the master latch 10 and the slave latch 20.

  According to this embodiment, one transistor can be further reduced from the flip-flop circuit according to the fourth embodiment. In addition, since one transistor for inputting the clock signal to the gate terminal is reduced, it is possible to further reduce power consumption due to a change in the clock signal.

  In the sixth embodiment, an example in which one PMOS transistor is reduced is shown. However, when the clock signal CK is at the “L” level and the node A changes from the “L” level to the “H” level, the node A is the gate terminal. The “H” level is supplied to the node A through the PMOS transistor P25 and the PMOS transistor PT1 input to. Therefore, when the 'H' level supplied to the node A is lowered by the threshold voltage of the PMOS transistor 25 and the power supply voltage is lowered, the operation speed is greatly reduced. Therefore, in this embodiment, an example of a circuit that can reduce the decrease in the operation speed even when the power supply voltage becomes low is shown.

  FIG. 7 is a circuit diagram of the logic gate level of the low-voltage operation-compatible flip-flop circuit in which a countermeasure against the above-described operation speed reduction problem is taken.

  In the circuit shown in FIG. 7, an inverter IV12 that receives the output signal of the node C is added to the master latch 100A as compared with the flip-flop circuit disclosed in the prior application by the applicant shown in FIG. And the output signal of the node AA is input to the AND-NOR type composite gate ANR21 of the slave latch 200 in place of the output signal of the node A.

  FIG. 8 is a circuit diagram showing an example of the configuration of the flip-flop circuit according to the seventh embodiment of the present invention, corresponding to the circuit shown in FIG.

  The circuit shown in FIG. 8 is an inverter IV12 to which a circuit portion constituted by a PMOS transistor P18 and an NMOS transistor N18 is added. The node AA at the output terminal is input to the PMOS transistor P25 and the NMOS transistors NT12 and NT14. Yes.

  Since the PMOS transistor P18 is directly driven by the power supply voltage, the “A” level of the node AA is not lowered, and the operation speed of the flip-flop circuit is improved as compared with driving the load by the output signal of the node A.

  According to such a present Example, even if a power supply voltage becomes low, the fall of operation speed can be decreased.

  FIG. 9 is a circuit diagram showing an example of the configuration of a flip-flop circuit according to Embodiment 8 of the present invention. In this embodiment, the circuit configuration of the seventh embodiment shown in FIG. 8 is replaced in the same manner as in the fifth embodiment.

  That is, the NMOS transistor NT12 and the NMOS transistor NT14 of FIG. 8 are obtained by exchanging the connection terminals with the NMOS transistor NT11.

  Therefore, also in the present embodiment, the same operation and effect as those of the seventh embodiment can be obtained.

  Furthermore, the circuit replacement shown in the seventh embodiment can also be applied to the circuits shown in the first to third embodiments. In the present embodiment, as an example, an example in which the circuit configuration of the first embodiment shown in FIG.

  FIG. 10 is a circuit diagram showing an example of the configuration of a flip-flop circuit according to Embodiment 9 of the present invention.

  Also in this embodiment, the circuit composed of the PMOS transistor P22 and the PMOS transistor P24 of the first embodiment is replaced with the PMOS transistor PT1, and the portion driven by the output signal of the node A in the first embodiment is replaced with the PMOS transistor. It is driven by the output signal of the node AA which is the output terminal of the inverter composed of P18 and NMOS transistor N18.

  According to the present embodiment, the number of PMOS transistors to which the clock signal is input to the gate terminal can be reduced by one as compared with the first embodiment, and the operation speed is reduced even when the power supply voltage is lowered. Can be reduced.

1, 1A, 1B, 10, 10A, 10B Master latch 2, 20, 20A, 20B Slave latch P13, P16, P17, P18, P21-P26, PT1 PMOS transistors N11-N15, N17, N18, NT1-NT3, NT11- NT15 NMOS transistor

Claims (7)

A first AND-NOR type logic gate circuit to which a data signal is inputted and a second AND-NOR type logic gate circuit to which its own output signal inverted by the first inverter is inputted are connected by staking connection. A master latch configured as described above, a third AND-NOR type logic gate circuit to which the output signal of the second logic gate circuit is input, and a fourth AND to which the output signal of the first inverter is input A slave latch configured by stakingly connecting a NOR type logic gate circuit;
The output of the second AND-NOR type logic gate circuit connected in parallel to the power supply terminal between the first AND-NOR type logic gate circuit and the third AND-NOR type logic gate circuit. A first P-channel transistor to which a signal is input and a second P-channel transistor to which a clock signal is input are shared,
An output signal of the first inverter connected in parallel to the power supply terminal is input between the second AND-NOR logic gate circuit and the fourth AND-NOR logic gate circuit. A flip-flop circuit in which a third P-channel transistor and a fourth P-channel transistor to which the clock signal is input are shared,
A first N-channel path whose conduction is controlled by the clock signal between the output terminal of the second AND-NOR logic gate circuit and the output terminal of the fourth AND-NOR logic gate circuit. The transistor is connected,
A second N-channel pass transistor whose conduction is controlled by the clock signal is connected between the output terminal of the first inverter and the output terminal of the third AND-NOR logic gate circuit. A flip-flop circuit characterized by that. The second N-channel pass transistor comprises:
Instead of being connected to the output terminal of the first inverter,
Connected to the output terminal of the first AND-NOR type logic gate circuit via a third N-channel type pass transistor whose conduction is controlled by the output signal of the second AND-NOR type logic gate circuit. The flip-flop circuit according to claim 1. Between the first N-channel pass transistor and the output terminal of the second AND-NOR logic gate circuit,
3. The flip-flop circuit according to claim 2, wherein a fourth N-channel pass transistor whose conduction is controlled by an output signal of the first inverter is connected in series. Instead of the second P-channel transistor and the fourth P-channel transistor, the clock signal is connected between the drain terminal of the first P-channel transistor and the drain terminal of the third P-channel transistor. Is connected to a P-channel pass transistor whose conduction is controlled by
Instead of the output signal of the second AND-NOR logic gate circuit, the output signal of the second inverter obtained by inverting the output signal of the first inverter is input to the first P-channel transistor. The flip-flop circuit according to any one of claims 1 to 3, wherein A first AND-NOR type logic gate circuit to which a data signal is input and a second AND-NOR type logic gate circuit to which an output signal inverted by the first inverter is input are connected to each other. A master latch configured as described above, a third AND-NOR type logic gate circuit to which the output signal of the second logic gate circuit is input, and a fourth AND- to which the output signal of the first inverter is input. A slave latch configured by stakingly connecting a NOR type logic gate circuit;
The output of the second AND-NOR type logic gate circuit connected in parallel to the power supply terminal between the first AND-NOR type logic gate circuit and the third AND-NOR type logic gate circuit. A first P-channel transistor to which a signal is input and a second P-channel transistor to which a clock signal is input are shared,
An output signal of the first inverter connected in parallel to the power supply terminal is input between the second AND-NOR logic gate circuit and the fourth AND-NOR logic gate circuit. A flip-flop circuit in which a third P-channel transistor and a fourth P-channel transistor to which the clock signal is input are shared,
One end of the first N-channel pass transistor whose conduction is controlled by the clock signal is
A second N-channel pass transistor connected to an output terminal of the first AND-NOR type logic gate circuit and controlled in conduction by an output signal of the second AND-NOR type logic gate circuit; Connected to the output terminal of the second AND-NOR type logic gate circuit and connected in common to a third N-channel type pass transistor whose conduction is controlled by the output signal of the first inverter,
The other end of the first N-channel pass transistor is
A fourth N-channel pass transistor connected to an output terminal of the third AND-NOR type logic gate circuit and controlled in conduction by an output signal of the second AND-NOR type logic gate circuit; and 4 and an AND-NOR type logic gate circuit connected to the output terminal of the AND gate and connected in common to a fifth N-channel type pass transistor whose conduction is controlled by the output signal of the first inverter. Flip-flop circuit. One of the connection destinations to which the one ends of the first N-channel pass transistors are connected in common is the fourth N-channel pass transistor instead of the second N-channel pass transistor,
One of the connection destinations to which the other ends of the first N-channel pass transistors are connected in common is the second N-channel pass transistor instead of the fourth N-channel pass transistor. The flip-flop circuit according to claim 5. Instead of the second P-channel transistor and the fourth P-channel transistor, the clock signal is connected between the drain terminal of the first P-channel transistor and the drain terminal of the third P-channel transistor. Is connected to a P-channel pass transistor whose conduction is controlled by
Instead of the output signal of the second AND-NOR logic gate circuit, the output signal of the second inverter obtained by inverting the output signal of the first inverter is input to the first P-channel transistor. The flip-flop circuit according to claim 5 or 6,

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