JP2016076864A - Latch circuit and flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a latch circuit and a flip-flop circuit that can stably operate even when MOS transistors to which a clock signal is input are decreased in number.SOLUTION: A gate circuit 11 has a PMOS transistor P11 which has its source terminal connected to a power supply terminal Vcc and receives a data signal D at its gate terminal. A gate circuit 12 is cross-connected to the gate circuit 11, and has a PMOS transistor P21 which has its source terminal connected to the power supply terminal Vcc and receives, at its gate terminal, an inverted data signal DN from an inverter IV11. A PMOS transistor P3 is connected between drain terminals of the PMOS transistors P11, P21, and receives a clock signal CK at its gate terminal. A PMOS transistor P13 is connected to the PMOS transistor P11 in parallel, and receives, at its gate terminal, an output signal DNN of an inverter IV12 inverting the inverted data signal DN.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a latch circuit and a flip-flop circuit.

  As one configuration form of the latch circuit, the latch circuit includes a first gate circuit to which a data signal and a clock signal are input, and a second gate circuit to which an inverted signal of the data signal and a clock signal are input. There is a configuration in which the output is connected to the input of the other party. The current consumption during the operation of the CMOS latch circuit having such a configuration is high in the charge / discharge current ratio of the MOS transistor to which the clock is inputted in a normal operation with a low data activation rate.

  As a countermeasure, it is effective to reduce the number of MOS transistors to which a clock is input. Therefore, the present applicant has devised and filed a circuit sharing a MOS transistor to which a clock signal is input between the first gate circuit and the second gate circuit constituting the latch circuit.

  However, in the latch circuit sharing the MOS transistor to which the clock signal is input, a hazard occurs due to the delay time of the inverter that generates the inverted signal of the data signal, and the operation may not be performed depending on the manufacturing process and operating voltage conditions. May become stable.

JP 2011-171916 A

  An object of the present invention is to provide a latch circuit and a flip-flop circuit that can perform a stable operation even if the number of MOS transistors to which a clock signal is input is reduced.

  The latch circuit according to the embodiment includes a first gate circuit, a first inverter, a second gate circuit, and a third PMOS transistor, and the second inverter, the fourth PMOS transistor, Is provided. The first gate circuit includes a first PMOS transistor having a source terminal connected to the power supply terminal and a data signal input to the gate terminal. The first inverter inverts the data signal. The second gate circuit includes a second PMOS transistor that is connected to the first gate circuit, the source terminal is connected to the power supply terminal, and the output signal of the first inverter is input to the gate terminal. . The third PMOS transistor is connected between the drain terminal of the first PMOS transistor and the drain terminal of the second PMOS transistor, and a clock signal is input to the gate terminal. The second inverter inverts the output signal of the first inverter. The fourth PMOS transistor is connected in parallel with the first PMOS transistor, and the output signal of the second inverter is input to the gate terminal.

FIG. 3 is a circuit diagram illustrating an example of a configuration of a latch circuit according to the first embodiment. The circuit diagram and logic operation | movement waveform diagram of the logic gate level of the latch circuit of 1st Embodiment. FIG. 3 is a reference circuit diagram for explaining the operation of the latch circuit according to the first embodiment. The figure for demonstrating operation | movement of the latch circuit of 1st Embodiment. A circuit diagram showing an example of composition of a flip flop circuit of a 2nd embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(First embodiment)
FIG. 1 is a circuit diagram illustrating an example of the configuration of the latch circuit according to the first embodiment.

The latch circuit 1 of the present embodiment has a basic configuration similar to the latch circuit of the applicant (Japanese Patent Laid-Open No. 2011-171916) already filed by the applicant, and has a source terminal connected to the power supply terminal Vcc and a data signal D to the gate terminal. Is input to the gate circuit 11 having the PMOS transistor P11, the inverter IV11 for inverting the data signal D, and the gate circuit 11, and the source terminal is connected to the power supply terminal Vcc and the output signal of the inverter IV11 is connected to the gate terminal. A gate circuit 12 having a PMOS transistor P21 to which DN is input, and a PMOS transistor P3 connected between the drain terminal of the PMOS transistor P11 and the drain terminal of the PMOS transistor P21 and to which the clock signal CK is input to the gate terminal. ing. The PMOS transistor P3 is shared by the gate circuit 11 and the gate circuit 12.

  The latch circuit 1 includes an inverter IV13 that inverts the output of the gate circuit 11 and outputs the inverted signal as an output signal Q.

  In addition to the basic configuration described above, the latch circuit 1 of the present embodiment is further connected in parallel with the inverter IV12 that inverts the output signal DN of the inverter IV11 and the PMOS transistor P11, and the output signal DNN of the inverter IV12 is connected to the gate terminal. Is input to the PMOS transistor P13.

  As a result, the gate circuit 11 includes a PMOS transistor P11 to which the data signal D is input to the gate terminal, a PMOS transistor P13 to which the signal DNN is input in parallel to the PMOS transistor P11, and the drain of the PMOS transistor P11. The PMOS transistor P12 is connected between the terminal and the output terminal NA and connected to the gate terminal of the output terminal NB of the gate circuit 12.

  The gate circuit 11 includes an NMOS transistor N11 having a drain terminal connected to the output terminal NA and a data signal D input to the gate terminal between the output terminal NA and the ground terminal VSS, and a drain terminal connected to the NMOS transistor N11. An NMOS transistor N12 connected to the source terminal, the source terminal connected to the ground terminal VSS and the clock signal CK input to the gate terminal, a drain terminal connected to the output terminal NA, a source terminal connected to the ground terminal VSS and to the gate terminal. And an NMOS transistor N13 to which the output terminal NB of the gate circuit 12 is connected.

  The gate circuit 12 includes a PMOS transistor P21 to which a signal DN is input to the gate terminal, a PMOS transistor P21 connected between the drain terminal of the PMOS transistor P21 and the output terminal NB, and an output terminal NA of the gate circuit 11 to the gate terminal. The transistor P22, the NMOS transistor N21 whose drain terminal is connected to the output terminal NB and the signal DN is inputted to the gate terminal, the drain terminal is connected to the source terminal of the NMOS transistor N21, the source terminal is connected to the ground terminal VSS, and the gate terminal An NMOS transistor N22 to which the clock signal CK is input, an NMOS transistor N23 whose drain terminal is connected to the output terminal NB, whose source terminal is connected to the ground terminal VSS, and whose gate terminal is connected to the output terminal NA of the gate circuit 11, Is provided.

  FIG. 2A is a circuit diagram showing the latch circuit 1 of the present embodiment at the logic gate level. In terms of the logic gate level, the gate circuit 11 and the gate circuit 12 are both AND-NOR type composite gates.

  FIG. 2B is a logic operation waveform diagram of the latch circuit 1 of the present embodiment. The latch circuit 1 performs a through operation in which the change of the data signal D appears as it is in the change of the output signal Q while the clock signal CK is H (high level), and the output signal when the clock signal CK is L (low level). A holding operation for holding the value of Q is performed.

  Next, the effect on the circuit operation of the inverter IV12 and the PMOS transistor P13 added in the present embodiment to the latch circuit of the application will be described with reference to FIGS.

  FIG. 3 is a circuit diagram showing an example of the configuration of a latch circuit already filed. In the latch circuit shown in FIG. 3, only the PMOS transistor P11 and the PMOS transistor P12 connected in series are connected between the power supply terminal Vcc and the output terminal NA of the gate circuit 11A.

  In this latch circuit, the data signal D changes from L to H when the clock signal CK is L, the output terminal NA of the gate circuit 11A is H, and the output terminal NB of the gate circuit 12 is L. To do.

  As the data signal D changes from L to H, the PMOS transistor P11 changes from on to off, and the NMOS transistor N11 changes from off to on.

  At this time, the output signal DN of the inverter IV11 changes from H to L with a delay of time Δt1 from the change of the data signal D due to the propagation delay of the inverter IV11. Therefore, the PMOS transistor P21 remains off during the period of Δt1.

  Therefore, even if the PMOS transistor P3 to which the clock signal CK is input is turned on, the current path between the power supply terminal Vcc and the output terminal NA of the gate circuit 11A is cut off. Therefore, during this period, the H level of the output terminal NA of the gate circuit 11A is held by the charge accumulated in the parasitic capacitance C1 of the output terminal NA. The charge Q is expressed as Q = C1 · V, where V is the voltage at the output terminal NA and C1 is the capacitance of the parasitic capacitance C1.

  However, when the NMOS transistor N11 is turned on by the change of the data signal D from L to H, charge sharing is performed between the parasitic capacitance C1 of the output terminal NA and the parasitic capacitance C2 of the NMOS transistor N11 with respect to the charge Q. Will occur.

  As a result, charge is transferred from the parasitic capacitance C1 to the parasitic capacitance C2, and the charge Q is distributed to the parasitic capacitance C1 and the parasitic capacitance C2 according to the capacitance ratio.

  Therefore, the voltage V1 of the output terminal NA after the charge transfer is V1 = C1 / (C1 + C2) · V, and is lower than the initial voltage V, where the capacitance of the parasitic capacitor C2 is C2.

  When the drop in the voltage at the output terminal NA exceeds the threshold value of the inverter IV13, the level of the output Q of the latch circuit that should be originally held also changes from L to H. For this reason, a malfunction may occur in the circuit to which the output Q is connected.

  FIG. 4 shows how the latch circuit 1 of the present embodiment responds to this. In the latch circuit 1 of this embodiment, a PMOS transistor P13 is connected in parallel with the PMOS transistor P11, and a signal DNN obtained by inverting the output signal DN of the inverter IV11 by the inverter IV12 is input to its gate terminal.

  The output signal DNN of the inverter IV12 changes with a delay of time Δt2 from the change of the output signal DN of the inverter IV11 due to the propagation delay of the inverter IV12.

  Therefore, after the data signal D changes from L to H, the output signal DNN of the inverter IV12 remains L during the period of Δt1 in which the output signal DN of the inverter IV11 is H. Therefore, the PMOS transistor P13 remains on during the period of Δt1.

  Thus, unlike the latch circuit of FIG. 3, when the clock signal CK is L, even if the data signal D changes from L to H and the PMOS transistor P11 is turned off, the PMOS transistor P13 causes the power supply terminal Vcc to A current path between the output terminal NA of the gate circuit 11 is maintained.

  Therefore, when the NMOS transistor N11 is turned on by the change of the data signal D from L to H, the parasitic capacitance C2 is charged by the current flowing from the power supply terminal Vcc. Therefore, in this embodiment, the H level voltage of the output terminal NA of the gate circuit 11 is stable.

  According to the present embodiment, in the circuit configuration in which the gate circuit 11 and the gate circuit 12 share the PMOS transistor P3 to which the clock signal CK is input, even if the inverter IV11 that inverts the data signal D has a propagation delay. The level fluctuation due to charge sharing does not occur at the output terminal NA of the gate circuit 11, and the level of the output signal Q during the output holding period can be stably held.

(Second Embodiment)
FIG. 5 is a circuit diagram showing an example of the configuration of the flip-flop circuit of the second embodiment.

  The flip-flop circuit 2 of the present embodiment uses the latch circuit 1 of the first embodiment for the master latch 21 and the slave latch 22.

  In the master latch 21, the data signal D is input to the data input, and a signal obtained by inverting the clock signal CK by the inverter IV21 is input to the clock input.

  In the slave latch 22, the output of the master latch 21 is input to the data input, and the clock signal CK is input to the clock input.

  In the flip-flop circuit 2, the output signal Q changes in synchronization with the rising edge of the clock signal CK.

  According to the present embodiment, since the latch circuit 1 of the first embodiment is used for the master latch 21 and the slave latch 22, the number of PMOS transistors to which a clock signal is input can be reduced and the output can be reduced. The level can be kept stable.

  According to the latch circuit and flip-flop circuit of at least one embodiment described above, stable operation can be performed even if the number of MOS transistors to which a clock signal is input is reduced.

  Moreover, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Latch circuit 11, 12 Gate circuit 2 Flip-flop circuit 21 Master latch 22 Slave latch P11-P13, P21-P22, P3 PMOS transistor N11-N13, N21-N23 NMOS transistor IV11-IV13, IV21 Inverter

Claims (4)

A first gate circuit having a first PMOS transistor having a source terminal connected to a power supply terminal and a data signal input to a gate terminal; a first inverter that inverts the data signal; and the first gate circuit; A second gate circuit having a second PMOS transistor that is connected to each other, has a source terminal connected to the power supply terminal, and an output signal of the first inverter is input to a gate terminal; A third PMOS transistor connected between the drain terminal and the drain terminal of the second PMOS transistor, the clock signal being input to the gate terminal;
A second inverter for inverting the output signal of the first inverter;
A latch circuit, comprising: a fourth PMOS transistor connected in parallel with the first PMOS transistor and having an output signal of the second inverter input to a gate terminal. The first gate circuit comprises:
A fifth PMOS transistor connected between the first PMOS transistor and the first output terminal and connected to the gate terminal of the second output terminal of the second gate circuit;
The second gate circuit comprises:
2. The sixth PMOS transistor connected between the second PMOS transistor and the second output terminal and having the gate connected to the first output terminal. Latch circuit. The first gate circuit comprises:
A first NMOS transistor having a drain terminal connected to the first output terminal and the data signal being input to a gate terminal;
A second NMOS transistor having a drain terminal connected to a source terminal of the first NMOS transistor, a source terminal connected to a ground terminal, and the clock signal being input to a gate terminal;
And a third NMOS transistor having a drain terminal connected to the first output terminal, a source terminal connected to the ground terminal, and a gate terminal connected to the output terminal of the second gate circuit. The latch circuit according to claim 2. A flip-flop circuit using the latch circuit according to any one of claims 1 to 3 as a master latch and a slave latch.

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