JP2990910B2 - Binary parallel squaring multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary parallel squaring multiplier for performing squaring of a binary number by a parallel operation.

[0002]

2. Description of the Related Art A conventional binary parallel multiplier includes a partial product operation circuit for calculating a product of each bit of a binary number (hereinafter, referred to as a partial product), and an equivalent digit (power exponent) of each partial product. (The same value). FIG. 15 is a block diagram of an example of the above partial product operation circuit, FIG. 16 is a block diagram of an example of the above addition circuit, and FIG.
FIG. 7 is a diagram showing a mathematical expression of the calculation contents in FIGS. 15 and 16. In this example, when a 4-bit binary number is represented as “a ₃ a ₂ a ₁ a ₀ ” as a bit string from the upper digit, its square, that is, “a ₃ a ₂ a ₁ a ₀ ” × “a ₃ shows the case of calculating the a ₂ a ₁ a ₀ ". Further, the calculation result (8 bits) represented by _{"p 7 p 6 p 5 p} 4 p 3 p 2 p 1 p 0".

[0005] First, in FIG. 15, a portion with a black circle at the intersection of the matrix means a circuit for obtaining an AND between the horizontal axis and the vertical axis. For example, the intersection of the horizontal axis a ₃ and the vertical axis a ₀ is for obtaining the AND of a ₃ and a _0, partial products, i.e. (a ₃ a ₀₎ of its output and a ₃ and a ₀ Becomes Next, in FIG. 16, a square box indicates an adder, of which 3 inputs and 2 outputs (one of the inputs is the code described in the box)
Represents a full adder 1 and a square of two inputs and two outputs (one of the inputs is a code described in a box) represents a half adder 2, which means that the value in the box is added to the value input by an arrow. . Arrows 3 in oblique directions (diagonal directions) indicate inputs and outputs of addition results (sums), and arrows 4 in the horizontal and vertical directions indicate carry signals. In FIG. 16, the values of the same digit are arranged on a line parallel to the diagonal line. For example lines of _{a 3 a 0, a 2 a} 1, a 1 a 2, a 0 a 3 is 2 ³ digits (output p _3). The formula for the above operation is
As shown in FIG. In FIG. 17, in the term of addition, values having the same numerical value but different orders, for example, a ₃ a ₀ and a ₀ a ₃
Are the same value, so they are sorted with the most significant digits first. For example, and with _{a 3 a 0 + a 0 a} 3 = 2a 3 a 0. In the above example, the 4-bit binary number "a ₃ a ₂ a ₁ a ₀ "
Although the case where a power is calculated is illustrated, the above circuit employs 2
Not only multiplication operation but also multiplication of two arbitrary binary numbers can be obtained. Conventionally, when performing squaring, a general multiplier as described above has been used. Therefore, when performing 4-bit binary squaring, as shown in FIGS. 15 and 16, a partial product operation circuit having 4 × 4 = 16 AND gates and 4 × 3 = 12 And an adder circuit having the adder.

[0004]

As described above, in the prior art, when performing squaring, an ordinary multiplier must be used. In spite of the specialty of squaring, the calculation speed and the circuit are reduced. There is a problem that the complexity of the configuration becomes the same as that of a normal multiplier. SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and takes advantage of the special feature of squaring, thereby making it possible to achieve a binary parallel squaring multiplier having a simpler configuration and capable of performing high-speed calculations. The purpose is to provide.

[0005]

In a binary parallel binary multiplier according to the basic principle of the present invention, when the product of each bit of the same two n-bit binary numbers is a partial product, the partial product Each term of the product is a matrix of partial product terms in squaring in which the same terms of the power exponent as a binary number are arranged on a line parallel to the diagonal, and the partial product terms having the same value are put together. Is a triangular matrix raised by one digit at the position of the exponent exponent, an adder circuit formed by connecting an adder to the position of each partial product term of the triangular matrix, and each of the same two n-bit binary numbers A partial product operation circuit that calculates a partial product corresponding to the triangular matrix among the products of the bits, wherein each of the outputs of the partial product operation circuit is added to the position of the corresponding partial product term of the adder circuit Is configured to be input.
As the adder, for example, a 3-input / 2-output full adder, a 2-input / 2-output half adder, and a carry look ahead adder having a carry-ahead prefetch function can be used.

[0006] In the binary parallel second multiplier of the present invention based on the basic principle described above, in addition to the configuration of the basic principle, the n-bit binary number from the higher digits _{"a n-1 a n-} 2 ... a ₁
a ₀ ”, and the partial product is a _i a _j (0 ≦ i ≦ n−1,0
≦ j ≦ n−1), the partial product of a _{i an −1} (0 ≦ i ≦ n−2) in the partial product operation circuit is given to the addition circuit as a negative value as an output. In the addition circuit, 1 is added to 2 に は (n) digits, and the final digit p _2n-1
Is configured to output a negated value, thereby performing squaring by two's complement notation. It should be noted that “2 ↑ (n)” described in claim 2 indicates 2 to the power of n. That is, 2 ↑ (n) has the content shown by the following (Equation 1). Similarly, the sign of ↑ () indicates the exponent in parentheses.

[0007]

(Equation 1)

[0008]

As shown in FIG. 3, in the matrix of partial product terms in squaring, terms having the same digit (power exponent) as a binary number are arranged on a line parallel to the diagonal from upper left to lower right. A full adder is arranged in accordance with this line to perform addition, which is the adder circuit of the ordinary parallel multiplier shown in the conventional example of FIG. In the matrix of FIG. 3, the same partial product terms of values (eg, a ₃ a ₀ and a ₀ a ₃ , typically a _i a _j = a
_{j ai} ) is a triangular matrix as shown in FIG.
In FIG. 4, the term having a coefficient of 2 is a term obtained by summing the partial product terms having the same value as described above. The term with these coefficients 2 is 2
In the decimal operation, the digit is the same as the value one digit higher, so if the position is raised by one digit, the coefficient can be omitted. FIG. 5 is a matrix in which diagonal rows of 0 are entirely inserted and the coefficient 2 is omitted, and is a matrix equivalent to that of FIG. Further, in FIG. 5, the part to which 0 is added can reduce the term from the upper left to the lower right on a line parallel to the diagonal line without changing the overall value. A triangular matrix is created as shown in Note that in FIGS. 5 and 6, in a binary number, a _i a _i = a _i ² = a _i , so a _i
a _i is displayed as a _i . For example, the partial product term a ₆ a ₆ is a
₆ is displayed.

As described above, the matrix of the partial product terms can be rearranged by considering the specificity of the squaring.
If an adder is connected to the position of each partial product term of the rearranged triangular matrix (FIG. 6), the diagonal addition in the partial product term matrix as shown in FIG. 3 can be performed.
That is, an operation equivalent to the addition of matrices as shown in FIG. 3 can be performed on a triangular matrix as shown in FIG. FIG.
Is an example in a 7-bit binary number. Further, in this case, since the number of input partial product terms only needs to correspond to the triangular matrix, the number of partial product calculation circuits need only correspond to the triangular matrix as shown in FIG.

As described above, in the present invention, the terms of the same partial product are summed up and carried, so that the total number of partial product terms is reduced from the conventional n ² to (n ² + n) / It can be reduced to two. Therefore, the number of hardware elements of the adder circuit and the partial product operation circuit of the squaring multiplier can be reduced to almost half. In addition, by reducing the number of operations as described above, the overall calculation speed can be reduced by about 2 times.
The speed can be doubled.

[0011]

1 and 2 illustrate the basic principle of the present invention .
It is a block diagram for, 1 addition circuit, Figure 2 shows a partial product calculating circuit. In this embodiment, when a 7-bit binary number is represented as “a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ ” as a bit string from the upper digit, its square, that is, “a ₆ a ₅ a _{4 a 3 a 2 a 1 a} 0 "×" a 6 a 5 a 4 a 3 a 2 a 1 a 0 " to indicate a case of calculating, calculation result (14 bits) from the high-order digit" p ₁₃ p ₁₂ p represented by _{11 p 10 p 9 p 8 p} 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 ". In FIG. 1, a square box indicates an adder, of which a three-input two-output square (one of the inputs is the code described in the box) is a full adder 1 and a two-input two-output (one of the inputs is a box). Is the half adder 2
Represents that the value in the box and the value input by the arrow are added. And an arrow 3 in a diagonal direction (diagonal direction)
Indicates an input and an output of the addition result (sum), and an arrow 4 in the horizontal direction indicates a carry signal. The vertical rectangle is 2
Represents a bit carry look ahead adder 5 (adder with carry-ahead function). 51 is the upper input, 52 is the carry of the upper input, 53 is the lower input, 54
Is the carry of the lower input, 55 is the carry output, 56 is the upper sum output, and 57 is the lower sum output. Further, in FIG. 2, a portion where a black circle is attached to the intersection of the matrix means a circuit for obtaining an AND between the horizontal axis and the vertical axis. For example, the horizontal axis a
₃ and the intersection of the vertical axis a ₀ is for obtaining the AND of a ₃ and a _0, becomes the output of the partial product of a ₃ and a _0, that is, (a ₃ a _0).

Next, the operation will be described. First, the principle of the present invention will be described with reference to FIGS. FIG. 3 is a diagram showing a matrix of partial product terms in a general 7-bit squaring, in which the digits (power exponents) as binary numbers are equal on a line parallel to a diagonal line from the upper left to the lower right of the matrix. In the conventional parallel multiplier shown in the conventional example of FIG. 16, an adder circuit performs addition by arranging full adders according to this line. Considering the matrix of FIG. 3 in detail, the same partial product terms of values (eg, a ₃ a ₀ and a ₀ a ₃ , generally a _i a _j
= A _{j ai} ) 21 pairs, generally n (n-1) / 2 pairs. FIG. 4 shows an upper left triangular matrix in which pairs of terms having the same value are put together. In FIG. 4, the term having a coefficient of 2 is a term obtained by summing the partial product terms having the same value as described above. These terms having the coefficient 2 have the same digit in the binary operation as the value one digit higher, so if the position is increased by one digit, the coefficient can be omitted. FIG. 5 is a matrix in which diagonal rows of 0 are entirely inserted and the coefficient 2 is omitted, and is a matrix equivalent to that of FIG. Further, in FIG. 5, the part to which 0 is added can reduce the term from the upper left to the lower right on a line parallel to the diagonal line without changing the overall value. A triangular matrix is created as shown in In FIGS. 5 and 6, a binary number is a _i
because I am ^{_{a i = a i 2 = a}} i, a i a i is displayed as a _i. For example, the partial product term a ₆ a ₆ is displayed as a ₆ . If an adder is connected to the position of each partial product term of the triangular matrix shown in FIG. 6, the adder circuit shown in FIG. 1 is obtained. In FIG. 1, a 2-bit carry look-ahead adder (adder having a carry-ahead function) is connected to the final stage of the addition to prepare the final result of the squaring.

As shown in FIG. 1B, a similar circuit can be formed by connecting two half adders 21 and 22 instead of one carry look ahead adder. In FIG. 1B, the lower half adder 2
2 is sent to the upper half adder 21, and the carry signal 41 to the outside is sent to the upper half adder 2.
1 is output. In a circuit in which two half adders are connected as described above, the carry operation is performed twice in each half adder, that is, twice, so that the entire adder circuit is more complicated than when one carry look ahead adder is used. Although the calculation speed of the above is reduced, there is an advantage that the whole can be constituted by ordinary adder elements.

Further, in the case of the present invention, the number of input partial product terms only needs to correspond to a triangular matrix, so that the number of partial product calculation circuits corresponding to a triangular matrix is also limited, as shown in FIG. I just need. In other words, for a pair of partial product terms having the same value, only one value needs to be calculated.

As described above, according to the basic principle of the present invention, the number of partial product terms is reduced from 49 to 28 by combining and carrying the terms of the same partial product of values. Can be done. In general, the ^two n in the case of the 2 n-bit multiplication (n ² + n) / 2 in can be reduced. Therefore, the number of hardware elements of the adder circuit and the partial product operation circuit of the squaring multiplier can be reduced to almost half. Also, by reducing the number of operations as described above, the overall calculation speed can be approximately doubled. Therefore, in a system requiring only squaring, the efficiency expressed by the product of the complexity and the processing speed can be improved about four times as compared with the case of using a conventional ordinary multiplier.

Next, the configuration of an adder circuit for performing n-bit squaring will be described in detail. binary A of n bits represents a n-bit string _{"a n-1 a n-} 2 ... a 1 a 0" of the bit, the bit string of 2n bits a value obtained by squaring the _{A "p 2n-1 p 2n} -2 ... p ₁ p ₀ ″. Also, expressed as the partial product terms generated when squaring _{A a i a j (0 ≦} i ≦ n-1,0 ≦ j ≦ n-1). Incidentally, since it is ^{_{a i a i = a i 2}} = a i, expressed as these all a _i. The relationship between the above components is represented by the following (Equation 2).

[0017]

(Equation 2)

Further, the full adder F, a to H, 2-bit carry look-ahead adder half adder when expressed as C, they and the partial product term a _i a _j and squaring the result of the output p _i between means connecting Will be described below. Although an abstract connection relationship is originally given, a relative position is fixed two-dimensionally and a connection between elements is defined by the positional relationship in order to facilitate the description below. However, the applicable range of the present invention includes all equivalent connections between elements without being limited to two-dimensional positional relationships. A row in the horizontal direction and a column in the vertical direction are defined as relative positions arranged on a two-dimensional plane of the full adder F, the half adder H, and the carry look ahead adder C. The rows or columns of F, H, and C are called adder rows or adder columns. Each adder row is numbered from the bottom in order with the first as 1, and similarly, each adder row is numbered from the left with the first as 1. For example, F ₁ , ₂ indicates a full adder in the first row from the bottom and the second column from the left. Generally,
F _i , _j , H _i , _j , and C _i , _j . The full adder F has three inputs and two outputs, and the outputs are called “carry” and “sum”. Note that two of the three inputs are indicated by arrows, and the other one is indicated by a code in a box. The half adder H is obtained by removing one input from the full adder F. The carry look-ahead adder C has four inputs and three outputs, and there are two types of four inputs: upper two inputs and lower two inputs, and the outputs are called “carry”, “lower sum”, and “higher sum”. The above F, H, and C are collectively called a box (Box), and are represented by B.
Therefore, B _i , _j is the i-th from the bottom of the two-dimensionally arranged adder matrix.
Represents F, H or C in row, jth column from left.

Hereinafter, a specific example will be described. First, FIG. 7 shows an addition circuit of a 1-bit squarer. In this case, since a ₀ × a ₀ = a ₀ ² is simply calculated, a ₀ (meaning a ₀ a ₀ as described above) is connected to p ₀ .

FIG. 8 shows an adder circuit of a 2-bit squarer. In this case, 1 bit 2 shown in FIG.
Includes a multiplier, further connects the 0 to p _1. B ₁ , ₁ is a half adder H, whose inputs are given a ₀ a ₁ and a ₁ (meaning a ₁ a ₁ as described above), the sum output of which is given as p ₂ , and the carry output thereof is given as p ₃ Is connected to The above two-bit operation is represented by the following operation expression. The addition result (a ₁ a ₁ 2 a ₁ a ₀ a a
In ₀ a _0), it is _{a 1 a 1 = a 1,} a 0 a 0 = a 0, and 2a ₁ a ₀ is equal to the increased one digit a ₁ a _0. Therefore, when the addition result is arranged, it becomes as shown in the section after the arrangement. The circuit in FIG. 8 corresponds to the formula after the above rearrangement. In the present invention, by performing the above arrangement, the number of constituent elements is reduced, and the number of calculations is reduced accordingly, thereby improving the calculation speed. The principle described in FIG. 8 is basically the same even in the case of more bits.

FIG. 9 shows an adder circuit of a 3-bit squarer. In this case, two half adders H and one carry look ahead adder C are added to the 2-bit square multiplier shown in FIG. Then, connect as follows. H ₁ is included in the 2-bit multiplier, _one solves the joint between the carry output and p _3, the output and a ₀ a ₂ and H _{1, 2} inputs, H _{1, 2} of the sum output p ₃ And H _1, connecting _two carry output to the lower input of C _{2, 3.} Input of H _{2, 2} is set to two inputs of a ₁ a ₂ and a _2, H _{2, 2} of the sum output connecting to the lower input of _{C 2, 3, H 2,} 2 of the carry output C _{2, 3} Connect to the upper input of. Let the lower sum output of C ₂ , _{3 be} p ₄ and the upper sum output be p ₅ . Next, FIG. 10 shows an adder circuit of a 4-bit squarer.
Is an addition circuit of a 5-bit squarer, and FIG. 12 is an addition circuit of a 6-bit squarer. Hereinafter, the configuration of the adder circuit in the squaring device of four or more arbitrary bits will be described. (A) When the number of bits n is 4 or more, B _i ,
_{i + 1} is a carry look ahead adder C, and its lower sum output is p _2i , its upper sum output is p _{2i + 1} , and
For <n−2, the carry output of C at B _i , _{i + 1} is connected to the lower input of C at B _{i + 1} , _{i + 2} . Less than,
Similarly, when n ≧ 4, j> 2 and j ≠ i, generally (b) the input of B _ij is the carry output of B _i , _j−1 and
The sum output of B _{i + 1} , _j-1 and a _j-1 a _i , j if j is even
There a a _j a _i-1 if an odd number, and the three-input. Also, B
the carry output of the _ij is the input of B _{ij + 1,} a sum output B _i-1,
Connected to _{j + 1} input. (C) When j ≦ 2 and i is odd, B _i , ₁ and B _i , ₂
Is a half adder H, and the inputs of B _i , ₁ are a ₀ a _i and a ₁
a _i-1 . The carry output of B _i , ₁ is B _i , ₂
The inputs, the sum output is connected to the input of B _{i-1, 2.} The inputs of B _i , ₂ are _two inputs, the carry output of B _i , ₁ and a ₁ a _i . The carry output of B _i , _{2 is} the input of B _i , ₃ , and the sum output is B
_i-1 and ₃ are connected. (D) When j ≦ 2 and i is an even number, B _i , ₁ does not exist, B _i , ₂ is a half adder H, and the input of B _i , ₂ is a
_{2 ai-1} and the sum output of B _{i + 1} , ₁ . Carry output of B _{i, 2} is the input of B _i3, sum output is connected to the input of B _{i-1, 3.} (E) When 1>i> n−1 and j = i, B _i , _i is a full adder F, and the inputs of B _i , _i are a _i and the carry output of B _i , _i−1 , B _{i + 1} , _i−1 . B _i, the carry output of the _i is B _i, the upper input of _{i + 1,} the sum output is connected to the lower input of B _{i, i + 1.} (F) at i = n-1, when i is an even number, B _{n-1, 1} is _{absent, B n-1, 3,} B n-1, 5, ......, B n-1, n _-2 is a half adder H, and these inputs are two inputs of carry output of B _n-1 and _j-1 and a _{j-1 an -1} . B _n-1 , ₃ , B
The carry outputs of _n-1 , ₅ ,..., _Bn-1 and _n-2 are connected to the inputs of _Bn-1 and _{j + 1} , and the sum output is connected to the inputs of _Bn-2 and _{j + 1} . Also,
B _n−1 , ₂ , B _n−1 , ₄ , B _n−1 , ₆ ,... Among B _n−1 and _n−3
n-1 and ₂ are half adders H, and all others are full adders F. Of the above, B which is half adder H
The inputs of _n-1 and ₂ are _two inputs of an _{-1 aj-1} and an _{-2 aj,} and the other inputs of the full adder F are an _{-1 aj-1} and
There are three inputs: an _{-2 aj} and carry outputs of _Bn-1 and _j-1 . The sum output of each of the above elements is connected to the input of B _n−2 , _{j + 1} , and the carry output is connected to the input of B _n−1 , _{j + 1} . Further, B _n-1 and _n-1 are full adders F, and this input is a
_n-1 and a _n-2 a _n-1 and the carry output of B _n-1 and _n-2
Input. Sum output of the B _{n-1, n-1} is the lower input of B _{n-1, n,} the carry output is connected to the upper input of B _{n-1, n.} (G) When i = n−1 and i is an odd number, B _n−1 , ₁ , B
_{Of the n-1} , ₃ ,..., B _n-1 , _n-3 , B _n-1 , ₁ is a half adder H, and the others are full adders F. Of the above, the input of B _n-1 , ₁ which is the half adder H is a _j-1
a _n-1 and a two-input and a _j a _n-2, the input of the other of the full adder F is provided with a _j-1 a _n-1, and a _j a _n-2, B
_n-1 and _j-1 carry outputs. The sum output of each element is connected to the input of B _n-2 , _{j + 1} , and the carry output is connected to the input of B _n-1 , _{j + 1} . further,
B _n−1 , ₂ , B _n−1 , ₄ ,..., B _n−1 and _n−2 are half adders H
And these inputs are two inputs: a _{j-1 an -1} and carry outputs of B _n-1 and _j-1 . Their sum output is B
_The carry output is connected to the input of _n-2 , _{j + 1} , and the carry output is connected to the input of _Bn-1 , _{j + 1} . _{Also, B n-1, n-} 1 is the full adder F, this input, a a _n-1, a and _{n-2 a n-1,} B n-1, 3 of the carry output of the _n-2 Input. Sum output of the B _{n-1, n-1} is the lower input of B _{n-1, n,} the carry output is connected to the upper input of B _{n-1, n.}

Next, FIG. 13 is a block diagram of one embodiment of the present invention. This embodiment is a squaring multiplier for performing an operation by two's complement notation, and shows a case of 7 bits corresponding to FIG. In FIG. 13, the sign of “” added to the sign of the partial product is a value obtained by negating the partial product (inverted signal). For example, 'a ₃ a ₆ ' is a ₃ a ₆
Is "1" when it is "1" and "1" when it is "0". Further, in FIG. 13, the output of the carry look-ahead adder C for outputting the last digit p ₁₃ has become a negative output, and digit p _7, that is, the 2 ⁷ digit is "1" is added . Otherwise, it is the same as FIG. In the general case, the basics of the invention described so far
The complement operation can be performed by changing the square multiplier according to the principle as follows. That is, n bits 2
Decimal The expressed as _{"a n-1 a n-} 2 ... a 1 a 0" from the upper digit, the partial product _{a i a j (0 ≦ i} ≦ n-1,0 ≦ j ≦ n-
In the case of 1), among the partial products output from the partial product calculation circuit, the partial product of a _{i an -1} (0 ≦ i ≦ n−2) is obtained by adding the negated value to the addition circuit as an output. To the appropriate places. In the addition circuit, 2１ (n) digit is 1
Is added. The output of the last digit p _2n-1 is a value obtained by taking a negation. In the following, complement operation can be performed by the above configuration.
Will be described in detail. n-digit two's complement representation was used
Binary number _{a n-1 a n-2} ... value of a ₁ a ₀ is ^{_{-a n-1 2 n-1}} + a
_n−2 2 ⁿ⁻² +... + a ₁₂ + a ₀ . Therefore n digits
The square of the number of, i.e., _{a n-1 a n-2} ... a 1 a 0 and a _n-1 a _n-2
… A ₁ a ₀ multiplied by Becomes Of these, negative terms are converted to two's complement notation.
Then Becomes The difference between complement multiplication and absolute multiplication is
Is only the negative term of
Number multiplication can be realized. Add both negative terms above to overflow
Excluding the low digits, When this correction term is applied to squaring, Becomes Where the addition of the constant 1 to the p _2n-1 digits is
Since there is no need to consider, the output of p _2n-1 is exclusive of 1
You have to take the logical sum and take the negation as a result
Will be. Therefore, in the circuit configuration shown in this embodiment,
In this case, it is possible to calculate a square by two's complement operation.
You.

FIG. 14 is a block diagram showing an application example of the square multiplier of the present invention. In this example, the squaring multiplier of the present invention is used for an acoustic signal enhancer.
cer). In FIG. 14, reference numeral 10 denotes a microphone that converts an acoustic signal into an electric signal, 11 denotes an A / D converter that converts an analog signal into a digital signal, 1
2 is a parallel squaring multiplier of the present invention, 13 is a D / A converter for converting a digital signal into an analog signal, 14 is an amplifier, 1
A speaker 5 converts an electric signal into an acoustic signal. The acoustic signal enhancer as described above is a circuit that amplifies a strong signal more strongly in an inputted acoustic signal, and reduces a weak signal as noise. By using the squaring multiplier of the present invention as the parallel squaring multiplier 12 of such a circuit, the configuration is simpler and less expensive than in the prior art, and the operation speed can be increased.

[0024]

As described above, according to the present invention, in the matrix of the partial product terms of the squaring of n-bit binary numbers, the terms of the same partial product having the same value are put together and carry is carried out. The total number of partial product terms is changed from the conventional n ² (n ² +
n) / 2. Therefore, the number of hardware elements in the partial product calculation circuit and the addition circuit of the squaring multiplier can be reduced to nearly half. By reducing the number of operations as described above, the overall calculation speed can be approximately doubled. Thus, in only two multiplications are required systems, as compared to when using conventional normal multipliers such as, together with the complexity and represented by the product of the processing speed efficiency can be improved to about 4 times, 2 it is possible to perform the complement of the squaring by the processing of input and output signals is facilitated, good that
The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the basic principle of the present invention,
3 shows an addition circuit of a bit binary number multiplier.

FIG. 2 is a block diagram showing the basic principle of the present invention,
4 shows a partial product calculation circuit of a bit binary number multiplier.

FIG. 3 is a diagram showing a matrix of 7-bit binary partial product terms for explaining the principle of the present invention.

FIG. 4 is a diagram showing a triangular matrix in which terms of the same value in the matrix of FIG. 3 are summarized.

FIG. 5 is a diagram showing a triangular matrix in which a value with a coefficient 2 is shifted by one digit in the triangular matrix of FIG. 4;

FIG. 6 is a diagram showing a triangular matrix in which a portion to which 0 is added is packed from the upper left to the lower right in the triangular matrix of FIG. 5;

FIG. 7 is a block diagram illustrating an example of an addition circuit in a 1-bit squaring multiplier.

FIG. 8 is a block diagram showing an example of an addition circuit in a 2-bit squaring multiplier.

FIG. 9 is a block diagram illustrating an example of an addition circuit in a 3-bit squaring multiplier.

FIG. 10 is a block diagram showing an example of an addition circuit in a 4-bit squarer;

FIG. 11 is a block diagram showing an example of an addition circuit in a 5-bit squarer;

FIG. 12 is a block diagram showing an example of an addition circuit in a 6-bit squarer;

FIG. 13 is a block diagram of an embodiment of the present invention, showing an adder circuit in the case of performing an operation by two's complement notation in squaring a 7-bit binary number.

FIG. 14 is an application example diagram of the present invention, showing a case where the parallel squaring multiplier of the present invention is used for an acoustic signal enhancer.

FIG. 15 is a block diagram showing a partial product operation circuit of a conventional 4-bit binary multiplier.

FIG. 16 is a block diagram showing an addition circuit of a conventional 4-bit binary multiplier.

FIG. 17 is a view showing an operation expression of the operation contents in FIGS. 15 and 16;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Full adder F 2 ... Half adder H 3 ... Input / output signal 4 ... Carry signal 5 ... Carry look ahead adder C 51 ... Upper input 52 ... Upper input carry 53 ... Lower input 54 ... Lower input carry 55 ... Carry output 56 ... Upper sum output 57 Lower sum output 10 Microphone 11 A / D converter 12 Parallel squaring multiplier 13 of the present invention 13 D / A converter 14 Amplifier 15 Speaker

Claims (1)

(57) [Claims] When the product of each bit of the same two n-bit binary numbers is defined as a partial product, each term of the partial product is converted into a binary number whose power exponent is the same as a diagonal line. When a matrix of partial product terms in squaring arranged on a line is used, the partial product terms having the same value are put together, and the summed up term is a triangular matrix raised by one digit at the position of the exponent, the triangular matrix And an adder circuit formed by connecting an adder to the position of each partial product term, and a partial product for calculating a partial product corresponding to the triangular matrix among products of each bit of the same two n-bit binary numbers And an arithmetic circuit, wherein each output of the partial product arithmetic circuit is input to an adder at a position of a corresponding partial product term of the adder circuit , and the n-bit binary number is converted from a high-order digit to “ a _n-1 a _n-2
.. A ₁ a ₀ ”, and the above partial product is represented by a _i a _j (0 ≦ i ≦
when n-1,0 ≦ j ≦ n- 1) and, a _i a _n-1 in the partial product calculating circuit (0 ≦ i ≦ n-
The partial product of 2) is obtained by taking the negated value as an output
In the above-mentioned addition circuit, 1 is added to 2 ↑ (n) digits.
The output of the last digit p _2n-1 is the value obtained by taking the negation
By configuring such that, 2, characterized by performing two multiplication by 2's complement
Hexadecimal parallel 2 multiplier.