JP3153656B2 - Multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier using the Booth algorithm. 2. Description of the Related Art In recent years, computers have been used in various fields, and their performance has been demanded to be improved. In particular, an arithmetic unit that greatly affects the performance of a computer is required to increase the processing speed and reduce the amount of data.

[0002]

2. Description of the Related Art In a conventional multiplier using the Booth algorithm, when performing a binary multiplication, each of the generated partial products is sign-extended and then CSA (Carry Save A).
dder) tree, and the resulting thumb and carry are transferred to the CPA (CarryPropagate Ad).
der), the sum of Sam and Carry was obtained to finally obtain the product.

[0003]

Since such a conventional multiplier uses the Booth algorithm, there is an advantage that the number of circuits can be reduced to some extent as compared with other multipliers. . However, there is a problem that the physical quantity and the number of circuit stages are slightly too large due to the simple structure.

The present invention has been made in view of such a conventional problem, and a CSA tree is constructed so that the input to an adder provided at the last stage of each digit becomes two inputs. Bit which is input to CPA directly from 2 inputs
An object of the present invention is to realize the reduction of the amount of the multiplier and the number of circuit stages by creating P / G.

[0005]

According to the present invention, the above objects are achieved by the means as set forth in the appended claims.

That is, according to the present invention, a partial product generating section for generating a partial product of a multiplicand and a multiplier in accordance with the Booth algorithm, a CSA tree section for calculating a carry and a sum of each digit from the generated partial product, A CPA unit for calculating the product of the multiplicand and the multiplier by adding the carry and the sum of the CSA tree.
A two-input, two-output adder is provided at the last stage of each digit. If two inputs to the last-stage adder at the n-th digit are A _n and B _n , A _n and B _n , A _{n + 1} , B
_This is a multiplier provided with a circuit that receives _{n + 1} and generates a Propagation bit P _n and Generation bit G _n of the n-th digit.

[0007]

The multiplier using the Booth algorithm generates a plurality of partial products according to the number of bits of the multiplier. Then, each partial product is shifted by a required number of bits, and the sum of all values for each digit is defined as the final product. In addition, in the addition, a multi-input adder, that is, CSA
Use a tree. The number of stages in the CSA tree is determined by the number of partial products (the number of inputs).

The output of the CSA tree becomes the input of the CPA, but the CSA tree is constructed so that the last stage of the CSA tree has two inputs. Then, without passing the two inputs to the final stage to the two-input CSA as in the related art,
Bit-P / G which is the input to A (Pro-
By passing (page / generation) directly to another circuit that is directly formed, the amount of material and the number of circuit stages can be reduced (speeding up).

FIG. 1 is a diagram for explaining the principle of the present invention. One four-input circuit 1 shown in FIG. 1A operates similarly to the combination of the two two-input circuits 2 and 3 shown in FIG. 1B. When the four-input circuit 1 shown in FIG. 1A is used, it is possible to reduce the number of gates and the number of circuit stages.
This will be described in detail in Examples.

According to the present invention, a two-input CSA to be provided at the last stage of the CSA tree is removed. Therefore, the physical quantity can be reduced, and at the same time, the number of circuit stages is reduced. further,
The delay time of signals passing through the critical path is reduced,
Multiplication speeds up. It should be noted that the present invention can achieve a great effect when used in combination with the technique of the “multiplier” (filed on September 13, 1990), which has already been applied for a patent.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of 8-bit by 8-bit integer multiplication will be described below. First, a method of generating a partial product according to the Booth algorithm will be described. Here, two methods will be described, a first method of simply sign-extending and a second method disclosed in the invention of the "multiplier" for which a patent application has already been filed.

As shown in FIG. 2, by passing an 8-bit multiplier through a Booth decoder, G1 to G5 indicating magnification are displayed.
To obtain the decoded signal. Further, a partial product is obtained from the magnification of G1 to G5. Then, the obtained five partial products are shifted and arranged by 2 bits and input to the CSA tree.

FIG. 3 shows a partial product generated by the first method of sign extension. In FIG. 3, S ₁ is G
The sign of the partial product generated at a magnification of _1
1 is sign extended to the most significant digit of the CSA tree. 'H' is HOT-BIT. HOT-
BIT is a correction bit that is set when the magnification is -1 or -2.

FIGS. 5 to 7 show examples of the configuration of the CSA tree in the case of sign extension in FIG. As shown, the CSA tree can be constituted by adders 10 to 42 of three inputs or two inputs. 3-input or 2-input adder 1 shown
0 to 42 are CSs for calculating two outputs of sum and carry.
A. In the drawing, the path indicated by the dotted line is a critical path representing the operating speed of the CSA tree.

FIG. 4 shows a partial product generated by the second method based on the invention of the "multiplier".
In FIG. 4, E ₀ and E ₁ are extension bits disclosed in the invention of the “multiplier”. These extension bits E ₀ , E
By using ₁ , the number of inputs to the CSA tree as well as the number of gates for sign extension can be reduced.

The CS in FIG. 4 when the number of inputs is reduced
8 to 10 show configuration examples of the A tree. Again, C
The SA tree is composed of adders 50 to 84 of three inputs or two inputs. By the way, the fifth digit shown in FIG. 9 can be composed of three 3-input CSAs, but in the example of FIG. 9, two 3-input CSAs 63 and 64 and two 2-input CSAs 65 and 66, That is, a total of four CSA 63 ~
The number of gates used is reduced. Thus, even if the number of CSAs at the fifth digit is increased by one, the number of CSAs passing through the critical path of this CSA tree indicated by the dotted line does not change.

The CSA tree shown in FIGS.
Also, the CSA tree shown in FIG.
We are devised to be SA. In addition, even when it is sufficient to use a three-input CSA, two final CSAs are used by using two two-input CSAs. 8 to 10, the twelfth and subsequent digits are omitted, but these are the same as those of the twelfth and subsequent digits shown in FIG.

The final product can be obtained by adding the sum and carry output from the CSA tree using CPA. FIG. 11 is a diagram illustrating an example of calculating a product by CPA. CPA in Figure 11, and the n-th digit of the sum S _n of CSA tree outputs, a carry C _{n + 1} of the (n + 1) digit to full adder, and calculates the n-th digit of the product P _n.

By the way, if two inputs to the final stage CSA are A and B,

(Equation 1) And the input to the CPA, Bit-P / G, is

(Equation 2) It is. However, n = 0 to 15.

This Bit-P / G (Pro unit in bit units)
page / Generation) logic is NO
By optimizing the use of NOR gates in technologies where R-gates are enabled (fast or small) and using AND gates in technologies where AND-gates are enabled, the number of circuit stages and the number of gates can be reduced. it can.

The four-input two-output circuits 90 and 9 shown in FIG.
1 is for inputting the above A and B and outputting the above P and G. On the other hand, the two-input two-output circuits 100 to 102 provided in the last stage of the CSA tree shown in FIG.
, And outputs a sum and a carry. Two-input two-output circuits 103 and 104 provided in the next stage
Is for inputting a thumb and a carry and outputting the above P and G.

Comparing the physical quantities, the case of FIG. 12 using one 4-input, 2-output circuit for each digit is greater than the case of FIG. 13 using two 2-input, 2-output circuits for each digit. This is advantageous because the number can be reduced. FIG. 12 is more advantageous in terms of operating speed, that is, the number of circuit stages. Each of the CPAs 92 and 105 shown in FIGS. 12 and 13 receives the above P and G and obtains a product that is a result of multiplication of the multiplicand and the multiplier.

[0023]

As described above, according to the present invention,
The load (delay time) of the critical path in the CSA tree can be reduced, and the operating speed of the multiplier can be increased. In addition, since the number of gates used is reduced, the amount of the multiplier can be reduced, which greatly contributes to improving the performance of the computer.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention.

FIG. 2 illustrates a booth decoder.

FIG. 3 is a diagram illustrating an example of a method of adding partial products.

FIG. 4 is a diagram illustrating another example of a method of adding partial products.

FIG. 5 is a diagram illustrating a configuration example of a CSA tree that performs addition of partial products illustrated in FIG. 3;

FIG. 6 is a view following FIG. 5;

FIG. 7 is a view following FIG. 6;

8 is a diagram illustrating a configuration example of a CSA tree that performs addition of the partial products illustrated in FIG. 4;

FIG. 9 is a view following FIG. 8;

FIG. 10 is a view following FIG. 9;

FIG. 11 is a diagram illustrating an example of calculating a product by CPA.

FIG. 12 is a diagram showing an embodiment using a four-input circuit.

FIG. 13 is a diagram showing a conventional example using a two-input circuit.

[Explanation of symbols]

1,3,90,91,103,104 Bit-P / G
Generation circuit 2,10-42,50-84,100-102 CSA 92,105 CPA

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yozo Nakayama 4-49 Fukami Nishi, Yamato-shi, Kanagawa Prefecture PFY Yamato Factory Co., Ltd. (56) References JP-A-63-241634 (JP, A) Kaihei 3-177922 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 7/52 310

Claims (1)

(57) [Claims] 1. A partial product generator for generating a partial product of a multiplicand and a multiplier according to a Booth algorithm, a CSA tree unit for calculating a carry and a sum of each digit from the generated partial product, a carry and a sum of each digit. And a CPA unit for calculating the product of the multiplicand and the multiplier by adding the CSA tree, wherein the CSA tree unit includes a 2-input / 2-output adder at the last stage of each digit. , two inputs of the a _n to the adder of the final stage in the first digit n, when the B _n, a _n, B _n, enter the a n _{+ 1,} B n _{+ 1,} the n-th digit Pr
Opagation bits P _n and Generator
A multiplier provided with a circuit for generating n bits _Gn .