CN110851110B - Divider-free divide-by-three circuit - Google Patents
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Abstract
The invention discloses a divider-free three-division circuit.A binary number adder in the circuit is used for adding binary numbers located in even-numbered positions in binary data to obtain an addend Esum. The Osum adder is used for adding each binary number of the binary data, wherein the binary numbers are odd-numbered, so that the addend Osum is obtained. The first multiplexer is used for comparing the addend Esum with the addend Osum, if the addend Esum is larger than or equal to the addend Osum, the difference between the addend Esum and the addend Osum is calculated, the difference between the addend Esum and the addend Osum is output, if the addend Esum is smaller than the addend Osum, the difference between the addend Osum and the addend Esum is calculated, the difference is shifted by 1 bit to the left, and therefore twice of the difference between the addend Osum and the addend Esum is obtained and output. The divider-free three-division circuit can save hardware resources and reduce power consumption and cost.
Description
Technical Field
The present invention relates to the field of circuit design, and more particularly to a divider-less divide-by-three circuit.
Background
In an integrated circuit, a divider or a divide-by-three circuit is commonly used when performing a divide-by-three operation. Dividers or divide-by-three circuits typically consume more resources, power, and cost. The inventor finds that in some integrated circuit fields, such as the field of RFID tag chips, the hardware resources are severely limited, and the cost and power consumption of the circuit are high, so that the divider or the divide-by-three circuit is not suitable for performing the divide-by-three operation.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a divider-free three-division circuit which can save hardware resources and reduce power consumption and cost.
To achieve the above object, the present invention provides a divider-less divide-by-three circuit, which comprises: the system comprises an Esum adder, an Osum adder and a first multiplexer. The Esum adder is used for adding each binary number located at even number in the binary data to obtain an addend Esum. The Osum adder is used for adding each binary number of the binary data, wherein the binary numbers are located at odd-numbered positions, so that an addend Osum is obtained. First multiplexer with the Esum adder all links to each other, is used for the comparison addend Esum with addend Osum, if addend Esum more than or equal to addend Osum then calculates addend Esum with the difference of addend Osum, and will addend Esum with the difference of addend Osum is exported, if addend Esum is less than addend Osum then calculates addend Osum with the difference of addend Esum to shift this difference left by 1 bit, thereby obtain addend Osum with the twice of the difference of addend Esum to export this twice difference.
In an embodiment of the present invention, the divider-less divide-by-three circuit further includes: a Ksum computing unit and a KOEsum adder. The Ksum computing unit is used for solving an addend Ksum according to binary data and the addition coefficient of each bit of the binary data, wherein the binary data are sequentially represented as d (n-1), d (n-2), … …, d (1) and d (0) from the highest bit to the lowest bit; the addend Ksum ═ d (n-1) × K (n-1) + … + d (i) × K (i) + … + d (2) × K (2) + d (1) × K (1) + d (0) × K (0), wherein K (i) is an addend coefficient of the ith bit in the binary data. KOEsum adder with Ksum computational element the Osum adder the Esum adder and first multiplexer all links to each other, is used for when first multiplexer compares out addend Esum more than or equal to during addend Osum, KOEsum adder is right addend Ksum with addend Osum sums, still is used for when first multiplexer compares out addend Esum is less than when addend Osum, KOEsum adder is right addend Ksum with addend Esum sums.
In an embodiment of the present invention, when i is less than 2, the addend coefficient k (i) is 0, when i is an even number equal to or greater than 2, the k (i) is a binary number of alternating 1 and 0 of i-1 bits, and the lowest bit of the binary number of alternating 1 and 0 is 1, when i is an odd number equal to or greater than 2, the k (i) is a binary number of alternating 1 and 0 of i-1 bits, and the lowest bit of the binary number of alternating 1 and 0 is 0.
In an embodiment of the present invention, the Ksum calculating unit includes: one or more second multiplexers, and a ksum adder. Each of the second multiplexers is used for selecting an output result according to values of two binary numbers of adjacent digits in the binary data. The Ksum adder is connected to each of the second multiplexers, and is configured to add the output results of each of the second multiplexers to obtain an addend Ksum.
In one embodiment of the present invention, each of the second multiplexers outputs 0 when d (2 × i) is 0 and d (2 × i +1) is 0, each of the second multiplexers outputs K (2 × i) when d (2 × i) is 1 and d (2 × i +1) is 0, each of the second multiplexers outputs K (2 × i +1) when d (2 × i) is 0 and d (2 × i +1) is 1, each of the second multiplexers outputs binary data having i bits and i bits all equal to 1 when d (2 × i) is 1 and d (2 × i +1) is 1, where i is an integer greater than or equal to 1 and less than or equal to n/2.
Compared with the prior art, the divider-free three-division circuit only involves the operations of addition, subtraction, comparison, shifting and the like in the three-division operation, and the addition and the subtraction use the adder to complete the operation.
Drawings
FIG. 1 is a schematic diagram of a divide-by-three circuit for a remainder according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a divide-by-three circuit for quotient and remainder according to an embodiment of the present invention;
FIG. 3 shows the structural components of a Ksum computing unit according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of an 8-bit divide-by-three circuit according to an embodiment of the present invention;
FIG. 5 is a circuit schematic of a cascade of two divide-by-three circuits of the same number of bits according to an embodiment of the present invention;
FIG. 6 is a circuit schematic of a cascade of two different bit number divide-by-three circuits according to an embodiment of the invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
In order to overcome the problems in the prior art, the invention provides a divider-free three-division circuit, in the three-division operation, only addition, subtraction, comparison, shift and other operations are involved, and the addition and the subtraction use an adder to complete the operation.
FIG. 1 is a circuit for performing a divide-by-three circuit without a divider for determining a remainder after the division of three according to an embodiment of the present invention. The circuit includes: an Esum adder 10, an Osum adder 11 and a first multiplexer 12.
The Esum adder 10 is configured to add binary numbers located at even-numbered bits in the binary data to obtain an addend Esum.
The Osum adder 11 is configured to add each binary number located in an odd-numbered position in the binary data to obtain an addend Osum.
When the circuit is actually used, when the result output by the first multiplexer 12 of the circuit is less than 3, the result is the remainder, when the result output by the first multiplexer 12 of the circuit is greater than or equal to 3, the result output by the first multiplexer 12 needs to be sent to the divide-by-three circuit again for recalculation, the result obtained by calculation is compared with 3 again, and the above process is repeated until the result output by the first multiplexer 12 finally is less than 3.
FIG. 2 is a circuit for a divisor three without a divider for determining a quotient and remainder after a divisor three is removed, according to an embodiment of the present invention. The circuit includes: an Esum adder 10, an Osum adder 11, a first multiplexer 12, a Ksum calculating unit 13, and a KOEsum adder 14.
The Esum adder 10 is configured to add binary numbers located at even-numbered bits in the binary data to obtain an addend Esum.
The Osum adder 11 is configured to add each binary number located in an odd-numbered position in the binary data to obtain an addend Osum.
The Ksum calculating unit 13 is configured to solve an addend Ksum according to binary data and an addition coefficient of each bit of the binary data, where the binary data is represented by d (n-1), d (n-2), … …, d (1), and d (0) in sequence from the most significant bit to the least significant bit; the addend Ksum ═ d (n-1) × K (n-1) + … + d (i) × K (i) + … + d (2) × K (2) + d (1) × K (1) + d (0) × K (0), where K (i) is the addend coefficient of the ith bit in the binary data.
KOEsum adder 14 with Ksum computational element 13 the Osum adder 11 the Esum adder 10 and first multiplexer 12 all link to each other for when first multiplexer compares addend Esum more than or equal to during addend Osum, the KOEsum adder is right addend Ksum with addend Osum sums up, still is used for when first multiplexer compares out addend Esum is less than when addend Osum, the KOEsum adder is right addend Ksum with addend Esum sums up.
For the addend coefficient, when i is less than 2, the addend coefficient k (i) is 0, when i is an even number equal to or greater than 2, the k (i) is a binary number of alternating 1 and 0 of i-1 bits, and the lowest bit of the binary number of alternating 1 and 0 is 1, when i is an odd number equal to or greater than 2, the k (i) is a binary number of alternating 1 and 0 of i-1 bits, and the lowest bit of the binary number of alternating 1 and 0 is 0. The values of K (i) are shown in the following table.
| K(0)＝0b0 |
| K(1)＝0b0 |
| K(2)＝0b1 |
| K(3)＝0b10 |
| K(4)＝0b101 |
| K(5)＝0b1010 |
| K(6)＝0b10101 |
| K(7)＝0b101010 |
| K(8)＝0b1010101 |
| K(9)＝0b10101010 |
| K(10)＝0b101010101 |
| K(i)＝0b10101…1010101010 |
In order to increase the operation speed of the Ksum calculating unit 13, in a preferred embodiment, as shown in fig. 3, the Ksum calculating unit 13 includes: a plurality of second multiplexers 13a and a Ksum adder 13 b.
Each of the second multiplexers 13a is configured to select an output result according to values of two binary numbers of adjacent bits in the binary data. Wherein each of the second multiplexers 13a outputs 0 when d (2 × i) is 0 and d (2 × i +1) is 0, each of the second multiplexers 13a outputs K (2 × i) when d (2 × i) is 1 and d (2 × i +1) is 0, each of the second multiplexers 13a outputs K (2 × i +1) when d (2 × i) is 0 and d (2 × i +1) is 1, each of the second multiplexers 13a outputs binary data having i bits and i bits being 1, where i is an integer greater than or equal to 1 and less than or equal to n/2, when d (2 × i) is 1 and d (2 × i +1) is 1.
The Ksum adder 13b is connected to each of the second multiplexers 13a, and configured to add the output results of each of the second multiplexers 13a to obtain the addend Ksum.
When the circuit of the embodiment of fig. 2 and fig. 3 solves the remainder in actual use, when the result output by the first multiplexer 12 of the circuit is less than 3, the result is the remainder, when the result output by the first multiplexer 12 of the circuit is greater than or equal to 3, the result output by the first multiplexer 12 needs to be sent to the divide-by-three circuit for recalculation again, the result calculated by the first multiplexer 12 is compared with 3 again, and the above process is repeated until the last result output by the first multiplexer 12 is less than 3, and the last result is the remainder. In addition, when the circuit of this embodiment solves the quotient in actual use, when the result output by the first multiplexer 12 of the circuit is less than 3, the result of the KOEsum adder 14 is the quotient, when the result output by the first multiplexer 12 of the circuit is greater than or equal to 3, the result output by the first multiplexer 12 needs to be sent to the divide-by-three circuit again for recalculation, the result calculated by the first multiplexer 12 is compared with 3 again, the above process is repeated until the result output by the first multiplexer 12 is finally less than 3, and the sum of the results output by the KOEsum adder 14 each time in the process is the quotient obtained by dividing three. The numerical value (decimal) of the binary data to be divided is between 0 and 9, and after 1 cycle, a quotient and a remainder can be obtained. The numerical value (decimal) of binary data to be divided is 10-681, and after 2 circulation times, a quotient and a remainder can be obtained. The numerical value (decimal) of the binary data to be divided is more than 682, and after 3 times of circulation times and more, quotient and remainder can be obtained. In an actual application scenario, the cycle number of 3 times can satisfy most applications.
The calculation steps for solving the quotient and remainder of the above embodiment have precedence relationship, but are independent of the clock. The computation can be done using several clock edges or it can be done using combinatorial circuits without using clocks. For binary data to be divided with more bits, the same three-division circuit can be used repeatedly in the embodiment, and different three-division circuits can be used to improve the calculation efficiency. When the divide-by-three unit circuit is used in a circulating way, after each calculation is completed, if the output result of the first multiplexer 12 is greater than or equal to 3, the output result is used as the input of the next divide-by-three circuit calculation. The output result has a much reduced number of input bits relative to the original binary number to be divided. Obviously, in the subsequent loop calculation, a three-division circuit with a reduced input bit number can be adopted, and the calculation efficiency can be improved. For better understanding, in the following embodiments, the solution of the quotient and remainder is illustrated again with 8-bit binary data.
FIG. 4 is a circuit for divide-by-three without a divider according to an embodiment of the present invention. In fig. 4, 8D flip-flops 15 are used to store binary data of 8 bits, and each D flip-flop 15 stores one bit of data among the binary data, which includes respective binary numbers located in odd-numbered bits and respective binary numbers located in even-numbered bits. For convenience of explanation, the binary data are represented as d (7), d (6), … …, d (1), and d (0) in order from the most significant bit to the least significant bit.
The Esum adder 10 is connected to all the D flip-flops 15 storing the binary numbers located at the even number, and is configured to add the binary numbers located at the even number to obtain an addend Esum.
The Osum adder 11 is connected to all D flip-flops 15 that store the respective binary numbers in the odd bits, and is configured to add the respective binary numbers in the odd bits to obtain an addend Osum.
One of the 3 second multiplexers 13a is connected to a set of D flip-flops 15 that store D (7) and D (6), one of which is connected to a set of D flip-flops 15 that store D (5) and D (4), and one of which is connected to a set of D flip-flops 15 that store D (3) and D (2).
The Ksum adder 13b is connected to each of the second multiplexers 13a, and adds the output results of all the second multiplexers 13a to add the number Ksum. It is also noted that in other embodiments, the Ksum adder 13b may be directly connected to the set of D flip-flops 15 storing D (3) and D (2) without connecting the second multiplexer 13a, thereby eliminating a multiplexer. The reason why such variation is possible is that the output result of the second multiplexer 13a is used in agreement with the data of the set of D flip-flops 15 storing D (3) and D (2). Specifically, when d (3) and d (2) are 0 and 1, respectively, if the second multiplexer 13a is used, the second multiplexer 13a outputs binary 1; when d (3) and d (2) are 1, respectively, the second multiplexer 13a outputs the binary system 11; when d (3) and d (2) are 1, 0, respectively, the second multiplexer 13a will output binary 10; when d (3) and d (2) are 0, respectively, the second multiplexer 13a outputs a binary 0.
In the embodiment shown in fig. 4, since the numerical range of the binary data of 8 bits is within 255, the number of cycles for solving the quotient and remainder is within 2. When the number of cycles is 1, the quotient and remainder can be obtained directly with the circuit shown in fig. 4. When the number of cycles is 2, the result output from the first multiplexer 12 may be recalculated in the circuit input to this fig. 4. The two calculations of the KOEsum adder 14 are summed to obtain the quotient, and the second output of the first multiplexer 12 is the remainder. In addition, when the number of cycles is 2, one same circuit can be further cascaded to improve the operation efficiency, and this embodiment is shown in fig. 5. In addition, when the number of cycles is 2, a circuit with a reduced number of input bits (for example, 4 bits) may be cascaded to further improve the operation efficiency, and this embodiment is shown in fig. 6.
In summary, compared with a general divider, the divider-less divide-by-three circuit of the present embodiment converts the division operation into the addition, subtraction, and shift operations, and has the advantages of less resource occupation, low power consumption, and low cost. In addition, compared with the existing divide-by-three circuit, the binary data to be divided is not required to be continuously generated, the circuit is more flexible, and the continuous divide-by-three circuit working along with a clock circuit is not required, so that the larger power consumption is reduced, and the problem of alignment of the starting points of the divide-by-three circuit is solved.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (4)
1. A divider-less divide-by-three circuit, comprising:
the Esum adder is used for adding each binary number positioned at the even number in the binary data to obtain an addend Esum;
the sum adder is used for adding each binary number positioned at an odd number in the binary data to obtain an addend sum; and
a first multiplexer, connected to the Esum adder and the Osum adder, for comparing the addend Esum with the addend Osum, if the addend Esum is greater than or equal to the addend Osum, calculating the difference between the addend Esum and the addend Osum, and outputting the difference between the addend Esum and the addend Osum, if the addend Esum is less than the addend Osum, calculating the difference between the addend Esum and the addend Esum, and shifting the difference between the addend Esum and the addend Esum by 1 bit to obtain the double of the difference between the addend Esum and the addend Esum, and outputting the double of the difference between the addend Esum and the addend Esum;
the Ksum computing unit is used for solving an addend Ksum according to binary data and an addition coefficient of each bit of the binary data, wherein the bits of the binary data from the highest bit to the lowest bit are sequentially represented as d (n-1), d (n-2), … …, d (1) and d (0); the addend Ksum = d (n-1) × K (n-1) + … + d (i) × K (i) + … + d (2) × K (2) + d (1) × K (1) + d (0) × K (0), where K (i) is an addend coefficient of the ith bit in the binary data; and
KOEsum adder, with Ksum computational element the Osum adder the Esum adder and first multiplexer all links to each other, is used for when first multiplexer compares out addend Esum more than or equal to during addend Osum, KOEsum adder is right addend Ksum with addend Osum sums, still is used for when first multiplexer compares out addend Esum is less than when addend Osum, KOEsum adder is right addend Ksum with addend Esum sums.
2. The divisible divide-by-three circuit of claim 1, wherein when i is less than 2, the addend coefficient k (i) is 0, when i is an even number equal to or greater than 2, the k (i) is a binary number of alternating 1 and 0 bits of i-1 bits, and the lowest bit of the binary number of alternating 1 and 0 is 1, when i is an odd number equal to or greater than 2, the k (i) is a binary number of alternating 1 and 0 bits of i-1 bits, and the lowest bit of the binary number of alternating 1 and 0 is 0.
3. The divider-less divide-by-three circuit of claim 1, wherein the Ksum calculation unit comprises:
one or more second multiplexers each for selecting an output result according to values of two binary numbers of adjacent digits in the binary data;
and the Ksum adder is connected with each second multiplexer and used for adding the output results of each second multiplexer to obtain the addend Ksum.
4. The divider-less divide-by-three circuit of claim 3, wherein each of the second multiplexers outputs 0 when d (2 x i) =0 and d (2 x i +1) =0, outputs K (2 i) when d (2 x i) =1 and d (2 i +1) =0, outputs K (2 i +1) when d (2 x i) =0 and d (2 x i +1) =1, and outputs binary data having a total of i bits and i bits of 1 when d (2 x i) =1 and d (2 i +1) =1, where i is an integer greater than or equal to 1 and less than or equal to n/2.
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