JPH06224780A - Code conversion circuit - Google Patents

Abstract

PURPOSE:To suppress the errors of + or -1 bit in code conversion data due to noise or the like by adding '1' at the time of the decrease of data by a comparator circuit. CONSTITUTION:A delay circuit 1 is provided and binary linear code input data represented by the complement of '2' inputted at a certain sampling period are held for one sampling period. By the comparator circuit 2, the output of the delay circuit 1 is compared with the linear code input data and comparison signals are outputted. A complement circuit 3 is provided and the complement of '1' of the linear code input data is obtained. An exclusive OR circuit 4 is provided and the exclusive OR of the code bit of the linear code input data and the comparison signal is taken. An adding circuit 5 letting exclusive OR output be the carry input of a least significant bit is provided and the output of the complement circuit 3 is defined as input A conversion circuit 6 is provided and the output of the adding circuit 5 is converted to nonlinear PCM codes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code conversion circuit, and more particularly to a code conversion circuit for converting linear code data represented by 2's complement into non-linear PCM code data.

[0002]

2. Description of the Related Art Conventionally, a code conversion circuit for converting linear code data represented by 2's complement into 8-bit non-linear PCM code of 13-fold linear A characteristic (hereinafter referred to as A non-linear code) is as shown in FIG. , 13-bit linear code data LD ₀ to 1 of LD ₁₂
Complement circuit 3 composed of exclusive OR gates 301 to 312 for taking the complement of A, adder circuit 5 composed of full adders 501 to 512, linear code data of absolute value expression shown in FIG. The conversion circuit 6 performs code conversion according to the linear code correspondence table.

Next, the operation will be described.

Linear code data LD _{12 to} L in 2's complement representation
D ₀ is a sign bit indicating the polarity of the most significant bit LD ₁₂ , and is “0” for positive data and “1” for negative data.

[0005] In order to convert the linear code data of the straight line code data LD ₁₂ magnitude representation conforming the to Ld ₀ in the correspondence table of the linear code and A nonlinear code illustrated in FIG. 6, the linear code data LD ₁₂ ~ if LD ₀ is negative, it is necessary to take 2's complement addition of the data is inverted LD ₁₁ to Ld ₀ of lower 12 bits excluding the sign bit plus.

The complement circuit 3 receives the most significant bit LD ₁₂ of the linear code data as one input and the other bits LD _{11 to} L to the other.
It is composed of exclusive OR gates 301 to 312 for inputting D ₀ , and takes 1's complement. The adder circuit 5 is constituted by full adders 501 to 512 for adding 1 to the output of the complement circuit 3 when the linear code data LD _{12 to} LD ₀ is negative, and carries the carry of the least significant bit full adder 501. Input C
The code bit LD ₁₂ is input to. These full adders 501 to 512 are composed of gate circuits as shown in FIG.

The output of the adder circuit 5 is converted by the conversion circuit 6 which performs code conversion according to the correspondence table shown in FIG. 6, and is output as 8-bit A nonlinear code data PCM _{7 to} PCM ₀ . .

[0008]

In this conventional code conversion circuit, since the A non-linear code does not have a 0 code, when the A non-linear code to the linear code is near 0 of the linear code, the quantization step is caused by noise or the like. There is a ambiguity corresponding to the width, that is, an error of ± 1 bit is generated.

Further, the behavior of the code conversion circuit near 0 has a problem that it causes fluttering noise at the time of no signal input in signal processing of voice and the like.

[0010]

In the code conversion circuit of the present invention, binary linear code input data represented by a two's complement of n bits input at a predetermined sampling period is used for one sampling period. Delay circuit for holding
A comparison circuit for comparing the output of the delay circuit with the linear code input data and outputting a comparison signal, a complement circuit for taking the one's complement of the linear code input data, and the most significant bit of the linear code input data. An exclusive OR circuit that takes an exclusive OR of the sign bit and the comparison signal and outputs an exclusive OR output, and the output of the complement circuit is input and the exclusive OR output is carried to the least significant bit. It is provided with an adder circuit for inputting and a conversion circuit for converting the output of the adder circuit into a non-linear PCM code.

[0011]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, the code conversion circuit of the present invention is
The delay circuit 1, the comparison circuit 2, and the exclusive OR gate 4
And a complement circuit 3, which is a component common to the conventional example, an adder circuit 5, and a conversion circuit 6.

Next, the operation of this embodiment will be described.

13 input at constant sampling intervals
Linear code data LD _{12 to} LD ₀ expressed in 2's complement of bits
Are held in the delay circuit 1 constituted by the latch circuit for one sampling.

[0016] and the inverted output signal of the delay data stored in the delay circuit 1, the linear code data LD ₁₂ to Ld ₀ is the full adder 201 for inputting "1" to the carry input of the least significant bit
And the full adders 202 to 213 are input to the comparison circuit 2, and the comparison is performed by realizing the subtraction.
The most significant bit C of the comparison circuit 2 indicates the result of comparison between the previously input linear code data and the currently input linear code data. When "0", the linear code data increases.
When the value is "1", the linear code data decrease is shown.

Here, the full adder 2 constituting the comparison circuit 2
Since 01 to 212 do not require the addition output signal S, it is possible to use the adder having the gate configuration shown in FIG.

Like the circuit of FIG. 7 described in the conventional embodiment, the linear code data LD _{12 to} LD ₀ take the 1's complement when the polarity is negative. The exclusive OR gate 3 of the complement circuit 3 is used.
The inversion processing is performed by 01 to 312.

The outputs of the complement circuit 3 are full adders 501 to 51.
The linear code data L
When D _{12 to} LD ₀ are negative, “1” is added. Here, the comparison result output signal C indicating the increase / decrease of the linear code data detected by the comparison circuit 2 and the linear code data LD _{12 to} LD _0.
When the two's complement of the linear code data is obtained by setting the output signal E of the exclusive OR gate 4 that receives the sign bit LD ₁₂ indicating the polarity of The "1" addition for negative data and the "1" addition by decrease detection at the time of comparison with the previous data are simultaneously performed.

This operation will be specifically described.

First, when data from positive data is reduced by positive data, the input of the exclusive OR gate 4 is (0,
1), and "1" is added. In addition, when the data decreases from the positive data to the negative data or from the negative data to the negative data, the input of the exclusive OR gate 4 is (1,
1) and "0" is added, but only the inversion processing of negative data remains, which is equivalent to the result of adding 1 and then taking the complement of 2. Further, in the case where the data increases from the negative data to the negative data, the input of the exclusive OR gate 4 becomes (1,0), and "1" is added.

After these addition processes, the output of the adder circuit 5 and the most significant bit LD ₁₂ of the linear code data are the 8-bit A non-linear code data PCM ₇ according to the correspondence table shown in FIG.
To PCM ₀ are converted by the conversion circuit 6.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing the second embodiment.

The difference of this embodiment from the first embodiment is that the input linear code data is serial data.

In FIG. 2, shift registers 7 and 8 are provided.
The inverter 9, the serial adder circuit 10, and the latch circuit 10 are added to the complement circuit 3, the exclusive OR gate 4, the adder circuit 5, and the conversion circuit 6 similar to those of the first embodiment of FIG. Has been done.

Next, the operation of this embodiment will be described.

Linear code data SD input serially
_{The in} is converted into parallel data by the shift register 7, and at the same time, the serial output data SD _out of the shift register 7 is input to the shift register 8 via the inverter 9. The shift register 8 holds the data one sampling before in the delay circuit.

Serial output S of shift registers 7 and 8
O is added by the serial adder circuit 10 and compared. The addition result, that is, the comparison result is held in the latch circuit 11.

The serial adder circuit 10 is composed of a full adder and a flip-flop shown in FIG.

The output of the latch circuit 11, that is, the comparison result output signal C becomes one input of the exclusive OR gate 4.

The following conversion operation is similar to the operation of the first embodiment described above.

In the present embodiment, only one adder is required to carry out the comparison operation by serial operation, so that the circuit can be simplified.

[0034]

As described above, according to the present invention, since the increase / decrease of the data is checked by the comparison circuit and 1 is added when the data is decreased, the hysteresis characteristic is provided. This has the effect of suppressing the occurrence of bit errors. Further, there is an effect that fluttering noise when there is no signal in signal processing of voice or the like can be reduced by suppressing an error in code conversion data.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a code conversion circuit of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the code conversion circuit of the present invention.

FIG. 3 is a circuit diagram showing an example of a full adder of the complement circuit shown in FIGS. 1, 2 and 7.

FIG. 4 is a circuit diagram showing an example of a full adder of the adder circuit shown in FIGS. 1, 2 and 7.

5 is a circuit diagram showing an example of a full adder of the serial addition circuit shown in FIG.

FIG. 6 is a diagram showing a correspondence table between linear code data of absolute value representation and A non-linear code data.

FIG. 7 is a block diagram showing an example of a conventional code conversion circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Delay circuit 2 Comparison circuit 3 Complement circuit 4,301 to 312 312 Exclusive OR gate 5 Addition circuit 6 Conversion circuit 7 and 8 Shift register 9 Inverter 10 Serial addition circuit 11 Latch circuit 201 to 212, 501 to 512 Full adder

[Procedure amendment]

[Submission date] October 22, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 7

[Correction method] Delete

Claims (1)

[Claims] 1. A delay circuit for holding, for one sampling period, binary linear code input data represented by an n-bit two's complement input at a predetermined sampling period, and an output of the delay circuit. And a comparison circuit for comparing the linear code input data with each other and outputting a comparison signal, a complement circuit for taking a one's complement of the linear code input data, and a comparison with the code bit which is the most significant bit of the linear code input data. An exclusive OR circuit that takes an exclusive OR with a signal and outputs an exclusive OR output, and an adder circuit that inputs the output of the complement circuit and uses the exclusive OR output as a carry input of the least significant bit. And a conversion circuit for converting the output of the addition circuit into a non-linear PCM code.