JP2000174629A - Code modulation method, circuit and information recording and reproducing device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly conduct succeeding modulation by detecting a line overflow of an arithmetic result and using a selector that selects a succeeding integration DC component on the basis of the comparison result between the detection result and an absolute value so as to allow the selector to select the result substantially to be selected even when the arithmetic result indicates the occurrence of overflow. SOLUTION: A line overflow detection circuit 117 (119) receives a DSV value 101 (105) of a modulation code object A (B), an integral value 102, and an arithmetic result 104 (107) of a computing element 103 (106) and outputs a line overflow discrimination result 118 (120) of the arithmetic result 104 (107). A comparator 108 receives both the arithmetic results 104, 107 and compares the absolute values of them to provide an output of a comparison result 109. A comparison control circuit 121 outputs a line overflow state 123 that denotes whether or not a line overflow place. A selector 110 receives a selection result 122 and the line overflow state 123 as selection control signals and selects and outputs at of three kinds of the input signals that are the arithmetic results 104, 107 and the DSV value 101 being the modulation code object A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In a DC component suppressing modulation code modulator for converting an input code sequence into a modulation code sequence having a different number of bits, when selecting an optimal modulation code sequence from a plurality of modulation code candidates, A DC component value (Digital Sum) of a modulation code candidate for which selection is determined.
The present invention relates to a method and a circuit for performing calculation of a value (hereinafter referred to as DSV) and controlling the determination of the result.

[0002]

2. Description of the Related Art FIG. 2 shows a prior art circuit configuration of a DC component suppression modulation code modulator using an 8-16 modulation code modulator of a DVD system as an example.

In order to suppress the DC component of the modulation signal,
It is necessary to select a modulation code such that the number of “1” and “0” of the modulation signal becomes equal. The DSV value indicates the difference between the number of “0” and the number of “1”. For example, when “0” has one bit, 1 is added to the DSV value, and when “1” has 1 bit, 1 is added.
Is subtracted, when the DSV value is “+”, it is possible to indicate that the number of “0” is large, and when the DSV value is “−”, it is possible to indicate that the number of “1” is large. In the 8-16 modulation, when performing modulation, 8-bit (1 word) input data is converted into a 16-bit modulation code, and a modulation signal is generated by NRZI modulation. As is well known, NRZI modulation is a modulation method in which an output modulation signal is inverted every time "1" appears in input data, and a DSV value is calculated for this modulation signal. In order to limit the bandwidth of the frequency component of the modulated signal, a so-called run length is limited, which is 2 to 10, that is, the number of consecutive “0” s sandwiched by “1” before NRZI modulation is 2 to 10 NRZI
The number of continuations of “1” and “0” after modulation is set to 3 to 11. To achieve this, in the 8-16 modulation, when converting to a 16-bit modulation code, a 4-state modulation code is assigned to each data (0 to 255) of one word as a main conversion table. To the range of ~ 87, a 4-state modulation code different from the code of the main conversion table and the DSV is assigned as the sub conversion table. Each modulation code specifies the state of the next modulation code in order to satisfy the run-length condition at the connection with the next modulation code. In the modulation, when the data is in the range of 0 to 87, the modulation code of the state specified by the immediately preceding modulation code is selected one by one from the main conversion table and the sub conversion table, and the DSV of the integration is reduced from both. The other modulation code. When the data is 88 to 255, the state specified by the immediately preceding modulation code is state 1 or state 4
Only when the modulation length of both the state 1 and the state 4 of the main conversion table satisfies the run length condition, the code of the modulation code of the state 1 and the modulation code of the state 4 which has the smaller integrated DSV is selected. I do. DS
Since V can be both positive and negative, negative values are treated as two's complement in order to realize integration only by addition. When one of the two candidates is selected, one of the modulation code candidates is, for example, A
And the other modulation code candidate is, for example, B. The circuit adds the DSV value input 201 of the modulation code candidate A and the integrated value 202 and outputs an operation result 204, and adds the DSV value input value 205 of the modulation code candidate B and the integrated value 202 and outputs the operation result 207. An arithmetic unit 206, a comparator 208 that inputs the operation result 204 and the operation result 207, compares their absolute values and outputs a comparison result 209, and a selector that selects and outputs the operation result 204 and the operation result 207 based on the comparison result 209. 210, a latch 212 for holding a selected operation result 211 and outputting an integrated value 202, a comparison result 2
09, modulation code candidate A 213 and modulation code candidate B
And a selector 215 for selecting the code 214 and outputting a modulation code 216.

The comparator 208 compares the operation result 204 with the operation result 207. If the absolute value of the operation result 204 is smaller than the operation result 207, the comparison result 209 is set to 0, and the operation result 2
If the absolute value of 07 is smaller, the comparison result 209 is set to 1. If the comparison result 209 is 0, the selector 210 outputs the operation result 204 as the selection result 211, and the comparison result 2
If 09 is 1, the operation result 207 is output as the selection result 211. The selection result 211 is held in the latch 212 and output as the integrated value 202. The held integrated value 202 is similarly used for selecting the next modulation candidate. Furthermore, selector 2
Reference numeral 15 selects the modulation code candidate A if the comparison result 209 is 0, and selects the modulation code candidate B if the comparison result 209 is 1 and outputs it as the modulation code 216. In this way, the integrated value of DSV is compared, a modulation code is selected and modulation is performed.

[0005]

The arithmetic units 203 and 206 used in the prior art have a finite number of digits, and therefore have the following problems.

In FIG. 2, arithmetic units 203 and 206 are signed 4-bit arithmetic units as an example of a finite number of digits. The integrated value 202 is “+6” as a 4-bit value with a sign, “0110” in binary representation, the DSV value input 201 of the modulation code candidate A is “+7” as a 4-bit value with a sign, and “0111” in binary representation. ", DSV value input 20 of modulation code candidate B
5 is “+1” as a 4-bit value with a sign, and “0001” in binary representation. The calculation result of the calculator 203 is “+
"+13" is obtained by adding "6" and "+7", but becomes "1101" in binary notation and the most significant bit (sign bit)
Carry-over, the result is expressed as a negative number “−3”. On the other hand, the output of the arithmetic unit 206 is “+6” and “+
The result of addition 207 is “+7”, and the operation result 207 is “0111” in binary notation, representing “+7.” Here, the operation results 204 and 207 are compared by the comparator 208 and the comparison result is obtained. 209. Since the smaller absolute value is output as a result, the operation result 204 is originally “+13”,
Since the operation result 207 is “+7”, the operation result 207 should be selected and the comparison result 209 should be set to 1. However, the operation result 204 is interpreted as a negative number “−3” represented by a two's complement, and the operation result is calculated. Since the result 207 is “+7”, the operation result 20
By selecting 4 and setting the comparison result 209 to 0, the code with the larger DSV is selected. In this way, if the calculation result overflows, the code to be originally selected cannot be selected, and the subsequent DC control is not performed correctly because the incorrectly selected calculation result is used as the next integrated value. I do. If the number of digits of the arithmetic unit and the comparator is made larger than the DSV that can actually occur, such a problem does not occur. However, it is difficult to accurately predict the maximum value of the DSV, and the occurrence frequency is extremely high. Setting a large number of digits to a small worst value is also inefficient.

It is an object of the present invention to provide a code modulation with a DC component suppression control that enables a result to be originally selected to be selected even when an arithmetic result overflows, and enables subsequent modulation to be performed correctly. I do.

[0008]

In order to achieve the above object, an overflow detection circuit for detecting overflow of a calculation result and a next integrated DC component value are selected based on the overflow detection result and the absolute value comparison result. A selector is provided to constitute a DC component suppression control code modulation circuit.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of a DC component suppression control code modulation circuit according to the present invention. In the first embodiment, one modulation code is selected from the two types of modulation code candidates by the DSV value. The DSV value 101 of one modulation code candidate A and the integrated value 102 are added, and the operation result 104 is obtained. A computing unit 103 to output, a computing unit 106 to add the DSV value 105 of the other modulation code candidate B and the integrated value 102 and to output an operation result 107, and to calculate the DSV value 101, the integrated value 102 and the operation result 104 of the modulation code candidate A An overflow detector 117 that outputs an overflow determination result 118 of the operation result 104 as an input, and a DSV of the modulation code candidate B.
An overflow detection circuit 119 which receives a value input 105, an integrated value 102, and an operation result 107 as an input and outputs an overflow judgment result 120 of the operation result 107, an operation result 104, and an operation result 1
07, the comparator 108 compares the absolute values of the two, and outputs a comparison result 109. The comparator 108 inputs the comparison result 109 and the overflow judgment results 118 and 120, and the selection result 122 indicating which candidate is selected. Digit overflow state 1 indicating whether digit overflow has occurred in DSV integration by candidates
23, a comparison control circuit 121 that outputs 23, a selection result 122 and an overflow state 123 that are input as selection control signals,
A selector 110 that selects and outputs one signal from three types of input signals, that is, an operation result 104, an operation result 107, and a DSV value 101 of the modulation code candidate A, and a selected operation result 111
(Also referred to as an integrated DC component value) and a latch 112 for holding as an integrated value 102, a selection result 122 as a selection control signal, and selecting one of a modulation code candidate A113 and a modulation code candidate B114 to select a modulation code. 1
16 is provided. Although not shown here, the modulation code 116 is subjected to NRZI modulation to generate a modulation signal.

Next, the operation of the first embodiment will be described. The DSV value of each modulation code candidate has an initial value of 0,
Add the number of bits from the first bit until the first "1" appears, subtract the number of bits until the next "1" appears, add the number of bits until the next "1" appears, and so on.
This is a value calculated with a 6-bit length, and can take a positive value or a negative value. Therefore, when the previous NRZI modulation ends with “0”, the integrated DSV value may be the same as the DSV value of the modulation code candidate, but when the previous modulation ends with “1”, the modulation code candidate The sign of the DSV value needs to be inverted, and the sign is inverted by a sign inversion circuit (not shown). Here, first, the modulation code candidate A side is DSV
A case where an overflow occurs in addition of values will be described.
In FIG. 1, arithmetic units 103 and 106 are signed 4-bit arithmetic units as an example of a finite number of digits. Further, the negative number of the DSV is represented by a two's complement. The integrated value 102 is “+6” as a 4-bit value with a sign, and “011” in binary notation.
0 ”, the DSV value input 101 of the modulation code candidate A is“ +7 ”as a signed 4-bit value, and“ 011 ”in binary representation.
1 ”, the DSV value input 105 of the modulation code candidate B is“ +1 ”as a signed 4-bit value, and“ 0001 ”in binary representation.
And The output of the arithmetic unit 103 is “+13” by adding “+6” and “+7”, but the arithmetic result 104 is “1101” in the binary representation, and the most significant bit as the sign bit is “1”. Therefore, the two's complement of "-3" is expressed. The output of the arithmetic unit 106 is “+7” by adding “+6” and “+1”, and the arithmetic result 107 is “0” in the binary representation.
111 ”, which indicates“ +7 ”because the most significant bit, which is the sign bit, is“ 0 ”.
8 compares the operation results 104 and 107 with absolute values, and when | operation result 104 |> | operation result 107 |, the comparison result 109
Is "1", and when | operation result 104 | <| operation result 107 |, the comparison result 109 outputs "0". In our example,
The comparison result 109 should be “1” because “| the operation result 104 (“ +13 ”) |> | the operation result 107 (“ +7 ”) |” originally.
Since 04 is treated as “−3”, the comparison result 109 becomes “0”. In the digit overflow detection circuit 117, the integrated value 10
2 and the modulation code candidate A
Are the same (here, "0") as the sign bit of the DSV value input value 101, and are different ("1") as the sign bit of the operation result 104.
The digit overflow is detected, and the digit overflow determination result 118 indicates that the digit overflow is detected ("1"). On the other hand, in the overflow detector 119, the most significant bit which is the sign bit of the integrated value 102 and the DSV value input value 105 of the modulation code candidate B are output.
Since the most significant bit, which is the sign bit of the operation result 107, is the same (here, “0”), and the most significant bit, which is the sign bit of the operation result 107, is also the same (“0”), it is detected that there is no overflow. , The digit overflow determination result 120 indicates that there is no digit overflow (“0”). The comparison control circuit 121 outputs the comparison result 109 (“0”), the digit overflow determination result 118
(“1”), the digit overflow determination result 120 (“0”) is input. In this example, the digit overflow determination result 118 on the modulation code candidate A side indicates "1" to indicate digit overflow, and the digit overflow determination result 120 on the modulation code candidate B side indicates "0", indicating no digit overflow. Therefore, it is determined that the calculation on the modulation code candidate A side is not normal and the calculation on the modulation code candidate B side is normal, and the selection result 122 indicates that the modulation code candidate B side is to be selected. Since the selection has been made, the overflow state 123 is "0" indicating that there is no overflow.
Is output. The selector 110 selects the selection result 122
(“1”), the overflow state 123 (“0”) is input, the modulation code candidate B having no overflow is selected, and the operation result 107 of the modulation code candidate B is output as the selected operation result 111. I do. The selector 115 selects the selection result 122
(“1”) is input and the code 114 of the modulation code candidate B
Is output as a modulation code 116.

Next, a case where the modulation code candidate B generates overflow due to the addition of the DSV value will be described. The integrated value 102 is “+6” as a signed 4-bit value, “0110” in binary representation, and the DSV value input 10 of the modulation code candidate A
“1” as a 4-bit value with “1”, “0001” in binary notation, and DSV value input 105 for modulation code candidate B
Is “+7” as a signed 4-bit value, and “0” in binary
111. The output of the arithmetic unit 106 is “+6” and “+
7 ”is added to obtain“ +13 ”, but“ 1 ”is used in the binary representation.
101 "and the sign bit becomes" 1 ", so" -3 "
2's complement. The output of the arithmetic unit 103 is “+7” by adding “+6” and “+1”, and is “0” in the binary representation.
111 ”and the sign bit becomes“ 0 ”, so“ +7 ”
become. The comparator 108 compares the absolute values of the operation results 104 and 107 and outputs a comparison result 109. The comparison result 109 should be “0” because “| operation result 104 | <| operation result 107 |” originally. However, in the comparator 108, the operation result 107 is “−3” and the operation result 104 is “ +
7 ", the result is" | operation result 104 |> | operation result 107 | ", and the comparison result 109 becomes" 1 ". In the overflow detector 119, the most significant bit which is the sign bit of the integrated value 102 and the DSV value input value 1 of the modulation code candidate B
Since the most significant bit, which is the sign bit of 05, is the same (here, “0”) and the most significant bit, which is the sign bit of the operation result 107, is different (here, “1”), overflow is detected. The overflow determination result 120 is set to “1”. On the other hand, in the overflow detection circuit 117, the most significant bit which is the sign bit of the integrated value 102 and the most significant bit which is the sign bit of the DSV value input value 101 of the modulation code candidate A are the same (here, “0”), and Since the most significant bit which is the sign bit of the operation result 104 is the same (“0”), it is detected that there is no overflow, and the overflow determination result 118 is set to “0”. The comparison control circuit 121 calculates the comparison result 109
Is input, the digit overflow determination result 118 is input as “0”, and the digit overflow determination result 120 is input as “1”.
The overflow judgment result 120 on the side of "1" indicates overflow, and the overflow determination result 118 on the modulation code candidate A side is "0", indicating that overflow has not occurred.
It is determined that the calculation on the modulation code candidate B side is not normal and the calculation on the modulation code candidate A side is normal, and the selection result 122 is “0” indicating that the modulation code candidate A side is selected. The digit overflow state 123 is set to “0” indicating that there is no digit overflow. Since the selection result 122 is input to the selector 110 with “0” and the overflow state 123 is input with “0”, the modulation code candidate A is selected, and the selected calculation result 111 is the calculation result 104 of the modulation code candidate A side.
Is output. Since “0” is input to the selector 115 as the selection result 122, the code 1 of the modulation code candidate A
13 is output to the modulation code 116. As described above, even if overflow occurs in the DSV integration of one modulation code candidate, the other candidate for which the normal calculation is normally performed is selected.
The integration of V is performed normally, and DC component suppression control is realized.

Next, both the modulation code candidates A and B have DS values.
A case where an overflow occurs in the addition of the V value will be described. The integrated value 102 is expressed as a signed 4-bit value “+”.
6 ”,“ 0110 ”in binary notation, D of modulation code candidate A
SV value 101 is a signed 4-bit value of “+6”, 2
"0110" in hexadecimal notation, DSV value 1 of modulation code candidate B
05 is “+7” as a signed 4-bit value, and is “0111” in binary notation. DSV value of modulation code candidate A 10
The calculation result of 1 and the integrated value 102 is “+12” by adding “+6” and “+6”.
04 is "1100" in binary notation and the sign bit is "1", so it is a two's complement of "-4". The calculation result of the DSV value 105 and the integrated value 102 of the modulation code candidate B is “+13” by adding “+6” and “+7”, but the calculation result 107 of the calculator 106 is “1101” in binary notation.
And the sign bit becomes "1", so that it becomes a two's complement of "-3". The comparator 108 compares the absolute values of the operation results 104 and 107 and outputs a comparison result 109. Since the operation result 104 is originally “+12” and the operation result 107 is “+13”, “| operation result 104 | <| operation result 107 |”
Although the operation result 104 is smaller and the comparison result 109 should be "0", the operation result 104 is treated as "-4" and the operation result 107 is treated as "-3" in the comparator 108. Is smaller than
The comparison result 109 becomes “1”. Digit overflow detection circuit 11
7, the most significant bit which is the sign bit of the integrated value 102 and the most significant bit which is the sign bit of the DSV value input value 101 of the modulation code candidate A are the same (here, “0”), and the sign bit of the operation result 104 Is detected (here, "1"), the overflow is detected, and the overflow determination result 118 is set to "1". On the other hand, in the overflow detector 119, the most significant bit, which is the sign bit of the integrated value 102, is the same as the most significant bit, which is the sign bit of the DSV value input value 105 of the modulation code candidate B (here, "0"), and An overflow is detected based on the difference (here, “1”) of the most significant bit as a sign bit of the operation result 107, and the overflow determination result 120 is set to “1”. The comparison control circuit 121 outputs a comparison result 109 (“1”), a digit overflow determination result 118 (“1”), and a digit overflow determination result 120.
("1") is input, and the overflow determination determination results 118 and 120 on both the modulation code candidate A side and the B side are "1" indicating overflow, so that both the modulation code candidate A and the B side can calculate. It is determined that the result is not normal, and the selection result 122 is “0” indicating that the modulation code candidate A has been selected, and the overflow state 123 is “1” indicating that there is an overflow because only the overflowed calculated value could be selected. ". Selector 11
0 is the selection result 122 (“0”), the digit overflow state 12
3 (“1”) is input, and correct DSV integration was not performed for either modulation code candidate. Therefore, regardless of the selection result 122, the DSV on the modulation code candidate A side
The value input 101 is output to the operation result 111. Selector 1
Reference numeral 15 denotes a modulation candidate A to which the selection result 122 (“0”) is input.
Is output as a modulation code 116. As described above, when overflow occurs in both candidates in the DSV calculation of the modulation code candidates, the modulation code candidate on the predetermined side is selected as the modulation code, and the DSV value of the selected modulation code is set to the previous value. Initialize the integrated value by replacing it with the integrated value and continue the subsequent calculations. By doing so, the subsequent DSV integration is performed normally, and the overflow of the DSV integrated value does not affect the subsequent DSV integration. Table 1 shows an operation truth table of the selector 110 for the above operation. Note that the description so far has been made only on the case where overflow occurs due to addition. However, the same applies to an abnormal calculation result due to overflow when adding two's complements. is there.

[0013]

[Table 1]

As a second embodiment, modulation code candidates A,
An embodiment of another selector 110 in the case where overflow occurs in the calculation of the DSV value for both B will be described with reference to FIG. 1 of FIG.
In the embodiment, the DSV value input 101 of the modulation code candidate A is output as the calculation result 111 selected when the overflow state 123 is 1, but in the second embodiment of FIG. The DSV value input 105 on the modulation code candidate B side is input instead of the DSV value input 101 on the candidate A side, and the DSV value input on the modulation code candidate B side is included in the calculation result 111 selected when the overflow state 123 is 1. 10
5 is output. The contents of the input selection result 122 and the operation result 111 output-selected for the overflow state 123 for the selector 110 of FIG. 3 are shown in Table 2 as an operation truth table.

[0015]

[Table 2]

As a third embodiment, modulation code candidates A,
Another embodiment in which overflow occurs in the calculation of the DSV value for both B will be described with reference to FIG. In this figure, the selector 11 which operates differently from the first embodiment and the second embodiment is shown.
Only 0 is described.

In FIG. 4, the input of the selector 110 is only the operation result 104 and the operation result 107. When the overflow state 123 is "0", the input operation result indicated by the selection result 122 is converted to the operation result 111. When the overflow state 123 is “1”, all bits “0” are output to the selected operation result 111. Alternatively, a predetermined fixed value can be output. In this case, a candidate on an arbitrary side may be adopted as the modulation code. FIG.
Of the input selection result 122 and the output selection operation result 111 for the overflow state 123 for the selector 110
Are shown in Table 3 as an operation truth table.

[0018]

[Table 3]

Next, a fourth embodiment is shown in FIG. Here, the same portions as those in FIG. 1 are denoted by the same reference numerals. In this example, using the input code 100 and a selection result 122 to be described later as addresses, a modulation memory 124 that stores two modulation code candidates corresponding to each input code and outputs one modulation code from them is used as an input code 100. DSV memory 125, which simultaneously outputs DSV values of two modulation code candidates as addresses, DSV
A sign inverting circuit 126 that inverts the DSV values of the modulation code candidates A and B output from the memory 125 according to the final value of the NRZI modulation, a DSV value 101 and an integrated value 102 of one of the modulation code candidates A passing through the sign inversion circuit. , And outputs a calculation result 104. Similarly, a calculation unit 106 adds the DSV value 105 of the other modulation code candidate B and the integrated value 102 and outputs a calculation result 107, and inputs a DSV value of the modulation code candidate A. A digit overflow detection circuit 117 which receives 101, the integrated value 102, and the operation result 104 as input and outputs an overflow judgment result 118 of the operation result 104, the DSV value 105 of the modulation code candidate B, the integrated value 102, and the operation result 1
07 and the result 12 of the overflow of the calculation result 107
Overflow detection circuit 119 that outputs 0, operation result 104
And a comparator 108 which receives as input the operation result 107, compares the absolute values of the two, and outputs a comparison result 109,
9, a comparison control circuit 121 which receives the overflow judgment results 118 and 120 as input and outputs a selection result 122 and an overflow state 123, a selection result 122 and an overflow state 123
Selector 1 for selecting and outputting operation result 104, operation result 107 and DSV value input 101 of modulation code candidate A according to
10. A latch 112 which holds the selected operation result 111 and outputs the integrated value 102. The DSV value of the modulation code corresponding to the input code is obtained by adding the number of bits from the first bit to the first appearance of “1”, subtracting the number of bits until the next appearance of “1” from the first bit with 0 as the initial value. This is a value obtained by performing a 16-bit operation by alternately repeating addition and subtraction, such as adding the number of bits until “1” appears, and can take a positive value and a negative value. The modulation code 116 is subjected to NRZI modulation in an NRZI modulation circuit (not shown), and the level of the modulation signal is inverted each time "1" appears in the modulation code bit. Therefore, when the NRZI modulation result of the immediately preceding modulation code ends with “0”, the integration may be performed using the DSV value stored in the DSV memory 125 as it is, but the integration is performed using the immediately preceding modulation code. N
When the result of the RZI modulation ends with "1", the DSV value stored in the DSV memory 125 is inverted and the integration is performed. The sign inverting circuit 126 uses the modulation state signal 127 output from the NRZI modulation circuit (not shown) to generate DS.
The output of the V memory 125 is output as it is, or the output is inverted in sign. An example of sign inversion is shown in FIG. 7, and an example of the sign inversion circuit 126 is shown in FIG. In this example, a multiplexer for selecting one from two inputs and a 1-bit operation unit are provided. One input of each 1-bit operation unit is the output of the multiplexer, and the other input is a carry of a lower operation unit. Cout), and the modulation state signal 127 is input to the least significant 1-bit arithmetic unit. The sign inversion is realized by generating two's complements for the inputs 131A and 131B. That is, the modulation state signal 1
When 27 is "1", the multiplexer selects and outputs the inverted signal passed through the inverter and is input to the 1-bit arithmetic unit.
1B 2's complement is output. When the modulation state signal 127 is “0”, the multiplexers operate on the inputs 131A and 131A.
1B is selected and output, and only “0” is added in the 1-bit operation unit.
1A and 131B are output as they are. Although FIG. 8 shows only one system output of the two systems of DSV memory 125, it is actually composed of two systems. In this example, the case where the DSV value is 4 bits has been described, but the same applies to other numbers of bits, and the circuit configuration is not limited to the example of FIG. This sign inversion circuit 126
As described above, the DSV values 101 and 105 are represented by two's complement in the case of a negative number as described above, so that addition and subtraction can be performed by an adder circuit. The operation at the time of DSV calculation is the same as that of the embodiment of FIG.
If an overflow occurs in the integration, the modulation code of candidate B is used, and the DSV integrated value of candidate B is used as the DSV integrated value. If an overflow occurs in the DSV integration of the candidate B, the modulation code of the candidate A is adopted and the DSV
The DSV integrated value of the candidate A is adopted as the integrated value. When overflow occurs in the DSV integration of both candidates, the code on the side of A is selected as the modulation code, and the single DSV value of the selected modulation code is adopted as the DSV integration value. Similarly to the embodiment, the code on the B side can be selected. Alternatively, it can be set to a fixed value as in the third embodiment. The selection result 122 is the modulation memory 1
The address is 24, and when "0", the modulation code of candidate A is selected and output from the two modulation codes corresponding to input code 100, and when "1", the modulation code of candidate B is selected. And output.

FIG. 6 shows a fifth embodiment. Also in this figure, the same parts as those in FIGS. 1 and 5 are denoted by the same reference numerals. The difference between this embodiment and the fourth embodiment is that NRZI
The point lies in that the modulation state signal 127 after the modulation is obtained by counting the number of "1" in the modulation code 116. The modulation code 116 finally selected is sent to an NRZI modulation circuit (not shown) and held in a data latch 128. The held modulation code 130 is the counting circuit 1
Sent to 29, the number of "1" s in the code is counted. NRZ
In the I-modulation, the modulation output is inverted every time "1" appears in the input code. Therefore, if the number of "1" in the modulation code 130 is an even number, the modulation output state at the end of the NRZI modulation of this modulation code is Same as at the start. Conversely, if the number of “1” is odd, the state at the end is opposite to the state at the start. The counting circuit 129 counts the number of “1” in the modulation data 130 and determines whether the modulation data 130 is an even number or an odd number.
7 is output to the sign inversion circuit 125. The operation of the sign inversion circuit 125 is the same as that of the fourth embodiment. According to this configuration, since the modulation end state can be known without waiting for the modulation result of the NRZI modulation circuit (not shown), the processing of the next input code can be started quickly, and a series of DSV control processing can be performed. Has the advantage that it can be easily performed.

FIG. 9 shows a sixth embodiment. Also in this figure, the same parts as those in FIG. 1 are given the same numbers. The difference between this embodiment and the first embodiment is that the overflow determination results 132 and 134 indicating that the outputs of the overflow detectors 117 and 119 in FIG. Underflow determination result 13 indicating that underflow has occurred
3, 135, and an overflow / underflow state 136 indicating whether overflow is an overflow or an underflow is added to the output of the comparison control circuit 121, and an overflow / underflow state 136 is added to the input of the selector 110. When the overflowed modulation code candidate is selected, the value output to the selected operation result 111 which is the output of the selector 110 is changed depending on the difference between the overflow and the underflow. For example, the sign bit of the integrated value 102 is “0”,
The sign bit of the SV value input value 101 or 105 is "
If "0" and the corresponding operation result 104 or 107 is "1", it can be determined that an overflow has occurred, and the overflow detection circuit 117 or 119 indicates that an overflow has been detected.
To “1”, the underflow judgment result 133 or 135
Is set to “0”. At this time, if an overflow candidate is to be selected, the output overflow / underflow state of the comparison control circuit 121 becomes “1” indicating an overflow. On the other hand, the sign bit of the integrated value 102 is “1”, and the DSV value input value 101 or 1 to be added.
If the sign bit of 05 is “1” and the corresponding operation result 104 or 107 is “0”, it is possible to determine that an underflow has occurred, and the overflow detection circuit 117 or 119 indicates that an underflow has been detected. Alternatively, 134 is set to “0”, and the underflow determination result 133 or 135 is set to “1”. At this time, if an underflow candidate is to be selected, the output overflow / underflow state of the comparison control circuit 121 becomes “0” indicating underflow. Assuming that the same addition as that in the first embodiment has been performed, overflow will be described in each case.

First, a case will be described where the modulation code candidate A side overflows due to the addition of the DSV value and selects the one with the smaller absolute value of the DSV integrated value. At this time, the digit overflow detection circuit 117 on the modulation code candidate A side has detected an overflow, so that the overflow determination result 13
2 is “1”, the underflow determination result 133 is “0”,
Since the digit overflow detection circuit 119 on the modulation code candidate B side does not detect an overflow, the overflow determination result 134 is output as "0" and the underflow determination result 135 is output as "0".
The comparison control circuit 121 sets the modulation candidate B side as the selection result 122 since the overflow determination result 132 indicates an overflow even if the comparison result 109 of the comparator 108 indicates "0" indicating that the A side is selected. Is selected, and the normal calculation value is selected, and the overflow state 123 is set to "0", which indicates that there is no overflow.
The overflow / underflow state 136 may be either. The selector 110 selects the selection result 122 ("
1 "), the overflow state 123 (" 0 ") is input, the modulation code candidate B side without overflow is selected, and the operation result 107 of the modulation code candidate B side is output as the selected operation result 111. The selector 115 selects the selection result 12
2 (“1”) is input and the code 11 of the modulation code candidate B
4 is output as a modulation code 116.

Next, a case will be described in which the modulation code candidate A side underflows due to the addition of the DSV value and selects the one with the smaller absolute value of the DSV integrated value. At this time, the overflow detection circuit 117 on the modulation code candidate A side detects the underflow, and outputs the overflow determination result 132 as an output.
Is “0”, the underflow judgment result 133 is “1”, and the digit overflow detection circuit 119 on the modulation code candidate B side does not detect the digit overflow.
34 is “0” and the underflow determination result 135 is “0”.
And The comparison control circuit 121 selects the modulation candidate B as the selection result 122 because the underflow determination result 133 indicates an underflow even if the comparison result 109 of the comparator 108 indicates “0” indicating that the A side is selected. The normal calculation value is selected, and the overflow state 123 is set to "0" indicating that there is no overflow. The overflow / underflow state 136 may be either. The selector 110 selects the selection result 122 (“1”),
The overflow state 123 (“0”) is input, the modulation code candidate B side without overflow is selected, and the operation result 107 of the modulation code candidate B side is output to the selected operation result 111. The selector 115 receives the selection result 122 (“1”) and outputs the modulation code candidate B code 114 as the modulation code 116.

Next, the case where the modulation code candidate A overflows due to the addition of the DSV value and the modulation code candidate A is selected will be described. At this time, the overflow detection circuit 117 on the modulation code candidate A side has detected an overflow, so the overflow determination result 132 is "1", the underflow determination result 133 is "0", and the overflow on the modulation code candidate B side is detected. Since the circuit 119 does not detect overflow, the overflow determination result 134 is output as an output.
0, and the underflow determination result 135 is set to “0”.
When selecting the modulation code candidate A side according to other input conditions, the comparison control circuit 121 sets “0” indicating that the modulation candidate A side is selected as the selection result 122, and the overflow determination result 132 is “1”, so that the overflow state occurs. 123 is set to “1” indicating that there is an overflow, and the overflow / underflow state 136 is set to “1” indicating that an overflow has occurred. The selector 110 selects the selection result 122
(“0”), overflow state 123 (“1”), overflow / underflow state 136 (“1”)
Is selected, and the modulation code candidate A having overflow is selected, and the selected operation result 111 is the maximum value that can be indicated by the number of display digits, for example, since “signed 4 bits”, “+7”, 2 In hexadecimal display, “0111” is output. The selector 115 receives the selection result 122 (“0”) and inputs the code 113 of the modulation code candidate A to the modulation code 11.
Output as 6.

Next, a case where the modulation code candidate A side underflows due to the addition of the DSV value and selects the modulation code candidate A side will be described. At this time, the overflow detection circuit 117 on the modulation code candidate A side detects an underflow, so that the overflow determination result 132 is "0", the underflow determination result 133 is "1", and the overflow on the modulation code candidate B side is an output. Since the detection circuit 119 does not detect overflow, the overflow determination result 134 is output as "
0, and the underflow determination result 135 is set to “0”.
When selecting the modulation code candidate A side according to other input conditions, the comparison control circuit 121 overflows because the selection result 122 indicates that the modulation candidate A side is to be selected and the underflow determination result 133 is "1". The state 123 is set to “1” indicating that there is overflow, and the overflow / underflow state 136 is set to “0” indicating that there is an underflow. The selector 110 selects the selection result 122
(“0”), overflow state 123 (“1”), overflow / underflow state 136 (“0”)
Is selected, and the modulation code candidate A having overflow is selected, and the selected calculation result 111 is the minimum value that can be indicated by the number of display digits, for example, "-8" because it is a signed 4 bit here. In the two's complement display, "1000" is output. The selector 115 receives the selection result 122 (“0”) and inputs the code 113 of the modulation code candidate A to the modulation code 1.
Output as 16.

Next, a case will be described in which the modulation code candidate B side overflows due to the addition of the DSV value and selects the one with the smaller absolute value of the DSV integrated value. At this time, since the digit overflow detection circuit 117 on the modulation code candidate A side does not detect the digit overflow, the overflow judgment result 132 is output as an output.
0, the underflow judgment result 133 is “0”, and the overflow detection circuit 119 on the modulation code candidate B side has detected an overflow, so the overflow judgment result 1 is output as an output.
34 is “1” and the underflow determination result 135 is “0”.
And The comparison control circuit 121 selects the modulation candidate A as the selection result 122 because the overflow determination result 134 indicates an overflow even if the comparison result 109 of the comparator 108 indicates “1” indicating that the B side is selected. The normal calculation value is selected, and the digit overflow state 123 is set to "0" indicating that there is no overflow. The overflow / underflow state 136 may be either. The selector 110 selects the selection result 122 (“0”),
The overflow state 123 (“0”) is input, the modulation code candidate A having no overflow is selected, and the operation result 104 of the modulation code candidate A is output as the selected operation result 111. The selector 115 receives the selection result 122 (“0”) and outputs the code 113 of the modulation code candidate A as the modulation code 116.

Next, a case will be described in which the modulation code candidate B side underflows due to the addition of the DSV value and selects the one with the smaller absolute value of the DSV integrated value. At this time, since the digit overflow detection circuit 117 on the modulation code candidate A side does not detect the digit overflow, the overflow judgment result 132 is output as an output.
0, the underflow determination result 133 is “0”, and the overflow detection circuit 119 on the modulation code candidate B side has detected an underflow, so the overflow determination result 1 is output as an output.
34 is “0” and the underflow determination result 135 is “1”.
And The comparison control circuit 121 selects the modulation candidate A as the selection result 122 because the underflow determination result 135 indicates the underflow even if the comparison result 109 of the comparator 108 indicates “1” indicating that the B side is selected. The normal calculation value is selected, and the overflow state 123 is set to "0" indicating that there is no overflow. The overflow / underflow state 136 may be either. The selector 110 selects the selection result 122 (“0”),
The overflow state 123 (“0”) is input, the modulation code candidate A having no overflow is selected, and the operation result 104 of the modulation code candidate A is output as the selected operation result 111. The selector 115 receives the selection result 122 (“0”) and outputs the code 113 of the modulation code candidate A as the modulation code 116.

Next, the case where the modulation code candidate B side overflows due to the addition of the DSV value and the modulation code candidate B side is selected will be described. At this time, since the digit overflow detection circuit 117 on the modulation code candidate A side does not detect an overflow, the overflow determination result 132 is “0”, the underflow determination result 133 is “0”, and the digit overflow on the modulation code candidate B side is output. Since the detection circuit 119 has detected an overflow, the overflow judgment result 134 is output as an output.
1 ", and the underflow determination result 135 is" 0 ".
When selecting the modulation code candidate B side based on other input conditions, the comparison control circuit 121 indicates “1” indicating that the modulation candidate B side is to be selected as the selection result 122, and the overflow determination result 134 is “1”, so that the overflow state occurs. 123 is set to “1” indicating that there is an overflow, and the overflow / underflow state 136 is set to “1” indicating that an overflow has occurred. The selector 110 selects the selection result 122
("1"), overflow state 123 ("1"), overflow / underflow state 136 ("1")
Is input, and the modulation code candidate B having overflow is selected, and the selected operation result 111 is the maximum value that can be indicated by the number of display digits, for example, "+7", 2 In hexadecimal display, “0111” is output. The selector 115 receives the selection result 122 (“1”) and inputs the code 114 of the modulation code candidate B to the modulation code 11.
Output as 6.

Next, the case where the modulation code candidate B side underflows due to the addition of the DSV value and selects the modulation code candidate B side will be described. At this time, since the digit overflow detection circuit 117 on the modulation code candidate A side does not detect an overflow, the overflow determination result 132 is “0”, the underflow determination result 133 is “0”, and the digit overflow on the modulation code candidate B side is output. Since the detection circuit 119 has detected an underflow, the overflow determination result 134 is output as an output.
0 ", and the underflow determination result 135 is" 1 ".
When selecting the modulation code candidate B side based on other input conditions, the comparison control circuit 121 overflows since the selection result 122 indicates that the modulation candidate B side is to be selected, and the underflow determination result 135 is "1". The state 123 is set to “1” indicating that there is overflow, and the overflow / underflow state 136 is set to “0” indicating that there is an underflow. The selector 110 selects the selection result 122
("1"), overflow state 123 ("1"), overflow / underflow state 136 ("0")
Is input, and the modulation code candidate B side with overflow is selected, and the selected calculation result 111 is the minimum value that can be indicated by the number of display digits, for example, "-8" because it is 4 bits with a sign here. In the two's complement display, "1000" is output. The selector 115 receives the selection result 122 (“1”) and inputs the code 114 of the modulation code candidate B to the modulation code 1.
Output as 16.

Next, the modulation code candidates A and B are both DS
A case where overflow occurs due to the addition of the V value will be described. At this time, the digit overflow detection circuit 1 on the modulation code candidate A side
Reference numeral 17 indicates that the overflow determination result 132 is “1”, the underflow determination result 133 is “0” as an output because the overflow has been detected, and the overflow detection circuit 119 on the modulation code candidate B side has also detected an overflow. 134 is “1”, and the underflow determination result 135 is “0”. Comparison control circuit 12
1 indicates that both the overflow determination results 132 and 134 indicate overflow irrespective of the comparison result 109 of the comparator 108, so that the calculation is not normal regardless of which one is selected, and is designated by the immediately preceding modulation code. The state is input as one of the other input conditions, and a candidate for the specified state is selected. Here, it is the modulation code candidate A side. “0” indicating that the modulation candidate A side is selected as the selection result 122, and the overflow determination result 13
Since 2 and 134 are "1", the overflow state 123 indicates "1" indicating that overflow occurs, and the overflow / underflow state 136 indicates overflow.
The selector 110 sets the selection result 122 ("
0 ”), the overflow state 123 (“ 1 ”) and the overflow / underflow state 136 (“ 1 ”) are input, and the modulation code candidate A having overflow is selected.
The selected calculation result 111 outputs the maximum value that can be represented by the number of display digits, for example, “+7” because it is 4 bits with a sign, and “0111” in binary display. The selector 115 receives the selection result 122 (“0”) and outputs the code 113 of the modulation code candidate A as the modulation code 116.

Next, the modulation code candidates A and B are both DS.
A case where an underflow occurs due to the addition of the V value will be described. At this time, the digit overflow detection circuit 1 on the modulation code candidate A side
Reference numeral 17 indicates that the overflow determination result 132 is "0", the underflow determination result 133 is "1", and the overflow detection circuit 119 on the modulation code candidate B side has detected an underflow. The determination result 134 is “0”, and the underflow determination result 135 is “1”. Comparison control circuit 12
1 indicates that the underflow determination results 133 and 135 both indicate an underflow regardless of the comparison result 109 of the comparator 108, so that the calculation is not normal regardless of which one is selected, and is designated by the immediately preceding modulation code. The specified state is input as one of the other input conditions, and a candidate for the specified state is selected. Here, it is the modulation code candidate B side. The selector 110 selects the selection result 122 ("
1 "), the overflow state 123 (" 1 ") and the overflow / underflow state 136 (" 0 ") are inputted, and the modulation code candidate B side with overflow is selected.
The selected calculation result 111 outputs the minimum value that can be represented by the number of display digits, for example, “−8” because it is a signed 4 bit here, and “1000” in the two's complement display. The selector 115 receives the selection result 122 (“1”) and inputs the code 114 of the modulation code candidate B to the modulation code 11.
Output as 6. Table 4 shows an operation truth table of the selector 110 according to the sixth embodiment.

[0032]

[Table 4]

As described above, in the sixth embodiment, one DS
Even if an overflow occurs in the addition of the V value, the other candidate for which normal calculation is performed is selected, DSV integration is normally performed, and DC component suppression control is realized. Furthermore, even if an overflow occurs in the addition of the DSVs of all the modulation code candidates, if a candidate is selected according to the state specified by the immediately preceding modulation code, or a candidate that has an overflow in the addition of the DSV is selected. In this case, the DSV integrated value is set to the maximum value in the case of overflow and the minimum value in the case of underflow, and a normal modulation code is continuously selected, and a candidate which does not cause overflow in the next modulation code selection is selected. When the selected value is selected, the absolute value of the integrated value of the DSV is reduced, and when a candidate having overflow is selected, the maximum value or the minimum value is held in the integrated value of the DSV. Normally, DC component suppression control is realized.

As a seventh embodiment, the overflow detectors 117 and 119 which operate differently from the sixth embodiment are shown in FIG.
Shown in The outputs of the digit overflow detection circuits 117 and 119 of the sixth embodiment need only indicate whether an overflow has occurred or not, and if an overflow has occurred, indicate whether an overflow or an underflow has occurred. You may. The output of the digit overflow detection circuit 117 is "1" when digit overflow occurs, "0" when no digit overflow occurs, and 137 when the overflow occurs.
An overflow / underflow state 138 indicating "1" or "0" in the case of an underflow may be used. Similarly, the output of the overflow detector 119 may be set to "1" when an overflow occurs and to "0" when no overflow occurs. "The digit overflow state 139 indicates that the overflow occurs."
The overflow / underflow state 140 may indicate “1” or “0” in the case of underflow.

In each of the above-described embodiments, in order to simplify the explanation in each case, the DSV calculation judgment is made in 4 steps.
Although an example in which the number of bits is used has been described, the present invention is not limited to this number of bits, and can be similarly applied to an arbitrary number of bits.

Next, FIG. 11 shows an example in which the code modulation circuit according to the present invention is applied to an information recording / reproducing apparatus. In the figure, an optical disk 301 is a medium on which information is recorded, an optical pickup 302 irradiates a laser beam for recording and reproducing information and detects reflected light, and a reference numeral 303 denotes a medium rotating at a constant rotational speed or a constant line. A spindle motor rotating at a speed; 304, a read channel for detecting information signals and servo signals from reflected light detected by the optical pickup; 305, a code demodulation circuit for demodulating the information signal detected by the read channel; A servo circuit for performing a servo operation from the servo signal detected in the step 30,
Reference numeral 7 denotes a servo driver that drives a focusing actuator (not shown), a tracking actuator (not shown), a sled motor (not shown), and a spindle motor based on the output of the servo circuit. The information demodulated by the code demodulation circuit 305 is output to an error correction code generation / correction circuit 308.
Are corrected and transferred to the host device via the host interface 310. The memory 309 temporarily stores information when the error correction code generation / correction circuit 308 performs generation / correction. When recording information,
An error correction code is generated and added by an error correction code generation / correction circuit 308 to the information transferred from the host device via the host interface 310, and the DC component is suppressed by the code modulation circuit 312 using the code modulation method according to the present invention. The laser signal in the optical pickup 302 is modulated by the laser driver 311 and recorded on the optical disk 301. As described above, by using the code modulation circuit according to the present invention, it is possible to suppress the DC component of various recording information, and reduce the load on the optical pickup, read channel, and code demodulation circuit on the reproduction side. And
Reduce required performance and circuit scale. In particular, when forming an integrated circuit together with a code modulation circuit alone or other circuits,
The scale of the integrated circuit can be reduced. In the embodiment shown in FIG. 11, the optical disk device of the optical modulation recording system has been described as an example, but the scope of the present invention is not limited to this. , A magneto-optical disk device using a magnetic field modulation recording method,
Further, the present invention can be widely applied to magnetic disk devices, magnetic tape devices, and the like.

[0037]

According to the present invention, it is possible to continue the modulation normally without causing a judgment error even when the integration result of the DSV value overflows in the process of the DC component suppression control. Alternatively, even when an overflow occurs in the integration result of the DSV value and a correct value cannot be obtained, the influence does not continue.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a code modulation circuit with a digit overflow detection circuit.

FIG. 2 is a block diagram of a conventional code modulation circuit.

FIG. 3 is a block diagram of a selector according to a second embodiment which is an application example of FIG. 1;

FIG. 4 is a block diagram of a selector according to a third embodiment which is an application example of FIG. 1;

FIG. 5 is a block diagram of a fourth embodiment.

FIG. 6 is a block diagram of a fifth embodiment.

FIG. 7 is an explanatory diagram of a sign inversion operation.

FIG. 8 shows an embodiment of a sign inversion circuit.

FIG. 9 is a block diagram of a sixth embodiment.

FIG. 10 is a block diagram of a digit overflow detection circuit according to a seventh embodiment which is an application example of FIG. 9;

FIG. 11 shows an example in which a code modulation circuit is applied to an information recording / reproducing device.

[Explanation of symbols]

101 {modulation code candidate A side DSV value input, 102}
{DSV integrated value, 103} arithmetic unit, 104} arithmetic result, 105 {modulation code candidate B side DSV value input, 10}
6 operation unit, 107 operation result, 108 comparator, 109 comparison result, 110 selector, 111
{Selected operation result, 112} Latch, 113}
Modulation code candidate A, 114 {modulation code candidate B, 11
5 ‥‥ selector, 116 ‥‥ selected modulation code, 11
7, 119 ° digit overflow detection circuit, 118, 120 °
Overflow determination result, 121 {comparison control circuit, 122}
{Selection result, 123} Digit overflow state, 124
Modulation memory, 125 DSV memory, 126 sign inverting circuit, 127 modulation state signal, 128 data latch, 129 counting circuit, 130 modulation code,
131 input, 132, 134 overflow determination result, 133, 135 underflow determination result,
136 ‥‥ overflow / underflow state,
137, 139 Overflow state, 138, 140
‥‥ Overflow / underflow state 301 ‥‥ Optical disk, 302 ‥‥ Optical pickup, 3
03 spindle motor, 304 read channel, 305 code demodulation circuit, 306 servo circuit,
307 servo driver, 308 error correction code generation / correction circuit, 309 memory, 310 host interface, 311 laser driver, 312
‥ Code modulation circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhisa Nara 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information System (72) Toshifumi Takeuchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Co., Ltd. F-term in Hitachi Multimedia Systems Development Division (reference) 5D044 GL01 GL21

Claims (12)

[Claims] When converting an input code string comprising one word with a predetermined number of bits into a modulation code string having a different number of bits, an integrated DC component value is minimized from a plurality of modulation code candidates. In the code modulation method for selecting a modulation code, for each of a plurality of modulation code candidates, at the time of DC component integration calculation, occurrence of an overflow or underflow in which an integrated DC component value exceeds a handleable range is detected. Code modulation method. 2. The code modulation method according to claim 1, wherein a modulation code candidate in which no overflow or underflow has occurred is adopted as a modulation code. 3. The code modulation method according to claim 1, wherein when overflow or underflow occurs in all modulation code candidates, an arbitrary modulation code candidate is adopted as a modulation code. 4. The code modulation method according to claim 3, wherein a DC component value based on said arbitrary modulation code alone is adopted as said integrated DC component value. 5. The code modulation method according to claim 3, wherein a predetermined value is adopted as said integrated DC component value. 6. The code modulation method according to claim 3, wherein when overflow occurs in all modulation code candidates,
Alternatively, when an underflow has occurred in all modulation code candidates, a modulation code candidate having the largest absolute value of a DC component value among the modulation code candidates is adopted as the integrated DC component value. 7. When converting an input code sequence constituting one word with a predetermined number of bits into a modulation code sequence having a different number of bits, a modulation code with the smallest integration is determined from a plurality of modulation code candidates. A first arithmetic unit for adding a DC component value of a first modulation code candidate and an integrated value of a DC component up to that point to be described later, and a DC component value of a second modulation code candidate in a selected code modulation circuit; And a second computing unit that adds the integrated value of the DC component up to that and a later-described computing unit, a comparator that compares the computation results of the first and second computing units in absolute value, and outputs a comparison result, First digit overflow detection for detecting an overflow or an underflow by inputting a DC component value of a first modulation code candidate, an integrated value of DC components of a modulation code up to that, and an operation result of the first arithmetic unit. Circuit and the second A second digit overflow detection circuit for detecting an overflow or an underflow by inputting the DC component value of the modulation code candidate and the integrated value of the DC component of the modulation code up to that and the operation result of the second arithmetic unit;
A comparison control circuit that inputs an output result of the comparator, an output result of the first and second digit overflow detection circuits, and a determination condition necessary for another selection and outputs a determination result, and an output result of the comparison control circuit. Accordingly, from the calculation result of the first calculator, the calculation result of the second calculator, the integrated DC component value of the first modulation code candidate, and the integrated DC component value of the second modulation code candidate. A first selector that selects any one of them and outputs the integrated value of the DC component, a latch that holds the integrated value of the DC component output from the first selector, and an output result of the comparison control circuit. A code modulation circuit comprising a second selector for selecting and outputting the first modulation code candidate and the second modulation code candidate in response to the request. 8. When converting an input code sequence comprising one word with a predetermined number of bits into a modulation code sequence having a different number of bits, a modulation code having the smallest DC component is selected from a plurality of modulation code candidates. In a selected code modulation circuit, a first memory circuit that outputs the DC component values of the first and second modulation code candidates using the input code string as an address input and a first memory circuit that is an output of the first memory circuit. And a sign inversion circuit for inverting the sign of the DC component value of the second modulation code candidate as necessary, a DC component value of the first modulation code candidate passing through the sign inversion circuit, and a DC component up to that point described later. A first computing unit that adds the integrated value of the first modulation component, a second computing unit that adds the DC component value of the second modulation code candidate and the integrated value of the DC component up to that time, which will be described later, And the second computing unit A comparator for comparing the absolute values of the calculation results and outputting the comparison results; a DC component value of the first modulation code candidate and an integrated value of the DC components of the modulation codes up to that; and a calculation result of the first arithmetic unit A first overflow detector for detecting an overflow or an underflow, a DC component value of a second modulation code candidate, an integrated value of a DC component of a modulation code up to that, and the second arithmetic unit. A second digit overflow detection circuit for inputting the operation result and detecting an overflow or an underflow; an output result of the comparator and an output result of the first and second overflow detection circuits as inputs; A comparison control circuit to output, in accordance with an output result of the comparison control circuit, a calculation result of the first calculator, a calculation result of the second calculator, a DC component value of the first modulation code candidate, and Second modulation code A first selector that selects one of the complementary DC component values and outputs the integrated value of the DC component, a latch that holds an integrated value of the DC component that is the output of the first selector, A code modulation circuit comprising a second memory circuit that receives a result of the output of the comparison control circuit as a part of an address, receives the input code string as another address, and outputs a modulation code. 9. A method of converting an input code sequence forming one word with a predetermined number of bits into a modulation code sequence having a different number of bits, the modulation code having the smallest DC component from a plurality of modulation code candidates. In the selected code modulation circuit, a first memory circuit that receives the input code string as an address input and outputs DC component values of first and second modulation code candidates, and a first memory circuit that is an output of the first memory circuit. A sign inverting circuit for inverting the sign of the DC component value of the first and second modulation code candidates in accordance with the output of a counting circuit described later, and a DC component value of the first modulation code candidate passing through the sign inverting circuit; A first arithmetic unit that adds the integrated value of the DC component up to that time, and a second arithmetic unit that adds the DC component value of the second modulation code candidate and the integrated value of the DC component up to that time, which will be described later. An arithmetic unit and the second A comparator for comparing the calculation results of the first and second calculators with absolute values and outputting the comparison result; a DC component value of the first modulation code candidate and an integrated value of the DC component of the modulation code up to that; A first overflow detection circuit for detecting an overflow or underflow by inputting the operation result of the first arithmetic unit, and integrating the DC component value of the second modulation code candidate and the DC component of the modulation code up to that value A second digit overflow detection circuit for inputting a value and an operation result of the second arithmetic unit to detect an overflow or an underflow; an output result of the comparator and an output result of the first and second overflow detectors; A comparison control circuit that receives the output result as an input and outputs a determination result, and, in accordance with the output result of the comparison control circuit, the operation result of the first operation unit, the operation result of the second operation unit, and the first modulation DC component value of code candidate Selects one of the DC component value of the second modulation code candidates,
A first selector that outputs the integrated value of the DC component, a latch that holds the integrated value of the DC component that is the output of the first selector, and the output result of the comparison control circuit as a part of the address. A second memory unit that receives the input code string as an address and outputs a modulation code, a holding circuit that holds an output of the second memory unit, and “1” of the modulation code held in the holding circuit. And a counting circuit that counts the number of "", identifies whether the number is odd or even, and outputs a control signal to the sign inverting circuit. 10. An information recording / reproducing apparatus for performing code conversion of information by code modulation means based on a predetermined code modulation method and performing recording and reproduction on a recording medium, wherein the code modulation means comprises:
Code modulation means for selecting a modulation code having the smallest integrated DC component value from a plurality of modulation code candidates,
An overflow or an underflow in the DC component integration calculating means by each of the plurality of modulation code candidates is detected, a modulation code candidate in which no overflow or underflow has occurred is adopted as a modulation code, and an integration DC component by the modulation code is used. An information recording / reproducing apparatus characterized by performing subsequent modulation by employing a value. 11. An information recording / reproducing apparatus for performing code conversion of information by code modulation means based on a predetermined code modulation method and recording and reproducing the information on and from a recording medium, wherein the code modulation means comprises:
Code modulation means for selecting a modulation code having the smallest integrated DC component value from a plurality of modulation code candidates,
Each of the plurality of modulation code candidates detects an overflow or an underflow in the DC component integration calculating means, and when an overflow or an underflow occurs in all the modulation code candidates, an arbitrary modulation code is obtained from the plurality of modulation code candidates. An information recording / reproducing apparatus characterized in that the following modulation is performed and the subsequent modulation is performed by replacing the integrated DC component value with a predetermined value. 12. An information recording / reproducing apparatus for performing code conversion of information by code modulation means based on a predetermined code modulation method and recording and reproducing information on and from a recording medium, wherein the code modulation means comprises:
Code modulation means for selecting a modulation code having the smallest integrated DC component value from a plurality of modulation code candidates,
By each of a plurality of modulation code candidates, to detect overflow or underflow in the DC component integration calculation means, when overflow occurs in all modulation code candidates, or when underflow occurs in all modulation code candidates, An arbitrary modulation code is adopted from a plurality of modulation code candidates, and of the modulation code candidates, the one having the largest absolute value of the DC component value is adopted as the integrated DC component value, and subsequent modulation is performed. Information recording and reproducing apparatus.