JP2752564B2 - Leading one prediction device and floating point addition / subtraction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for performing addition normalization of a floating-point operation.
1. Field of the Invention The present invention relates to a leading one prediction device for predicting an amount of cancellation caused by addition and subtraction of a floating point operation, and a floating point addition and subtraction device using the leading one prediction device.

[0002]

2. Description of the Related Art In addition / subtraction of a floating-point operation, a significand value is sometimes subtracted by a combination of the sign of two operands and the addition / subtraction processing. If the absolute value of the difference between the exponent values of the two operands is 1 or less due to the subtraction of the mantissa value, two or more digits may be lost in the mantissa value. When the digit loss occurs, a process of calculating the digit loss amount to normalize the result of the mantissa value subtraction and a process of normalizing the subtraction result based on the digit loss amount are required. However, if the digit loss amount is calculated and normalized after waiting for the output of the mantissa value subtraction result, the execution time of addition normalization becomes longer. Therefore, it is known that the execution time of the addition normalization can be reduced by predicting the amount of cancellation at the time of normalization prior to or in parallel with the execution of the subtraction of the mantissa value by means independent of the addition operation. Was.

As a conventional example, there is Japanese Patent Application Laid-Open No. 2-144624. Hereinafter, this conventional example (conventional example 1) will be described with reference to the drawings. FIG. 8 is a diagram illustrating an algorithm for predicting the amount of cancellation in conventional example 1 using a state transition diagram. XOR (P, Propagate = propagation), AND (G, Generate = generate), NOR (Z, Zero =) resulting from a bit comparison of corresponding bit positions of two operands in two's complement representation
Zero) The amount of cancellation is predicted by looking at the combination of networks that process the state signal from the most significant bit side. First, the state of the most significant bit (GMS
B, ZMSB, PMSB), and if the status is G or Z
If so, a signal representing the number of shifts is generated. This number is a count of each successive state signal determined, and is generated as long as the state is true. When the state becomes false, the generation of the shift amount signal is stopped and the adjustment signal is issued. The adjustment signal is based on the carry from the lower bit at the false bit position, and the state of the false bit position is used to determine the sign of the addition result.

When the state of the most significant bit is P (PMSB), the stop of the shift number signal depends on the state of the state signal at the bit position following the false bit position. If the second state (Gj or Zj) at the false bit position is accompanied by a state signal of the third state (Z if P → G, G if P → Z), the generation of the shift signal is false if the third state is false. Or the shift signal is stopped at the bit position following the false bit position. In these cases, the adjustment signal will be based on the carry from the lower bit at the bit position where the shift signal was stopped, and the state at this position will determine the sign of the addition result.

By this mechanism, by means different from the addition / subtraction circuit, the number of consecutive 0 or 1 bits counted from the most significant bit generated by addition / subtraction of the mantissa value, that is, if the result of addition / subtraction of the mantissa value becomes positive, When the result of subtraction of the number of zeros and the mantissa value becomes negative, the number of consecutive ones in the two's complement representation can be obtained.

A conventional example is disclosed in Japanese Patent Application Laid-Open No. 5-53765.
There is an official gazette. Hereinafter, this conventional example (conventional example 2) will be described with reference to the drawings.

FIG. 9 is a block diagram of a leading one detection circuit of the second conventional example. Reference numeral 804 in the figure denotes a one-digit element of the leading one detection circuit.

The minuend X and the subtrahend Y are input to a redundant binary value generation circuit 901 for each bit, and a redundant binary value Zsd is generated. Explaining by focusing on the k-th bit, this redundant 2
The binary circuit executes the minuend Xk-subtraction Yk, and outputs the redundant binary value Zsdk = 1, 0, -1. Next, Zsdk is input to the intermediate sum intermediate carry generation circuit 902, and the intermediate sum S
k, generate an intermediate carry Ck.

[0009]

[Table 1]

Next, a scan value generating circuit 903 is used by using the intermediate sum Sk and the intermediate carry Ck-1 from the lower bit of one bit.
Generates a scan value Zk according to the rules in Table 2.

[0011]

[Table 2]

At this time, the number of 0s until the 1 appears for the first time from the most significant bit of Z indicates the bit shift amount during normalization or a value smaller by 1 bit than this. Is input to the priority encoder,
The bit shift amount at the time of normalization or a number smaller by one bit could be obtained. Further, by this mechanism, independently of the addition / subtraction circuit, it is possible to obtain the bit shift amount at the time of normalization or a number smaller by one bit regardless of the sign of the result of the subtraction of the mantissa value.

Next, FIG. 1 is a block diagram of a mantissa operation unit of a floating point addition / subtraction apparatus using a leading one detection circuit according to Conventional Example 2.
0 is shown. When subtraction is performed on two floating-point data X and Y consisting of a mantissa part, an exponent part, and a sign part, digit alignment processing, mantissa part addition / subtraction processing, and normalization processing are performed in this order. Hereinafter, a floating point addition / subtraction apparatus using the leading one detection circuit of the second conventional example shown in FIG. 10 will be described as an example.

First, the digit alignment processing is executed as follows. Exponent part of two input operands (Xe, Ye)
Is input to the subtraction circuit 305, the shift signal generation circuit 304, and the selector circuit 306. At the same time, the operand mantissa (1. Xf or 0. Xf, 1. Yf or 0.
Yf) is also input to the left / right one-digit shift circuit 301. At this time, in the subtraction circuit 305, the operand exponent values Xe,
Ye is subtracted, and the absolute value (Xe−Ye) and the sign value (Xe−
Ye). At the same time, the shift signal generation circuit 304 detects whether or not each input operand is a normalized number and determines the sign value (Xs, Ys) of the operand.
) And a subtraction execution signal SUB to create a control signal for shifting the two input operand mantissa values left and right. The left / right shift circuit 301 shifts two input operand mantissa values right or left based on the control signal from the shift signal generation circuit 304. The output of the left / right shift circuit 301 is input to the swap circuit 302, where the subtraction circuit 3
05 based on the code value (Xe-Ye) output from
The input data is swapped, the mantissa value of the operand having a small exponent value is input to the right barrel shift circuit 303, and the other operand mantissa value having a small exponent value is input to the addition / subtraction circuit 307. In the right barrel shift circuit 303, the input value is shifted to the right by the absolute value (Xe-Ye) of the difference between the operand exponent values output from the subtraction circuit 305. In this way, the digit matching process is executed.

Second, the addition / subtraction processing and the rounding processing are executed by the addition / subtraction circuit 307.

Third, the normalization processing will be described. In parallel with the second addition processing and the rounding processing, prediction of the amount of undercut is executed using the leading one detection circuit 311 and the priority encoder 308. The predicted undercut amount is output from the priority encoder 308 as Zae.

The left barrel shift circuit 309 shifts the output value of the addition / subtraction circuit 307 to the left using the predicted cancellation amount Zae output from the priority encoder 308 and outputs the result. At the same time, the value of the first digit higher than the decimal point is output to the signal line L1. L1 is "0" if the value after left shift is not normalized, and becomes "1" if the value is normalized. If L1 is "0", it means that the predicted cancellation amount Zae was smaller by one, so that it is necessary to shift left by one digit. This is performed by the alignment circuit 312.

At the same time, the predicted digit loss Zae
Is also input to the subtraction circuit 310, where the two subtractions Ze'-Zae and Ze'-Zae-1 are simultaneously performed and output to the data lines L2 and L3. Then, in the selector circuit 313, the value of the signal line L1 is "0".
If the value of the signal line L1 is "1", the subtraction result of Ze'-Zae-1 is output, and the normalization process is realized.

[0019]

However, in the configuration as in the above-mentioned prior art example 1, when the result of subtraction of the mantissa value becomes negative, the number of consecutive ones is obtained from the most significant bit in the two's complement representation. However, since the mantissa value is generally represented by an absolute value expression in the floating-point format, when performing the conversion, a one-bit error occurs between the number of consecutive ones and the bit shift amount at the time of normalization. Could occur.

Further, in the configuration as in the above-mentioned conventional example 2, the output bit shift amount is the bit shift amount at the time of normalization or the bit shift amount smaller by one bit than the bit shift amount at the time of normalization. In addition to the process of aligning the result of the mantissa value subtraction with the obtained bit shift amount, a process of further correcting a one-bit error is required.

Accordingly, the present invention has been made in consideration of the above problems, and has been made in consideration of the above problems. In parallel with or prior to subtraction of a mantissa value, a leading one prediction apparatus for accurately predicting a bit shift amount during normalization regardless of whether the subtraction result is positive or negative. And a floating-point adder / subtracter capable of performing high-speed arithmetic processing by simultaneously performing subtraction of a mantissa value and prediction of an accurate bit shift amount during normalization using the leading one prediction device. The purpose is to provide.

[0022]

In order to solve the above-mentioned problems, a leading one prediction apparatus according to the present invention comprises: means for generating the cancellation loss prediction amount within a one-bit error range; Means for generating propagation information, wherein a selector outputs an accurate bit shift amount necessary for normalization from the cancellation loss prediction amount depending on the presence or absence of the borrow.

Further, in the floating point addition / subtraction device of the present invention, in the addition / subtraction circuit of the mantissa value of the floating point operation, the two mantissa operands after the digit alignment processing are simultaneously input to the addition / subtraction circuit and the preceding one prediction device. The addition / subtraction circuit performs a subtraction, inputs the subtraction result to a barrel shifter, and shifts the subtraction result input to the barrel shifter using the bit shift amount output from the preceding one prediction device. Things.

[0024]

According to the present invention, by using the leading one prediction apparatus having the above-described configuration, the amount of cancellation at the time of mantissa value subtraction can be accurately predicted regardless of whether the subtraction result is positive or negative in parallel with or prior to the mantissa value subtraction. can do. In addition, by operating this leading one prediction device simultaneously with the mantissa value subtraction, the mantissa value subtraction result is obtained, and at the same time, the mantissa value subtraction result is normalized using the underscore amount prediction value. The device can be realized.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first-order prediction apparatus and a floating-point addition / subtraction apparatus according to one embodiment of the present invention will be briefly described below by comparing conventional example 2 with the present invention.

In the conventional example 2, there are a case where the bit shift amount at the time of normalization is correctly indicated and a case where the bit shift amount is indicated by one bit less. These cases will be described in more detail with examples.

For example, if the number of input bits is 8 for both the minuend and the subtrahend,
Consider the case of bits. The subtrahend X (7: 0) -subtract Y (7: 0) is executed, and if X> Y, the scan value Zk is first set to the third bit with the least significant bit as 0 bit.
Considering the situation where = 1 appears, Z = 000000αα: α = 0 or 1.

In this case, X (7: 0) -Y (7: 0) =
Assuming that the difference S is (7: 0), and the maximum value of the difference S is maxS1 and the minimum value is minS1, maxS1 = 00001111 minS1 = 000000101. Furthermore, the maximum value when indicating a correct bit shift amount is maxS2, the minimum value is minS2, and the maximum value when indicating a bit shift amount smaller by one bit is maxS3, and the minimum value is minS3.
Then, maxS2 = 00000011 minS2 = 0000001000 maxS3 = 000000111 minS3 = 000000101.

When a bit shift amount smaller by one bit is indicated, the bit for which Zk = 1 for the first time (the least significant bit is k =
0, and in this example, subtraction X by bits less than the next lower bit (k = 2) of k = 3)
It can be seen that this corresponds to the case where (2: 0) -Y (2: 0) becomes negative.

Similarly, when Y> X, X (2: 0) -Y
It can be seen that this corresponds to the case where (2: 0) becomes positive.

In this example, the case where the input is 8 bits has been described. However, with respect to a general arbitrary number of input bits, in the second conventional example, the subtraction result of the first bit lower than the bit of Zk = 1 for the first time is obtained. X> Y: X (k-1: 0) -Y (k-1: 0) <0 Y> X: X (k-1: 0) -Y (k-1: 0)> It can be seen that 0 indicates a bit shift amount smaller by one bit.

According to the present invention, in response to the case where the bit shift amount is smaller by one bit as described above, the corrected bit shift amount at the time of normalization is output.

That is, 1) X> Y, 2) Y> X, 3) X (k-1: 0)> Y (k-1: 0), 4) Y (k-1: 0)> X ( (k-1: 0) is used to correct and output the position of the scan value Zk = 1 that first appears from the most significant bit of the second conventional example, regardless of whether the subtraction result is positive or negative. In this case, an accurate bit shift amount can be output.

The manner in which the above four pieces of information are obtained is as follows. First, in order to distinguish 1) X> Y and 2) Y> X, a binary value created in Conventional Example 2 is used. Instead of creating a scan value Zk, a redundant binary value ZZk is created according to Table 3.

[0035]

[Table 3]

By doing so, ZZ which appears for the first time
1) When kＹ0 is ZZk = 1, 1) X> Y, ZZk = −1
2) Y> X. Note that ZZk =
0 corresponds to Zk = 0 in Conventional Example 2, and ZZKK0 is Zk
= 1.

Next, a description will be given of how information on the magnitude relationship between X (k-1: 0) and Y (k-1: 0) is obtained.

For example, when X (k-1: 0) <Y (k-1: 0), X (n: 0) -Y (m: 0) (n ≧ k, m ≧
When k) is executed, X (k-1: 0) -Y (k-1: 0)
In order to be <0, the digit of X (k) is borrowed (borrow B
x (k)) occurs. Similarly, X (k-1:
0)> Y (k-1: 0), Y (m: 0) -X
When (n: 0) is executed, Y (k-1: 0) -X (k-1
: 0) <0, so that a borrow (borrow By (k)) occurs in the digit of Y (k). Therefore, in this embodiment, a borrow propagation device is introduced, and Bx (k) and Bx (k)
By creating y (k), X (k-1: 0) and Y
(K-1: 0) is obtained.

Further, 1) X> Y and 4) Y (k-1: 0)
> X (k-1: 0) and 2) Y> X and 3) the most significant bit in the case of X (k-1: 0)> Y (k-1: 0) And a selector for increasing the number of consecutive ZZk = 0 by one up to ZZk ≠ 0, which appears for the first time after counting from the above, and according to these operations, the embodiment of the present invention can operate regardless of whether the subtraction result is positive or negative. The bit shift amount at the time of accurate normalization is obtained. In this way, if the output is input to the priority encoder, a bit shift number for normalizing the subtraction result can be obtained.

Using this bit shift number, the result of mantissa value subtraction in binary absolute value expression is shifted by the barrel shifter, thereby completing the mantissa value subtraction and normalization.

Hereinafter, description will be made with reference to the drawings.

FIG. 1 is a configuration diagram of a mantissa value addition circuit using the leading one prediction apparatus according to the present invention. In FIG. 1, reference numeral 11 denotes an addition / subtraction circuit that adds / subtracts a mantissa value and outputs an absolute value, 12 denotes a leading one prediction device having the configuration of the present invention for predicting the amount of cancellation, and 13 denotes a provisional one for normalization. A barrel shifter 14 for shifting a numerical value is a priority encoder.

FIG. 2 is a block diagram of the preceding one prediction device 12 according to the present invention when the input operand is 8 bits. In FIG. 2, reference numeral 21 denotes an undercut amount prediction device for predicting the undercut amount within a 1-bit error range independently of the addition / subtraction circuit. The scan value ZZk = redundant binary number described above by this apparatus =
The value of 1, 0, -1 is output. Reference numeral 22 denotes a borrow propagation device that outputs borrow propagation from lower bits independently of the addition / subtraction circuit. This apparatus outputs the above-mentioned borrows Bx (k) and By (k) for an arbitrary k. Numeral 23 denotes an output from the borrow propagation device 22, and the cancellation loss prediction device 2
1 is a selector for operating the bit shift amount necessary for normalization from the output of 1.

FIG. 3 is a detailed diagram of the undercut amount prediction device 21 written at the gate level. In FIG. 3, 31 and 32 are 8-bit input operands, PLUS33 and MINUS3.
4 is the scan value ZZk, PLUS = 1 and MINUS = 0 when ZZk = 1, PLUS = 0 and MINUS = when ZZk = 0.
0, ZZk = -1 is a signal line for outputting with PLUS = 0 and MINUS = 1. At this time, PLUS = 1 and MINUS
= 1 does not exist. Here, the number of consecutive 0 bits before ZZk ≠ 0 appears for the first time from the most significant bit, that is, PLUS for the first time from the most significant bit
= "1" or MINUS = PLUS = "0" or MINUS until the one that appears earlier, whichever comes first, appears
The number of “0” corresponds to the amount of cancellation in the case where the borrow from the lower bits is not taken into account. Here, when the number other than ZZk = 0, which appears for the first time, is ZZk = 1, the result of the subtraction of the mantissa value is positive, and when ZZK = -1, the result is negative.

Gx 35, Gy 36, and P37 are bit lines for each bit to be output to the borrow propagation device.
x 35 is (NOT operand X) AND (operand Y), ie, (Xk, Yk) = (0, 1), and Gy 36 is (operand X) AND (NOT operand Y), ie, (Xk,
Yk) = (1, 0), P37 is (operand X) XNOR
(Operand Y), that is, (Xk, Yk) = (0, 0)
Indicates or (1, 1). Gx (n) 35 is the operand X
Gy is a signal that the n-th bit has generated a borrow.
(N) 36 is a signal that the n-th bit of the operand Y has generated a borrow, and P (n) 37 is a signal that propagates the borrow from the lower bits. Gx (n) 35 and Gy
The reason why the sixth bit is not required in (n) 36 is that the sixth bit has already been considered in the redundant binary subtraction of the seventh bit.

FIG. 4 is a diagram in which the borrow propagation device 22 is written at the gate level. In FIG. 4, reference numeral 41 denotes an external clock input (clock 1) for precharging and discharging the precharge line and outputting the value of the precharge line, and reference numeral 42 denotes a clock for outputting the value of the precharge line. Input (clock 2)
It has a phase inverted from the phase of clock 1. 131
To 144 are precharge lines which are precharged when clock 1 is "0" and discharged when clock 1 is "1" and the path to ground is open. Bx 39 is a signal indicating that the borrow from the operand X has propagated to the n-th bit.
0 is a signal that the borrow from the operand Y has propagated to the n-th bit. The reason why neither the 0th bit nor the 1st bit is required in Bx 39 and By 40 is that
This is because there is no borrow that propagates to the 0th bit, and the borrow that propagates to the 1st bit has already been considered when ZZk is created.

In general, the borrow propagation is as follows: B (n) = G (n) + P (n) * G (n-1) = G (n) + P (n) * ｛P (n-1) * G ( n-2) + P (n-1) * P (n-2) * G (n-3) + ...) (1)

The bit precharge line for which the expression (1) holds is discharged when the clock 1 is "1". Therefore, since the discharged bit has a borrow from the lower bit, a bit having a borrow from the lower bit can be set by outputting through the inverter. However, the inverter is set high when the clock 1 is "0". By using a stray capacitance such as a wiring capacitance by using a tri-state inverter that becomes an impedance, the state when the clock signal is "1" can be maintained even when the clock signal is "0". I have.

FIG. 5 is a diagram showing the selector 23 in more detail. In FIG. 5, reference numeral 51 denotes a demultiplexer, which is information on the outputs Bx 39 and By 40 from the borrow propagation device 22, that is, Y, from the outputs PLUS 33 and MINUS 34 of the cancellation amount prediction device 21, that is, ZZk = 1, 0, -1. (K-1
: 0)> X (k-1: 0), X (k-1: 0)> Y (k-1:
0), the bit shift amount at the time of normalization is selected.

FIG. 6 is a diagram in which the demultiplexer 51 is written at the transistor level. If the output Bx (k) 36 from the borrow propagation device is "0", the position of PLUS (k) is output as LZA (k) as it is to the output PLUS (k) 33, and if it is "1", PLUS (k). Is corrected to one bit lower bit and output as LZA (k-1). Similarly, the output B from the borrow propagation device 22 is output to the output MINUS (k) 34.
If y (k) 37 is "0", the position of MINUS (k) is output as it is as LZA (k). If "1", MINUS (k) is output.
The position of (k) is modified to the lower bit by 1 bit, and LZA (k-
1) Output as This is when there is a borrow from the lower bit in the output from the cancellation amount prediction device 21, that is, 1) X> Y and 4) Y (k-1: 0)> X (k-1:
0) or 2) Y> X and 3) X (k-1: 0)> Y
In the case of (k-1: 0), the correction is made so that the amount of cancellation is increased by one bit. This output LZA (7:
When 0) is input to the priority encoder and the number of consecutive zeros from the most significant bit is counted, the number is the bit shift amount when normalizing.

Next, the operation of the above configuration will be described using an example. For example, as an input after mantissa digit alignment, an 8-bit operand X (7: 0) = 111010100, Y
(7: 0) = 1110101101 is X (7: 0) -Y
Consider the case where the input is (7: 0). First, the operand X (7: 0) = 111010 is sent to the undercut amount prediction device 21.
100, Y (7: 0) = 110010110 is input. In the actual binary subtraction, the difference S is S (7: 0) = 0000.
0111. The undercut amount prediction device 21 generates a scan value ZZk which is a redundant binary number, and as a result,
PLUS (7: 0) 33 = 00001000, MINUS (7:
0) 34 = 00000001, that is, ZZk = 000
0100T (T = -1) is output. At this stage, since ZZk ≠ 0, which appears for the first time counting from the highest order, is ZZk = 1, it is understood that X> Y.

As an output to the borrow propagation device 22, Gx (5: 0) 35 = 001001 indicating a bit where a borrow may occur from the operand X, and a bit where a borrow may occur from the operand Y Gy
(5: 0) 36 = 01010000, P indicating borrow propagation
(6: 1) 37 = 110011 is output.

Next, the precharge lines 131 to 144 are precharged by the borrow propagation device 22 when the clock 1 is "0", and when the clock 1 is "1", the Gx
(5: 0) 35 = 001001, Gy (5: 0) 36 =
010000, P (6: 1) 37 = 110011 is input. Then, the precharge lines 131, 132, 1
A path from 33, 134, 142, 143, 144 to ground is made and discharged. At this stage, when the clock 2 is set to “0”, Bx (7: 2) 39 = 0000111 and By (7:
2) 40 = 111000 is output. That is, ZZk ≠ 0 for the first time in ZZ (4) counting from the most significant bit, and since ZZk = 1, X> Y. Looking at the borrow Bx (4) at this time, Bx (4) = 1, and
In this case, for the first time counting from the most significant bit, ZZk ≠ 0
This is a case where it is necessary to increase the number of consecutive 0s by one bit until the point where.

Next, PLUS (7: 0) 33 is supplied to the selector 23.
= 00001000, MINUS (7: 0) 34 = 0000
0001 (ie, ZZ (7: 0) = (0000100
T) (T = -1)), Bx (7: 2) 39 = 00001
1, By (7: 2) 40 = 111000,
LZA (7: 0) 38 = 000000101 is output.
In LZA (7: 0) = 000000101, the number of bit shifts at the time of normalization is 5 bits because 5 bits of 0 continue from the most significant bit to the bit where 1 appears for the first time. Therefore, if this result is input to the priority encoder 24, which is viewed from the most significant bit, a decoded bit shift signal "101" for normalization input to the barrel shifter is obtained. This binary value "1
01 "is 5 in decimal notation.

In this example, X (7: 0) is replaced by Y (7: 7).
0), but X (7: 0)
Is smaller than Y (7: 0), the same effect can be obtained. In this embodiment, the leading one prediction device has a configuration independent of the mantissa value addition / subtraction circuit. However, if the borrow propagation device is shared with the mantissa value addition / subtraction circuit, the portion of the borrow propagation device can be omitted. . The configuration is not limited to the 8-bit configuration, but may be a general configuration of any number of bits.

When the present invention is used in a system in which one of the subtrahend and the subtrahend is always known to be larger than the other, the subtraction result is always either positive or negative. The signed loss amount prediction device can be replaced with a simple loss amount prediction device, and the device that generates information as to which borrow originated from which operand was generated from the operand of the smaller one of the minuend and the subtrahend It can be replaced with a device that propagates only borrows.

Further, in this embodiment, in the process of obtaining the number of consecutive zeros from the most significant bit generated by mantissa value subtraction, processing was performed using a redundant binary number expression. It is also possible to adopt a configuration in which processing is performed using only the information.

Next, FIG. 7 shows a block diagram of the mantissa operation unit of the floating-point addition / subtraction apparatus using the above-mentioned leading one prediction circuit. As in the second conventional example, when subtraction is performed on two floating-point data X and Y including a mantissa part, an exponent part, and a sign part, digit alignment processing, mantissa addition / subtraction processing, and normalization processing are performed in this order. Be executed.

Hereinafter, a floating point addition / subtraction apparatus using the leading one prediction circuit according to the present invention shown in FIG. 7 will be described as an example. The digit matching process and the mantissa addition / subtraction process perform the same operations as in the conventional example 2. The explanation of the first and second parts is as follows.
This has already been described in the section of the prior art. The processing up to this point is the same as that of the conventional example 2, but the normalization processing is performed by the left barrel shift circuit 309 with respect to the mantissa value.
Digit cancellation amount Z predicted based on the output of prediction device 321
Using ae, the output of the addition / subtraction circuit 307 is shifted to the left and output to complete. For the exponent value, the predicted cancellation amount Zae is input to the subtraction circuit 310, and the subtraction circuit 31
When 0, Ze'-Zae = Ze is executed, and Ze is output to complete the process.

[0060]

According to the present invention, an accurate value of the bit shift amount required for addition normalization is obtained by the above configuration, so that in the process of normalizing the addition result,
The digit is aligned with the bit shift amount output from the conventional leading one prediction device, and the most significant bit is 0.
In the case of (1), the process of shifting by one more bit can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a mantissa value addition circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a preceding one prediction device in the embodiment.

FIG. 3 is a detailed diagram of the undercut amount prediction device in the embodiment.

FIG. 4 is a detailed view of a borrow propagation device in the embodiment.

FIG. 5 is a detailed view of a selector in the embodiment.

FIG. 6 is a detailed view of a demultiplexer in the embodiment.

FIG. 7 is a block diagram of a floating-point addition / subtraction apparatus according to an embodiment of the present invention.

FIG. 8 is a diagram of a simple algorithm for predicting the amount of cancellation in Conventional Example 1.

FIG. 9 is a block diagram of a leading one detection circuit of Conventional Example 2.

FIG. 10 is a block diagram of a floating-point addition / subtraction device of Conventional Example 2.

[Explanation of symbols]

 12 Leading One Predictor 21 Digit Loss Predictor 22 Borrow Propagator 23 Selector

Claims (5)

(57) [Claims] 1. A method according to claim 1, wherein when the subtraction of the mantissa value in the addition / subtraction instruction of the floating-point operation causes a cancellation, the cancellation amount is calculated within a 1-bit error range.
Means for generating information on propagation of a borrow from the lower bit side generated at the time of mantissa value subtraction, and third means for operating the predicted canceling amount using the propagation information of the borrow. The third means outputs a bit shift amount for normalizing the mantissa value in which the cancellation has occurred from the cancellation loss prediction amount obtained by the first means according to the presence or absence of the borrow. A preceding one prediction device, characterized in that: 2. A method according to claim 1, wherein when a subtraction result of the mantissa value in the addition / subtraction instruction of the floating-point operation causes a cancellation, a cancellation cancellation prediction amount is generated within a 1-bit error range;
First to output whether the result of addition / subtraction instruction is positive or negative
Means for transmitting the borrow from the lower bit side generated at the time of the subtraction of the mantissa value, and generating the borrow generated at the time of the subtrahend-subtraction generated at the time of the subtraction of the mantissa of the operand; A second means for generating two types of borrows generated at the same time, and a third means for operating the predicted cancellation amount using propagation information of the borrows, wherein the subtraction result is a positive number. If the subtraction results in the presence or absence of a borrow occurring at the time of the subtrahend-subtraction, and if the subtraction result is a negative number, the first means obtains the result according to the presence or absence of the borrow occurring at the time of the subtrahend-subtraction. The first predicting apparatus according to claim 1, wherein the third means outputs a bit shift amount for normalizing the mantissa value in which the cancellation has occurred from the obtained cancellation amount. 3. The leading one prediction device according to claim 2, wherein a minuend X composed of an i-digit binary number and a decrement Y composed of a j-digit binary number (i and j are natural numbers) are each digit. First means for generating a redundant binary number Zsd in which each digit is composed of (1, 0, -1); and k-th digit (k is the least significant digit) from the lower order of the redundant binary value Zsd. Zsdk + using a redundant binary value Zsdk of (an integer where the bit is k = 0) and a redundant binary value Zsdk + 1 of the (k + 1) th digit from the lower order.
According to the equation Zsdk = 2Ck + Sk, the intermediate carry Ck is such that Ck = Zsdk when 1 = "1" or "-1", and CK = 0 when Zsdk + 1 = "0".
A second means for generating an intermediate sum Sk; "0" when the addition result of each digit of the intermediate carry Ck-1 from the lower digit and the intermediate sum Sk is "0"; A third means for generating a redundant binary number ZZk of "-1" at the time of 1. 4. A mantissa operand, an exponent operand,
2. A floating-point addition / subtraction device for adding or subtracting two operand data in a floating-point format having a sign operand, wherein an adder / subtractor circuit to which two mantissa operands after the digit-alignment processing are input is provided. And a barrel shifter to which an output of the adding / subtracting circuit is inputted, and a priority encoder to which a numerical value outputted from the preceding 1 predicting device is inputted to find the number of consecutive zeros from the top, A floating-point addition / subtraction device, wherein the output of the addition / subtraction circuit input to the barrel shifter is shifted and output using the output of the priority encoder. 5. A mantissa operand, an exponent operand,
3. A floating-point addition / subtraction apparatus for adding or subtracting two pieces of operand data in a floating-point format having a sign operand, wherein an add / subtract circuit to which two mantissa operands after digit alignment processing are input, respectively. And a barrel shifter to which an output of the adding / subtracting circuit is inputted, and a priority encoder to which a numerical value outputted from the preceding 1 predicting device is inputted to find the number of consecutive zeros from the top, A floating-point addition / subtraction device, wherein the output of the addition / subtraction circuit input to the barrel shifter is shifted and output using the output of the priority encoder.