GB1597468A - Conversion between linear pcm representation and compressed pcm - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO CONVERSION BETWEEN LINEAR PCM REPRESENTATION AND COMPRESSED PCM (71) We, the POST OFFICE, a British corporation established by Statute, of 23, Howland Street, London W1P 6HQ, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to the conversion of information which is coded in linear PCM form to compressed PCM form and to the conversion of information in compressed PCM form to linear PCM. The invention has particular application in telephony systems.

In for example a telephone exchange which employs a digital switch, analog speech information is converted into digital form prior to being fed to a digital switch. The speech information is generally encoded in the form of PCM code words. The PCM coded information may be produced initially as a linear representation and then compressed according to one of two compression characteristics into a form suitable for switching. The two types of compression characteristics are known as A-law and ,u-law as defined by CCITT recommendation G711. The present invention concerns the conversion of the linear representation to either A-law or ,u-law representation and vice versa.

We have found from a comparison of linear PCM and A-law characteristics that a relationship exists between the two representations which allows the conversion to be done by combinational logic according to a given algorithm.

In the case of -law a similar technique can be used if binary number 33 is added to the linear representation prior to it being applied to the combinational logic.

According to a first aspect of the present invention there is provided a converter for converting information in linear PCM representation to A-law representation comprising first combinational logic arranged to operate on a predetermined first number of bits of the linear code in accordance with a given algorithm to produce the A-law segment code, and second combinational logic arranged to operate on a predetermined second number of bits of the linear code and to select in accordance with the segment code predetermined ones of those bits to produce the A-law interval code.

The converter may have an n-way data selector, n being the number of bits of the interval code. The first combinational logic may comprise a plurality of NOR gates and said data selector comprises a matrix of field effect transistors, the transistors being switched on or off according to the outputs of said NOR gates such that said predetermined ones of the second number of bits are passed through the matrix.

The converter may include an inverter for converting offset binary into a linear magnitude code.

According to a second aspect of the present invention there is provided a converter for converting information in A-law representation to m bit linear PCM comprising an m-way data selector, the data selector comprising an array of gates which has inputs arranged to receive the interval bits of A-law code and control inputs arranged to receive the segment bits of the A-law code, the selector being operable in accordance with the segment code to direct the interval bits to selected ones of the m outputs and that the output from said array of gates is the m bit linear code.

The data selector may comprise a matrix of field effect transistors, the transistors being arranged to be switched on or off according to the segment code such that the bits of the interval code can pass to the selected outputs.

The converter may include an inverter for inverting the bits of the linear PCM code to produce two's complement linear PCM.

According to a third aspect of the present invention there is provided a converter for converting information in linear PCM representation to flaw representation comprising an addition circuit arranged to receive linear PCM representation and to add binary 33 thereto, first combinational logic arranged to operate on a predetermined first number of bits of the addition circuit output in accordance with a given algorithm to produce the ll-law segment code, and second combinational logic arranged to operate on a predetermined second number of bits of the addition circuit output and to select in accordance with the segment code predetermined ones of those bits to produce the ll-law interval code.

According to a fourth aspect of the present invention there is provided a converter for converting information in ,u-law representation to m bit linear PCM comprising an m way data selector, the data selector comprising an array of gates which has inputs arranged to receive the interval bits of the CL-law code and control inputs arranged to receive the segment bits of the 4aw code, the selector being operable in accordance with the segment code to direct the interval bits to selected ones of the m outputs of the selector, and a subtraction circuit connected to said m outputs, the subtraction circuit being arranged to subtract binary 33 from the output of the data selector to produce the linear code.

The invention will be described now by way of example only with particular reference to the accompanying drawings. In the drawings: Figures la and ib are curves comparing the A-law and -law characteristics; Figure 2 is a circuit diagram of apparatus in accordance with the present invention for converting linear PCM code words to A-law form; Figure 3 is a circuit diagram of a circuit for converting A-law to linear PCM form; Figure 4 illustrates an A-law to linear converter used in conjunction with a decoder of the type described in U.K. Patent Application No. 50096/76; (Serial No. 1580447) Figure 5 is a circuit diagram of a linear PCM to ,u-law converter, and Figure 6 is a circuit diagram of a ,u-law to linear PCM converter.

A-law and flaw PCM compression or companding characteristics are defined in CCITT recommendation G711. The code words for each characteristic are 8 bit words having a sign bit, 3 segment bits and 4 interval bits.

Figures la and 1b illustrate the difference between claw and A-law codes. The ordinate on the curve represents the value of linear samples whilst the abcissa represents segment numbers and intervals in each segment of the ll-law and A-law codes representative of those samples. In both flaw and A-law each segment is divided into 16 intervals. A-law increments in steps of 4 for segments 0 and 1 whereas -law has a single step of 1 and then 15 steps of 2 in segment 0 followed by 16 steps of 4 in segment 1 etc. Comparison of the curves in Figures la and 1b shows that if the ,u-law characteristic is shifted upwardly by 33 linear increments then ll-law corresponds exactly with A-law for segments 1 to 7.This fact can be made use of if the linear code is increased by 33 units before conversion to ll-law.

The conversion of linear PCM to A-law will be considered initially. The linear binary code, which can be produced by the coder described in U.K. Patent Application No.

5014/77, (Serial No. 1588219) must have sufficient definition, i.e. sufficient bits, to describe both the finest detail around zero amplitude and the full amplitude range. A study of the encoding law reveals that the ratio of the smallest decision level spacing to the total encoding range (maximum positive to maximum negative) is 4096. This means that the primary linear PCM encoder for encoding speech signals must have a 12 bit accuracy. The coder referred to above produces 14 bit linear PCM codewords in offset binary notation and it will be seen that the present converter operates on only the 12 most significant bits to produce A-law.

Referring now to Table 1 there are shown A-law codewords (second column) for sample or decision levels around zero amplitude (first column). The third column shows the corresponding linear offset binary code and the fourth column the linear sign and magnitude code. It can be seen that the linear and A-law codes near zero amplitude align exactly with no compression. It can also be seen that by inverting all bits of the linear codeword apart from the sign bit if the sign is negative (a zero) then the linear codewords take on a sign and magnitude notation completely symmetric about absolute zero. They have a double zero magnitude code similar to that of the A-law code. Further conversion to A-law format need thus only be considered for positive magnitudes assuming inversion has taken place if the linear codeword is negative.

Table 2 shows the linear binary magnitudes corresponding to a number of A-law codes for several segments. The first column shows various decision levels in decimal notation, the second column shows the linear magnitude code for each decision level and the third column shows the corresponding A-law code. As is well known to those skilled in the art A-law codewords in low number segments correspond to fewer linear decision levels than codewords in higher number segments; hence the term compression characteristic.

TABLE 1 Decimal A-law Linear Offset Linear Magnitude +4 10000100 100000000100 100000000100 +3 10000011 100000000011 100000000011 +2 10000010 100000000010 100000000010 +1 10000001 100000000001 100000000001 zero+0 10000000 100000000000 100000000000 -0 00000000 011111111111 000000000000 -1 00000001 011111111110 000000000001 -2 00000010 011111111101 000000000010 -3 00000011 011111111100 000000000011 -4 00000100 011111111011 000000000100 TABLE 2

Linear A-law Code Segment Decimal Magnitude Segment Interval 141 00010001101 140 00010001100 100 0001 139 00010001011 138 00010001010 137 00010001001 136 00010001000 4 135 00010000111 134 00010000110 133 00010000101 132 00010000100 100 0000 131 00010000011 130 00010000010 129 00010000001 B.P. 128 00010000000 127 00001111111 126 00001111110 011 1111 125 00001111101 124 00001111100 I I 3 ! I I 69 00001000101 z 011 0001 68 00001000100 67 00001000011 66 00001000010 2 011 0000 65 00001000001 B.P. 64 00001000000 TABLE 2 (cont'd)

Linear A-law Code Segment Decimal Magnitude Segment Interval 63 00000111111 010 1111 62 00000111111 61 00000111101 010 1110 60 00000111100 2 1 1 35 00000100011 010 0001 # 34 00000100010 33 00000100001 010 0000 B.P. 32 00000100000 31 00000011111 001 1111 30 00000011110 001 1110 0 AND I 1 2 00000000010 000 0010 1 00000000001 000 0001 Zero 0 00000000000 000 0000 In Table 2 only four segment boundaries, which are identified by the letters B.P., are shown but this is sufficient to illustrate the principle of the present converter given that later segments follow the same power of two compression law. It can be seen from Table 2 that the A-law segment code can be obtained by finding the position of the most significant 1 in the linear magnitude code.The remaining four bits (interval bits) of the A-law code are found to correspond exactly with the four bits immediately following the most significant "1" (apart from segment code zero which is easy to evaluate since segment zero can be defined by no. "1" in or above position 5). This rule forms the basis of the present converter as will now be described.

Consider a 12 bit linear PCM codeword in offset binary given by the following notation b12 bll blo b9 b8 b7 b6 b5 b4 b3 b2 bl b12 is the sign bit and if b12 = 1 the sample is positive and if b12= 0 the sample is negative The offset binary codeword corresponds to the magnitude code if b12 = 1 and can be coverted to a sign and magnitude form by inverting bits b1 to b11 if b12 = 0 to give the following code sgn M11 Mlo Mg M8 M7 M6 M5 M4 M3 M2 M1 The A-law segment code can be represented by S3 S2 Si. From the general rule it can be shown that S3 = M11 + M11 M10 + M11 M10 M9 + M11 M10 M9 M8 S2 = M11 + M11 M10 + M11 M10 M9 M8 M7 + M11 M10 M9 M8 M7 M6 S1 = M11 + M11 M10 M9 + M11 M10 M9 M8 M7 + M11 M10 M9 M8 M7 M6 M5 These reduce to give S3 = M11 + Mlo + Ms + M8 S2 = M11 + M10 + M9 M8 M7 + M9 M8 M6 S1 = M11 + M10 M9 + M10 M8 M7 + M10 M8 M6 M5 Given that the segment code can be formed from the magnitude code the segment code can be used to control a data selector to obtain the four required interval bits of the A-law code using the following table: TABLE 3 SEGMENT CODE INTERVAL CODE S3 S2 S1 14 I3 12 I1 0 0 0 M4 M3 M2 M1 0 0 1 M4 M3 M2 Ml 0 1 0 MS M4 M3 M2 0 1 1 M6 M5 M4 M3 1 0 0 M7 M6 M5 M4 1 0 1 M8 M7 M6 M5 1 1 0 Mg M8 M7 M6 1 1 1 Mlo M9 M8 M7 Figure 2 shows a circuit which can carry out conversion from linear PCM to A-law using the algorithm described above.This circuit is designed for use in conjunction with a coder of the type described in U.K. Patent Application No. 5014/77. (Serial No. 1588219) This coder produces PCM linear coded samples each having 14 bits. The samples are in offset binary form and appear at the output of an accumulator latch.

The circuit of Figure 2 has twelve inputs labelled b12 to bl, these being connected to receive the most significant bits of the 14 bit linear codewords. Each of the lines bl to bll is connected to an input of a respective one of 11 exclusive OR-gates 10 to 20 which constitute a controlled inversion stage. The twelfth line b12 is connected via an inverter 24 to the other input of the OR-gates 10 to 20. The outputs of the OR-gates 10 to 20 are the magnitude code bits M1 to M11 referred to above.

The outputs M1 to M10 of the OR-gates are connected to a transistor matrix 40 as shown in Figure 2. There is a field effect transistor at every node of the matrix although all the transistors are not shown.

The output lines M6 and M11 of the OR-gates are connected to combinational logic in the form of a group of NOR gates indicated generally at 42. The output line M5 is also connected to the NOR-gates 42 via an inverter 44. The NOR-gates 42 are so arranged and connected that they combine the magnitude bits according to expressions given above so that the outputs of the NOR-gates 45, 46 and 47 of the group 42 are the inverse of the segment bits Sl S2 S3. These can be inverted by inverters 55 to 57 to produce the segment bits Sl S2 S3 on lines 50 to 52.

The outputs of the NOR-gates 45, 46 and 47 and the outputs of the inverters 55 to 57 are connected to a series of NOR-gates 58 to 64, the outputs of which are connected to the columns of the transistor matrix 40. The matrix 40 operates as a 4-way data selector and has four output lines 70 to 73. The outputs on these lines constitute the interval bits Il to 14 of the A-law code.

The inputs to the NOR-gates 58 to 64 are so arranged that selected transistors of the matrix 40 are energised to allow four of the bits Ml to Mlo to pass to the outputs 70 to 73 according to Table 3 above. For example if the segment code is 011 then bits M6 M5 M4 M3 are the interval bits. In this case the output of the NOR-gate 62 goes high since it receives a zero on each input. The transistors in the column associated with that NOR gate are all switched on to couple lines M 6 to M 3 with respective outputs 70 to 73. The outputs of all other NOR-gates are low.

Conversion from A-law to linear PCM can be realised in a similar manner. A comparison of Tables 1 and 2 shows that the linear magnitude code can generally be obtained from the A-law code by positioning 114 I3 12 Il 1 in a 12 bit linear PCM number in accordance with the segment code. An A-law codeword produced by the converter only specifies that an input speech sample has a value lying between two particular decision levels. The larger the sample magnitude the wider the decision level spacing resulting in an approximately constant signal to quantisation noise ratio over a wide dynamic range of signal levels.To minimise the mean quantisation noise power the sample magnitude produced by a decoder for a given A-law code must lie midway between the pair of decision levels producing that codeword. If the reverse of the linear to A-law conversion were performed by positioning a 1 followed by 14 I3 I2 Il across an 11 bit magnitude field in accordance with the segment code, the resulting binary number would represent the lower of the two decision levels that went into producing A-law code. In order to describe the mid point of the decision levels a number generated by the above procedure must be incremented by an amount equal to half the weight of Il which is variable depending upon the segment code.It is straightforward however, since it is necessary only to add a 1 immediately after I1 and then position 1 141312 Il 1 in accordance with the segment code. The extra 1 requires the magnitude field to be increased to 12 bits (13 with the sign bit) for segments 0 and 1. For segment 0 the linear codeword is I4 I3 12 I1 1 positioned in the five least significant positions of the 12 magnitude bits.

The application for which the present converter has been designed requires PCM codewords in two's complement notation. This requires a positive number to have a zero for its sign bit and a negative number to have a 1 for its sign bit. The procedure for conversion can thus be summarised: form a 13 bit linear codeword as described above with a zero inserted in the sign bit position. If the input sample is positive the number formed is the required two's complement number. If the input sample is negative the number formed is the negative of the required number. The correct number can be obtained by inverting all bits and adding one to the least significant position.Table 4 summarises the way in which conversion can be carried out by positioning 114 13 I2 Il 1 in accordance with the segment code.

A circuit for performing this operation is shown in Figure 3. The input to the circuit is along lines 90 to 96. The interval bits 14 to Il are TABLE 4 SEGMENT SGN BITS TWO'S COMPLEMENT S3 S2 S1 1 0 0 0 0 0 0 0 0 0 0 0 I4 I3 I2 I1 1 1 0 0 1 0 0 0 0 0 0 0 1 I4 I3 I2 I1 1 1 0 1 0 0 0 0 0 0 0 1 I4 I3 I2 I1 1 0 1 0 1 1 0 0 0 0 0 1 I4 I3 I2 I1 1 0 0 1 1 0 0 0 0 0 0 1 I4 I3 I2 I1 1 0 0 0 1 1 0 1 0 0 0 1 I4 I3 I2 I1 1 0 0 0 0 1 1 1 0 0 0 1 I4 I3 I2 I1 1 0 0 0 0 0 1 1 1 1 0 1 I4 I3 I2 I1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 I4 I3 I2 I1 1 0 0 0 1 1 1 1 1 1 1 1 0 I4 I3 I2 I1 1 0 0 1 0 1 1 1 1 1 1 0 I4 I3 I2 I1 1 0 0 0 1 1 1 1 1 1 1 0 I4 I3 I2 I1 1 0 0 0 1 0 0 1 1 1 1 0 I4 I3 I2 I1 1 0 0 0 0 1 0 1 1 1 1 0 I4 I3 I2 I1 1 0 0 0 0 0 1 1 0 1 1 0 I4 I3 I2 I1 1 0 0 0 0 0 0 1 1 1 1 0 I4 I3 I2 I1 1 0 0 0 0 0 0 applied to lines 90 to 93 and the segment bits S1 to S3 to lines 94 to 96. The sign bit is fed along a line 100 to an inverter 101.

Each of the lines 90 to 93 is connected to a transistor matrix 108. The matrix 108 has a field effect transistor at every node although only some of these transistors are shown. The matrix 108 has two further inputs 106, 107 to which 1's can be applied and inputs 109 to which 0's can be applied.

The lines 94 to 96 are connected to NOR-gates 110 to 117 directly and via inverters 120 to 122. The output of each NOR-gate is connected to one column of the matrix 108. The output from the transistor matrix 108 has twelve output lines 125 to 136. The outputs which appear on these lines are the bits of the linear magnitude code. The output lines 125 to 136 are connected to a series of exclusive OR-gates 142 to 154. Each of the OR-gates 142 to 153 has an input which is connected to receive the inverted sign bit from the inverter 101. The outputs of the OR-gates are the bits al to a12 of Table 4.

The matrix 108 and the gates 110 to 117 constitute a 12 way data selector which is arranged to position the interval bits 1413 12 Il in a 12 bit magnitude code in accordance with the segment code. In operation the inverters 120 to 122 and the NOR-gates 110 to 117 demultiplex the segment code bits of the A-law code and apply control signals to the transistors of the matrix 108 in such a way that the bits 1 1413 I2 Il 1 are positioned correctly in the linear magnitude according to Table 4. The OR-gates 142 to 154 operate as a controlled inversion stage to produce the two's complement notation if the codeword is positive. If the codeword is negative a 1 has to be added as described below.

Figure 4 illustrates in block form the use of the A-law to linear converter in a decoder of the type described in U.K. Application No. 50096/76. (Serial No. 1580447) The A-law to linear converter is shown at 160 the output being connected to an offset addition and limiting circuit 161. The output of the circuit 161 is connected to a 13 bit latch 162 which is controlled by clock signals fed along a line 163. The latch 162 is connected to a delta sigma modulator which includes an accumulator 165 having an adder 166 and a latch 168. This type of circuit is described in Application No. 50096/76. (Serial No. 1580447) The sign bit a13 from the A-law to linear converter is loaded into a latch 169 using the same clock waveform that clocks the latch 162. The latched sign bit is then connected to the carry input of the addition circuit 166.Since the sign bit of the two's complement codeword is 1 when the codeword is negative a 1 is added infor negative codewords-as required. This arrangement obviates a need for an extra 13 bit adder to add the 1 for negative codewords.

The conversion of linear PCM to u-law can be realised in a similar manner. However, there are two main differences between the A-law characteristic described above and the u-law characteristic. Firstly u-law codewords have a magnitude code for zero consisting of the all ones state which then counts downwards to reach the all zero's state for maximum sample level. If one generates codewords starting from all zeros for the minimum sample magnitude through to all ones for the maximum and then inverts all bits before output the correct code results. It will be assumed that sign bit = 1 means a positive codeword.

Secondly the characteristics are of a different shape. A 14 bit linear code is required for conversion to ll-law. The basic difference is illustrated in Figures la and 1b which show that if the u-law characteristic is shifted upwardly by 33 linear increments it corresponds with A-law for segments 1 to 7.

The conversion from 14 bits offset binary to law can be carried out in the following manner which applies to segment 0 as well as segments 1 to 7.

Offset 14 bit binary code can be represented as follows: bl4 bl3 bl2 bll blo bg b8 b7 b6 b5 b4 b3 b2 b1 This is positive if bl4 = 1 and negative if bl4 = 0 Initially the sign and magnitude format are formed by using bl3 to bl for the magnitude if b14 = 1 and using bl3 to bl if bl4 = 0. Thus one obtains for the magnitude code: Sgn. M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 The next step is to add binary 33 to the magnitude code: i.e.

(Magnitude) M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 (33) 0 0 0 0 0 0 0 1 0 0 0 0 1 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 The required ll-law segment code S3 S2 S1 is determined from the position of the first 1 looking from the most significant end.The bits of the segment code are obtained as follows: S3 = C13 + C12 + Cii + C10 S2 = C13 + C12 + C11 C10 C9 + Cii C10 C8 S1 = C13 + C12 C11 + C12 C10 C9 + C12 C10 C8 C7 Given that the segment code can be obtained by combinational logic the segment code can be used to control data selectors to obtain the required interval bits of the ll-law code using the following table;; Segment Code Interval Bits S3 S2 S1 I4 I3 12 I1 0 0 0 C5 C4 C3 C2 0 0 1 C6 C5 C4 C3 0 1 O C7 C6 C5 C4 0 1 1 C8 c7 C6 C5 1 0 0 C9 C8 C7 C6 1 0 1 C10 C9 C8 C7 1 1 0 Cii C10 C9 C8 1 1 1 C12 Cii C10 C9 In the required output format referred to above the output bits are; Sgn. S3 S2 S1 I4 I3 I2 I1 Figure 5 illustrates a circuit which can carry out the conversion outlined above.This circuit is designed for use in conjunction with a coder of the type described in United Kingdom Patent Application No. 5014/77. (Serial No. 1588219) The coder part of this codec produces linear PCM coded samples each having 14 bits. These samples are in offset binary form and appear at the output of an accumulator latch.

The circuit shown in Figure 5 has 14 inputs labelled bl to b14, each of which is arranged to receive one of the bits of the linear PCM words. Each of the lines bl to b13 is connected to an input of a respective one of 13 exclusive OR-gates 210 to 222. The 14th line b14, which carries the sign bit, is connected via an inverter 224 to the other input of each of the OR-gates 210 to 222. The outputs from the OR-gates 210 to 222 are the magnitude code bits M1 to M13 referred to above. These bits are fed to an addition circuit 228 which is arranged to add binary 33 to the magnitude code bits M1 to M13. The outputs from the adder 228 are the bits C1 to C13 referred to above and these appear on lines C1 to C13 in Figure 5.

The output lines C9 to C13 of the addition circuit 228 have OR-gates 235 to 239 connected therein. The OR-gates 235 to 239 are provided to detect an overflow condition should the addition of binary 33 cause the number system to overflow and to limit the output in the case of such an overflow condition. The lines C2 to C12 are connected to a transistor matrix 240 in the manner shown in Figure 5. In the matrix there is a transistor at every node although all transistors are not drawn on the Figure.

The lines C8 to C13 are connected to a group of NOR-gates indicated generally at 242.

The line C7 is also connected to the NOR-gates 242 via an inverter 244. The outputs of NOR-gates 245 to 247 of the group 242 constitute the segment bits S1 S2 S3 and appear on lines 250 to 252. The outputs of the gates 245 to 247 are also connected via inverters 255 to 257 to a series of NOR-gates 258 to 265 the outputs of which are connected to the transistor matrix 240. The transistor matrix 240 is so connected that the bits C2 to C12 are selected according to the segment code in the manner set out in the table above to give the interval bits of the p-law code. The matrix 240 has four output lines 270 to 273 each of which is connected to a respective inverter circuit 275 to 278. The outputs of the inverters 275 to 278 constitute the four interval bits I1 I2 I3 I4 of the -law code.

A circuit for converting -law representation to linear PCM representation can also be realised in a similar manner to that described for A-law.

It can be shown that the linear magnitude corresponding to a particular ll-law magnitude can be obtained from the -law magnitude by positioning 1 I4 I3 I2 I1 1 in a 13 bit linear PCM number in accordance with the segment code of the -law representation and then subtracting binary 33 from the result.This procedure works for segment 0 as well as other segments and is summarised in the following table: Segment Code Intermediate Linear Magnitude S3 S2 S1 d13 d12 dll d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 0 0 0 0 0 0 0 0 0 0 1 14 13 I2 I1 0 0 1 0 0 0 0 0 0 1 14 I3 I2 I1 1 0 0 1 0 0 0 0 0 0 1 14 13 I2 I1 1 0 0 0 1 1 0 0 0 0 1 14 13 I2 I1 1 0 0 0 1 0 0 0 0 0 1 14 I3 I2 I1 1 0 0 0 0 1 0 1 0 0 1 14 13 I2 I1 1 0 0 0 0 0 1 1 0 0 1 14 13 I2 I1 1 0 0 0 0 0 0 1 1 1 1 14 I3 I2 I1 1 0 0 0 0 0 0 0 Subtraction of binary 33 can be carried out by adding the two's complement of 33 to the number as follows: d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 -33 1 1 1 1 1 1 1 0 1 1 1 1 1 C13 Cl2 Cii Cl0 C9 C8 C7 C6 C5 C4 C3 C2 C1 The result C13 through to C1 represents the required linear magnitude. Before this can be used by a digital delta-sigma modulator which is used in the decoder described in United Kingdom Patent Application No. 50096/76 (Serial No. 1580447) it has to be converted into a two's complement notation.If the code word is deemed to be positive this is achieved simply by inserting 0 for the sign bit before the C13 to C1 bits. If the codeword is deemed to be negative then a sign bit of 1 is inserted, all the bits C13 to C1 are inverted, and then 1 added to the bits C1 to C13.

A circuit for performing the conversion from -law to linear PCM shown in Figure 6. The input to the circuit is along lines 290 to 296. The interval bits I1 to I4 are applied to lines 290 to 293 and the segment bits S1 to S3 to lines 294 to 296. The sign bit is fed along line 300 and inverted by an inverter 301.

Each of the lines 290 to 293 is connected via an inverter 302 to 305 to a transistor matrix 308 which is of a form similar to that described with reference to Figure 3. The lines 294 to 296 are connected to NOR-gates 310 to 317 directly and via inverters 320 to 322. The NOR-gates 310 to 317 are connected to the transistor matrix 308. The output from the transistor matrix has 13 output lines 325 to 337. The outputs which appear on the lines 325 to 337 are the bits dl to d13 of the linear magnitude code. These lines 325 to 327 are connected to a subtraction circuit 340 which has 13 outputs which are connected to a series of OR-gates 342 to 354. Each of the OR-gates 342 to 354 has an input which is connected to receive the sign bit from the output of the inverter 301. The outputs of the OR-gates 342 to 354 represent the offset binary code to be applied to the delta-sigma modulator of the decoder described in Application No. 50096/76. (Serial No. 1580447) In operation the inverters 320 to 322 and the NOR-gates 310 to 317 demultiplex the segment code bits of the -law representation and control the transistor matrix 308 in such a way that the bits 1 I4 I3 I2 I1 1 are positioned correctly in the linear magnitude code. The linear magnitude code is then applied to the subtraction circuit 340 where binary 33 is subtracted from the code to give the desired output.

The 1 in the case of a negative codeword can be added in the manner described with reference to Figure 4.

WHAT WE CLAIM IS: 1. A converter for converting information in linear PCM representation to A-law representation comprising first combinational logic arranged to operate on a predetermined first number of bits of the linear code in accordance with a given algorithm to produce the A-law segment code, and second combinational logic arranged to operate on a predetermined second number of bits of the linear code and to select in accordance with the segment code predetermined ones of those bits to produce the A-law interval code.

2. A converter as claimed in claim 1 wherein the second combinational logic is an n way data selector, n being the number of bits of the interval code.

3. A converter as claimed in claim 2 wherein said first combinational logic comprises a plurality of NOR-gates and said data selector comprises a matrix of field effect transistors, the transistors being switched on or off according to the outputs of said NOR-gates such that said predetermined ones of the second number of bits are passed through the matrix.

4. A converter as claimed in any preceding claim including an inverter for converting offset binary into a linear magnitude code.

5. A converter for converting information in A-law representation to m bit linear PCM comprising an m-way data selector, the data selector comprising an array of gates which has inputs arranged to receive the interval bits of A-law code and control inputs arranged to receive the segment bits of the A-law code, the selector being operable in accordance with the segment code to direct the interval bits to selected ones of the m outputs and that the output from said array of gates is the m bit linear code.

6. A converter as claimed in claim 5 wherein the data selector comprises a matrix of field effect transistors, the transistors being arranged to be switched on or off according to the segment code such that the bits of the interval code can pass to the selected outputs.

7. A converter as claimed in claim 5 or claim 6 including an inverter for inverting the bits of the linear PCM code to produce two's complement linear PCM.

8. A converter for converting information in linear PCM representation to klaw representation comprising an addition circuit arranged to receive linear PCM representation and to add binary 33 thereto, first combinational logic arranged to operate on a predetermined first number of bits of the addition circuit output in accordance with a given algorithm to produce the p-law segment code, and second combinational logic arranged to operate on a predetermined second number of bits of the addition circuit output and to select in accordance with the segment code predetermined ones of those bits to produce the claw interval code.

9. A converter as claimed in claim 8 wherein the combinational logic is an n-way data selector, n being the number of bits of the interval code.

10. A converter as claimed in claim 9 wherein the first combinational logic comprises a plurality of NOR-gates and said data selector comprises a matrix of field effect transistors, the transistors being switched on or off according to the outputs of said NOR-gates such that said predetermined ones of the second number of bits are passed through the matrix.

11. A converter as claimed in any one of claims 8 to 10 including an inverter for converting offset binary into a linear magnitude code.

12. A converter for converting information in flaw representation to m bit linear PCM comprising an m-way data selector, the data selector comprising an array of gates which has inputs arranged to receive the interval bits of the ll-law code and control inputs arranged to receive the segment bits of the ll-law code, the selector being operable in accordance with the segment code to direct the interval bits to selected ones of the m outputs of the selector, and a subtraction circuit connected to said m outputs, the subtraction circuit being arranged to subtract binary 33 from the output of the data selector to produce the linear code.

13. A converter as claimed in claim 12 wherein the data selector comprises a matrix of field effect transistors, the transistors being arranged to be switched on or off according to the segment code such that the bits of the interval code can pass to the selected outputs.

14. A converter as claimed in claim 12 or claim 13 including an inverter for inverting the bits of the linear code to produce two's complement linear PCM.

15. A converter for converting information in linear PCM representation to A-law representation substantially as hereinbefore described with reference to and as shown in Figure 2 of the accompanying drawings.

16. A converter for converting information in A-law representation to linear PCM substantially as hereinbefore described with reference to and as shown in Figure 3 of the accompanying drawings.

17. A converter for converting information in linear PCM representation to ll-law representation substantially as hereinbefore described with reference to and as shown in Figure 5 of the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (18)

**WARNING** start of CLMS field may overlap end of DESC **. The 1 in the case of a negative codeword can be added in the manner described with reference to Figure 4. WHAT WE CLAIM IS:

1. A converter for converting information in linear PCM representation to A-law representation comprising first combinational logic arranged to operate on a predetermined first number of bits of the linear code in accordance with a given algorithm to produce the A-law segment code, and second combinational logic arranged to operate on a predetermined second number of bits of the linear code and to select in accordance with the segment code predetermined ones of those bits to produce the A-law interval code.

2. A converter as claimed in claim 1 wherein the second combinational logic is an n way data selector, n being the number of bits of the interval code.

3. A converter as claimed in claim 2 wherein said first combinational logic comprises a plurality of NOR-gates and said data selector comprises a matrix of field effect transistors, the transistors being switched on or off according to the outputs of said NOR-gates such that said predetermined ones of the second number of bits are passed through the matrix.

4. A converter as claimed in any preceding claim including an inverter for converting offset binary into a linear magnitude code.

5. A converter for converting information in A-law representation to m bit linear PCM comprising an m-way data selector, the data selector comprising an array of gates which has inputs arranged to receive the interval bits of A-law code and control inputs arranged to receive the segment bits of the A-law code, the selector being operable in accordance with the segment code to direct the interval bits to selected ones of the m outputs and that the output from said array of gates is the m bit linear code.

6. A converter as claimed in claim 5 wherein the data selector comprises a matrix of field effect transistors, the transistors being arranged to be switched on or off according to the segment code such that the bits of the interval code can pass to the selected outputs.

7. A converter as claimed in claim 5 or claim 6 including an inverter for inverting the bits of the linear PCM code to produce two's complement linear PCM.

8. A converter for converting information in linear PCM representation to klaw representation comprising an addition circuit arranged to receive linear PCM representation and to add binary 33 thereto, first combinational logic arranged to operate on a predetermined first number of bits of the addition circuit output in accordance with a given algorithm to produce the p-law segment code, and second combinational logic arranged to operate on a predetermined second number of bits of the addition circuit output and to select in accordance with the segment code predetermined ones of those bits to produce the claw interval code.

9. A converter as claimed in claim 8 wherein the combinational logic is an n-way data selector, n being the number of bits of the interval code.

10. A converter as claimed in claim 9 wherein the first combinational logic comprises a plurality of NOR-gates and said data selector comprises a matrix of field effect transistors, the transistors being switched on or off according to the outputs of said NOR-gates such that said predetermined ones of the second number of bits are passed through the matrix.

11. A converter as claimed in any one of claims 8 to 10 including an inverter for converting offset binary into a linear magnitude code.

12. A converter for converting information in flaw representation to m bit linear PCM comprising an m-way data selector, the data selector comprising an array of gates which has inputs arranged to receive the interval bits of the ll-law code and control inputs arranged to receive the segment bits of the ll-law code, the selector being operable in accordance with the segment code to direct the interval bits to selected ones of the m outputs of the selector, and a subtraction circuit connected to said m outputs, the subtraction circuit being arranged to subtract binary 33 from the output of the data selector to produce the linear code.

13. A converter as claimed in claim 12 wherein the data selector comprises a matrix of field effect transistors, the transistors being arranged to be switched on or off according to the segment code such that the bits of the interval code can pass to the selected outputs.

14. A converter as claimed in claim 12 or claim 13 including an inverter for inverting the bits of the linear code to produce two's complement linear PCM.

15. A converter for converting information in linear PCM representation to A-law representation substantially as hereinbefore described with reference to and as shown in Figure 2 of the accompanying drawings.

16. A converter for converting information in A-law representation to linear PCM substantially as hereinbefore described with reference to and as shown in Figure 3 of the accompanying drawings.

17. A converter for converting information in linear PCM representation to ll-law representation substantially as hereinbefore described with reference to and as shown in Figure 5 of the accompanying drawings.

18. A converter for converting information in -law representation to linear PCM

substantially as herein before described with reference to and as shown in Figure 6 of the accompanying drawings.