CN114710150B - CMOS full adder - Google Patents
CMOS full adder Download PDFInfo
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- CN114710150B CN114710150B CN202210602693.6A CN202210602693A CN114710150B CN 114710150 B CN114710150 B CN 114710150B CN 202210602693 A CN202210602693 A CN 202210602693A CN 114710150 B CN114710150 B CN 114710150B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
Abstract
The invention relates to a CMOS full adder. The source electrode of a tube P1 in the full adder is connected to VDD, the grid electrode of a tube P1 is connected with the drain electrode of a tube N1 and the grid electrode of a tube N2, and the drain electrode of a tube P1 is connected with the source electrode of a tube P2; the grid of the tube P2 is connected with A, and the drain of the tube P2 is connected with the source of the tube N1, the source of the tube N2, the grid of the tube N4, the grid of the tube N5, the grid of the tube P4 and the grid of the tube P5; the grid of the tube N1 and the drain of the tube N2 are connected with A, the source of the tube P3 is connected with VDD, the drain of the tube P3 is connected with the drain of the tube N3 and the source of the tube P4, the grid of the tube P3 is connected with the grid of the tube N3 and is connected with CIN, the source of the tube N3 is connected with VSS, the drain of the tube P4 is connected with the source of the tube N4, and the drain of the tube N4 is connected with CIN; the source of the tube P5 is connected to CIN, the drain of the tube P5 is connected to the source of the tube N5, and the drain of the tube N5 is connected to A. The invention has the characteristics of small area and low power consumption.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a CMOS full adder.
Background
The full adder proposed in the CMOS full adder and the multi-bit full adder has 28 transistors including 14 PMOS transistors and 14 NMOS transistors, and the circuit area and the energy consumption of the full adder are both large; to improve the above problem, ISSCC paper "An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision computer-In Memory Macro In 22nm for Machine-Learning Edge Applications" proposes a Full adder consisting of 14 transistors of 7 NMOS transistors and 7 PMOS transistors, but its driving capability is weak and area economy is poor.
Therefore, a new full adder is needed to solve the above problems.
Disclosure of Invention
The invention aims to provide a CMOS full adder which has the characteristics of small area and low power consumption.
In order to achieve the purpose, the invention provides the following scheme:
a CMOS full adder comprising: tube N1, tube N2, tube N3, tube N4, tube N5, tube P1, tube P2, tube P3, tube P4, and tube P5;
the source electrode of the tube P1 is connected to a power supply voltage VDD, the grid electrode of the tube P1 is connected with the drain electrode of the tube N1 and the grid electrode of the tube N2, and the drain electrode of the tube P1 is connected with the source electrode of the tube P2; the grid of the tube P2 is connected with the input signal A, and the drain of the tube P2 is connected with the source of the tube N1, the source of the tube N2, the grid of the tube N4, the grid of the tube N5, the grid of the tube P4 and the grid of the tube P5; the grid of the tube N1 and the drain of the tube N2 are both connected with an input signal A, the source of the tube P3 is connected with a power supply voltage VDD, the drain of the tube P3 is connected with the drain of the tube N3 and the source of the tube P4, the grid of the tube P3 is connected with the grid of the tube N3 and is connected with a carry input signal CIN, the source of the tube N3 is connected with a power supply ground signal VSS, the drain of the tube P4 is connected with the source of the tube N4, a node between the drain of the tube P4 and the source of the tube N4 is a summation output S, and the drain of the tube N4 is connected with the carry input signal CIN; the source electrode of the tube P5 is connected with a carry input signal CIN, the drain electrode of the tube P5 is connected with the source electrode of the tube N5, a node between the drain electrode of the tube P5 and the source electrode of the tube N5 is used for carrying output CO, and the drain electrode of the tube N5 is connected with an input signal A; the gate of the transistor P1, the drain of the transistor N1, and the gate of the transistor N2 are all connected to the input signal B.
Optionally, the tube N1, the tube N2, the tube N3, the tube N4 and the tube N5 are all NMOS transistors.
Optionally, the pipe P1, the pipe P2, the pipe P3, the pipe P4 and the pipe P5 are all PMOS transistors.
Optionally, a loop formed by the pipe N1, the pipe N2, the pipe N5, the pipe P1, the pipe P2, and the pipe P5 is an operation unit of the carry output CO of the CMOS full adder.
Optionally, a loop formed by the pipe N1, the pipe N2, the pipe N3, the pipe N4, the pipe P1, the pipe P2, the pipe P3 and the pipe P4 is an operation unit of the summation output S of the CMOS full adder.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a CMOS full adder, comprising: tube N1, tube N2, tube N3, tube N4, tube N5, tube P1, tube P2, tube P3, tube P4, and tube P5, and the specific logic of the full addition operation is realized by 10 transistors. The full adder structure provided by the invention has the characteristics of small area and low power consumption.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a CMOS full adder according to the present invention;
FIG. 2 is a schematic diagram of an arithmetic unit structure of a carry output CO of a CMOS full adder according to the present invention;
fig. 3 is a schematic diagram of an operation unit structure of a summation output S of a CMOS full adder according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a CMOS full adder which has the characteristics of small area and low power consumption.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic structural diagram of a CMOS full adder provided by the present invention, and as shown in fig. 1, the CMOS full adder provided by the present invention includes: tube N1, tube N2, tube N3, tube N4, tube N5, tube P1, tube P2, tube P3, tube P4, and tube P5.
The source electrode of the tube P1 is connected to a power supply voltage VDD, the grid electrode of the tube P1 is connected with the drain electrode of the tube N1 and the grid electrode of the tube N2, and the drain electrode of the tube P1 is connected with the source electrode of the tube P2; the grid of the tube P2 is connected with the input signal A, and the drain of the tube P2 is connected with the source of the tube N1, the source of the tube N2, the grid of the tube N4, the grid of the tube N5, the grid of the tube P4 and the grid of the tube P5; the grid of the tube N1 and the drain of the tube N2 are both connected with an input signal A, the source of the tube P3 is connected with a power supply voltage VDD, the drain of the tube P3 is connected with the drain of the tube N3 and the source of the tube P4, the grid of the tube P3 is connected with the grid of the tube N3 and is connected with a carry input signal CIN, the source of the tube N3 is connected with a power supply ground signal VSS, the drain of the tube P4 is connected with the source of the tube N4, a node between the drain of the tube P4 and the source of the tube N4 is a summation output S, and the drain of the tube N4 is connected with the carry input signal CIN; the source electrode of the tube P5 is connected with a carry input signal CIN, the drain electrode of the tube P5 is connected with the source electrode of the tube N5, a node between the drain electrode of the tube P5 and the source electrode of the tube N5 is used for carrying output CO, and the drain electrode of the tube N5 is connected with an input signal A; the gate of the transistor P1, the drain of the transistor N1 and the gate of the transistor N2 are all connected to the input signal B.
The addition operation of the full adder needs to consider not only two input data but also carry input data transferred from low order to high order, and the operation expression of the full adder carry output CO is as follows:
the operation expression of the summation output S is as follows:
the logical relationship between the input signal A, B and the carry input signal CI and the carry output signal CO and the sum output signal S is shown in table 1:
TABLE 1
That is, when a =0, B =0, and CIN =0, the tube N1 and the tube N2 are turned off, and the tube P1 and the tube P2 are turned on, so that the gates of the tube N4, the tube N5, the tube P4, and the tube P5 are at a high level, the tube P4 and the tube P5 are turned off, the tube N4 and the tube N5 are turned on, so that the sum output signal S = CIN =0, and the carry output signal CO = a = 0.
If a =0, B =0, and CIN =1, the tube N1 and the tube N2 are turned off, and the tube P1 and the tube P2 are turned on, so that the gates of the tube N4, the tube N5, the tube P4, and the tube P5 are at a high level, the tube P4 and the tube P5 are turned off, the tube N4 and the tube N5 are turned on, so that the sum output signal S = CIN =1, and the carry output signal CO = a = 0.
If a =0, B =1, and CIN =0, the tube N1 and the tube P1 are turned off, and the tube N2 and the tube P2 are turned on, and the input a is connected to the gates of the tube N4, the tube N5, the tube P4, and the tube P5, so that the tube P4 and the tube P5 are turned on, and the tube N4 and the tube N5 are turned off, so that the sum output signal S is an inverted signal of CIN, i.e., S =1, and the carry output signal CO = CIN = 0.
If a =1, B =0, and CIN =0, the tube N1 and the tube P1 are turned on, and the tube N2 and the tube P2 are turned off, the input B is connected to the gates of the tube N4, the tube N5, the tube P4, and the tube P5, the tube P4 and the tube P5 are turned on, and the tube N4 and the tube N5 are turned off, so that the sum output signal S is an inverted signal of CIN, i.e., S =0, and the carry output signal CO = CIN = 1.
If a =0, B =1, and CIN =1, the tube N1 and the tube P1 are turned off, and the tube N2 and the tube P2 are turned on, and the input a is connected to the gates of the tube N4, the tube N5, the tube P4, and the tube P5, so that the tube P4 and the tube P5 are turned on, and the tube N4 and the tube N5 are turned off, so that the sum output signal S is an inverted signal of CIN, i.e., S =0, and the carry output signal CO = CIN = 1.
If a =1, B =0, and CIN =1, the tube N1 and the tube P1 are turned on, and the tube N2 and the tube P2 are turned off, the input B is connected to the gates of the tube N4, the tube N5, the tube P4, and the tube P5, the tube P4 and the tube P5 are turned on, and the tube N4 and the tube N5 are turned off, so that the sum output signal S is an inverted signal of CIN, i.e., S =0, and the carry output signal CO = CIN = 1.
If a =1, B =1, and CIN =1, the tube P1 and the tube P2 are turned off, and the tube N1 and the tube N2 are turned on, and the input B is connected to the gates of the tube N4, the tube N5, the tube P4, and the tube P5, so that the tube P4 and the tube P5 are turned off, and the tube N4 and the tube N5 are turned on, so that the sum output signal S = CIN =1, and the carry output signal CO = a = 1.
The CMOS full adder completes full addition operation through the following three steps:
the first step is as follows: enabling an input signal A, an input signal B and a carry input signal CI;
the second step is that: according to the enabled input signal, firstly obtaining a carry output signal CO;
the third step: the sum signal S is derived from the enabled input signal (the path for the sum operation may be one more inverter delay than the path for the carry output, so the sum signal S is said to lag the carry output signal CO output, but the actual inverter delay time is very short and negligible).
As a specific example, the transistor N1, the transistor N2, the transistor N3, the transistor N4 and the transistor N5 are all NMOS transistors.
As a specific example, the P1, P2, P3, P4 and P5 transistors are PMOS transistors.
As shown in fig. 2, the loop formed by the pipe N1, the pipe N2, the pipe N5, the pipe P1, the pipe P2 and the pipe P5 is an arithmetic unit of the carry output CO of the CMOS full adder.
As shown in fig. 3, the loop formed by the pipe N1, the pipe N2, the pipe N3, the pipe N4, the pipe P1, the pipe P2, the pipe P3 and the pipe P4 is an arithmetic unit of the summation output S of the CMOS full adder.
The full adder comprises 5 PMOS transistors and 5 NMOS transistors, and the number of the used transistors is small, so that the area is optimized compared with the full adder structure in the prior art.
The NMOS transistor and the PMOS transistor have good matching performance, and meanwhile, the whole circuit uses fewer transistors and has lower power consumption.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (5)
1. A CMOS full adder, comprising: tube N1, tube N2, tube N3, tube N4, tube N5, tube P1, tube P2, tube P3, tube P4, and tube P5;
the source electrode of the tube P1 is connected to a power supply voltage VDD, the grid electrode of the tube P1 is connected with the drain electrode of the tube N1 and the grid electrode of the tube N2, and the drain electrode of the tube P1 is connected with the source electrode of the tube P2; the grid of the tube P2 is connected with the input signal A, and the drain of the tube P2 is connected with the source of the tube N1, the source of the tube N2, the grid of the tube N4, the grid of the tube N5, the grid of the tube P4 and the grid of the tube P5; the grid of the tube N1 and the drain of the tube N2 are both connected with an input signal A, the source of the tube P3 is connected with a power supply voltage VDD, the drain of the tube P3 is connected with the drain of the tube N3 and the source of the tube P4, the grid of the tube P3 is connected with the grid of the tube N3 and is connected with a carry input signal CIN, the source of the tube N3 is connected with a power supply ground signal VSS, the drain of the tube P4 is connected with the source of the tube N4, a node between the drain of the tube P4 and the source of the tube N4 is a summation output S, and the drain of the tube N4 is connected with the carry input signal CIN; the source electrode of the tube P5 is connected with a carry input signal CIN, the drain electrode of the tube P5 is connected with the source electrode of the tube N5, a node between the drain electrode of the tube P5 and the source electrode of the tube N5 is used for carrying output CO, and the drain electrode of the tube N5 is connected with an input signal A; the gate of the transistor P1, the drain of the transistor N1 and the gate of the transistor N2 are all connected to the input signal B.
2. The CMOS full adder according to claim 1, wherein said N1, N2, N3, N4 and N5 are NMOS transistors.
3. The CMOS full adder according to claim 1, wherein said P1, P2, P3, P4 and P5 are PMOS transistors.
4. The CMOS full adder according to claim 1, wherein the loop formed by the N1, N2, N5, P1, P2 and P5 is an operation unit of carry output CO of the CMOS full adder.
5. The CMOS full adder according to claim 1, wherein the loop formed by the N1, N2, N3, N4, P1, P2, P3 and P4 is an operation unit of the summation output S of the CMOS full adder.
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| CN202210602693.6A CN114710150B (en) | 2022-05-31 | 2022-05-31 | CMOS full adder |
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| CN202210602693.6A CN114710150B (en) | 2022-05-31 | 2022-05-31 | CMOS full adder |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355255A (en) * | 2011-07-15 | 2012-02-15 | 北京大学 | CMOS (complementary metal-oxide-semiconductor) full adder and method thereof |
| CN103078629A (en) * | 2012-12-27 | 2013-05-01 | 广州中大微电子有限公司 | Full-adder circuit based on 7 different or same transistors or units |
| CN110995246A (en) * | 2019-11-28 | 2020-04-10 | 重庆中易智芯科技有限责任公司 | Low-power-consumption full adder circuit with reset function |
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- 2022-05-31 CN CN202210602693.6A patent/CN114710150B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355255A (en) * | 2011-07-15 | 2012-02-15 | 北京大学 | CMOS (complementary metal-oxide-semiconductor) full adder and method thereof |
| CN103078629A (en) * | 2012-12-27 | 2013-05-01 | 广州中大微电子有限公司 | Full-adder circuit based on 7 different or same transistors or units |
| CN110995246A (en) * | 2019-11-28 | 2020-04-10 | 重庆中易智芯科技有限责任公司 | Low-power-consumption full adder circuit with reset function |
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