CN117275401B

CN117275401B - Image reduction circuit, LED display screen control card and image scaling method

Info

Publication number: CN117275401B
Application number: CN202311459502.6A
Authority: CN
Inventors: 刘秋翼; 廖志雄; 梁志钦; 丁光博; 杨贵川; 黄丽娟; 柳大智; 林铭杰; 潘江涛; 郭小川; 屈亚东
Original assignee: Zhongshan Zhiniu Electronic Co ltd
Current assignee: Zhongshan Zhiniu Electronic Co ltd
Priority date: 2023-11-03
Filing date: 2023-11-03
Publication date: 2024-02-27
Anticipated expiration: 2043-11-03
Also published as: CN117275401A

Abstract

The invention discloses an image reduction circuit, an LED display screen control card and an image scaling method, wherein a reduction logic circuit is designed based on four JK triggers, so that reduction of a monochromatic image or video can be conveniently realized by instantiating one or more circuit designs into the LED display screen control card and then matching with other logic image processing of the control card, the reduction of the monochromatic image or video can be realized by simply reducing the logic circuit, the occupied register resource is very little, no other logic devices are required to process the monochromatic image, unnecessary resource consumption can be effectively reduced, excessive resource consumption of the logic devices of the LED display screen is prevented, and the wide application of the LED display screen control card is facilitated.

Description

Image reduction circuit, LED display screen control card and image scaling method

Technical Field

The invention relates to the technical field of image scaling of an LED display screen, in particular to an image scaling circuit, an LED display screen control card and an image scaling method.

Background

An LED display (LED display) is a device for displaying various information such as text, images, video signals, etc., and is being increasingly used due to its characteristics of high brightness, long life, large viewing angle, etc.

The scaling operation in the LED display screen industry is all full-color, but the scaling operation is often accompanied by the problem of excessive resource consumption of logic devices, and the complex LED display screen can certainly cause resource waste when displaying monochromatic characters.

Disclosure of Invention

The invention overcomes the defects of the technology and provides an image reduction circuit, an LED display screen control card and an image scaling method.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

the first aspect of the embodiment of the invention discloses an image reduction circuit, which is a reduction logic circuit based on four JK triggers, wherein the reduction logic circuit is provided with a clock signal input end T1, a reset signal input end T2, a data input end T3, a data effective signal input end T4, a data effective signal output end T5 and a data output end T6, the reduction logic circuit is provided with the four JK triggers, the clock signal input end T1 is respectively connected with the clock input ends of the four JK triggers, and the reset signal input end T2 is respectively connected with the reset ends of the four JK triggers; the four JK triggers are respectively a first JK trigger U1, a second JK trigger U2, a third JK trigger U3 and a fourth JK trigger U4, and a logic processing circuit is arranged between the four JK triggers and the data effective signal output end T5 and the data output end T6;

When the sum of the pixel values of four pixels of the original image is greater than or equal to 2 and the four pixel value signals are all valid, namely, at least two signals input four times by the data input end T3 are high level, and all signals input four times by the data valid signal input end T4 are high level, outputting the high level to the data valid signal output end T5 and the high level to the data output end T6 through the logic processing circuit so as to realize the reduction of the image; on the contrary, when the sum of the pixel values of the four pixels of the original image is smaller than 2 and the four pixel value signals are all valid, that is, the signal input four times by the data input end T3 is only zero or is high level once, and the signal input four times by the data valid signal input end T4 is high level, the logic processing circuit outputs high level to the data valid signal output end T5 and outputs low level to the data output end T6.

As another alternative embodiment, the logic processing circuit is provided with a first logic circuit 1 for changing the signal output state of the first JK flip-flop U1, a second logic circuit 2 for changing the signal output state of the second JK flip-flop U2, a third logic circuit 3 for changing the signal output state of the third JK flip-flop U3, a fourth logic circuit 4 for changing the signal output state of the fourth JK flip-flop U4, a fifth logic circuit 5 for changing the signal output state of the data valid signal output terminal T5, and a sixth logic circuit 6 for changing the signal output state of the data output terminal T6;

The Q output end of the first JK trigger U1 is respectively connected with one input end of the fourth logic circuit 4, one input end of the second logic circuit 2 and one input end of the sixth logic circuit 6, and the Q non-output end of the first JK trigger U1 is respectively connected with one input end of the second logic circuit 2, one input end of the fifth logic circuit 5 and one input end of the sixth logic circuit 6; the Q output end of the second JK trigger U2 is respectively connected with one input end of the first logic circuit 1, one input end of the third logic circuit 3 and one input end of the fourth logic circuit 4, and the Q non-output end of the second JK trigger U2 is respectively connected with one input end of the first logic circuit 1, one input end of the third logic circuit 3, one input end of the fifth logic circuit 5 and one input end of the sixth logic circuit 6; the Q output end of the third JK trigger U3 is respectively connected with one input end of the first logic circuit 1, one input end of the second logic circuit 2, one input end of the fourth logic circuit 4, one input end of the fifth logic circuit 5 and one input end of the sixth logic circuit 6, and the Q non-output end of the third JK trigger U3 is respectively connected with one input end of the first logic circuit 1 and one input end of the second logic circuit 2; the Q output end of the fourth JK trigger U4 is respectively connected with one input end of the third logic circuit 3 and one input end of the sixth logic circuit 6, and the Q non-output end of the fourth JK trigger U4 is respectively connected with one input end of the first logic circuit 1, one input end of the second logic circuit 2, one input end of the third logic circuit 3 and one input end of the fifth logic circuit 5.

As another alternative embodiment, the first logic circuit 1 includes: the output end of the first logic sub-circuit 11 is connected with the J input end of the first JK trigger U1, and the output end of the second logic sub-circuit 12 is connected with the K input end of the first JK trigger U1;

the first logic sub-circuit 11 includes: the first three-input AND gate U11, the second three-input AND gate U12, the first two-input AND gate U13, the second two-input AND gate U14, the first two-input OR gate U15 and the first NOT gate U16, wherein a first input end of the first three-input AND gate U11 is connected with a Q non-output end of the second JK trigger U2, a second input end of the first three-input AND gate U11 is connected with a Q non-output end of the third JK trigger U3, and a third input end of the first three-input AND gate U is connected with a data valid signal input end T4; the first input end of the second three-input AND gate U12 is connected with the Q output end of the second JK trigger U2, the second input end is connected with the Q non-output end of the third JK trigger U3, and the third input end is connected with the Q non-output end of the fourth JK trigger U4; the first input end of the first two-input AND gate U13 is connected with the data input end T3 through a first NOT gate U16, and the second input end is connected with the data valid signal input end T4; a first input end of the second two-input AND gate U14 is connected with an output end of the second three-input AND gate U12, and a second input end of the second two-input AND gate U14 is connected with an output end of the first two-input AND gate U13; a first input end of the first two-input OR gate U15 is connected with an output end of the first three-input AND gate U11, a second input end of the first two-input OR gate U15 is connected with an output end of the second two-input AND gate U14, and an output end of the first two-input OR gate U15 is connected with a J input end of the first JK trigger U1;

The second logic sub-circuit 12 comprises: the first four-input AND gate U21, the second four-input AND gate U22, the second NOT gate U23 and the first two-input NOR gate U24, wherein the first input end of the first four-input AND gate U21 is connected with the Q output end of the second JK trigger U2, the second input end is connected with the Q non-output end of the third JK trigger U3, the third input end is connected with the Q non-output end of the fourth JK trigger U4, and the fourth input end is connected with the data input end T3; the first input end of the second four-input AND gate U22 is connected with the Q output end of the second JK trigger U2, the second input end is connected with the Q output end of the third JK trigger U3, the third input end is connected with the Q non-output end of the fourth JK trigger U4, and the fourth input end is connected with the data valid signal input end T4 through the second NOT gate U23; the first input end of the first two-input nor gate U24 is connected to the output end of the first four-input and gate U21, the second input end of the first two-input nor gate U24 is connected to the output end of the second four-input and gate U22, and the output end of the first two-input nor gate U is connected to the K input end of the first JK flip-flop U1.

As another alternative embodiment, the second logic circuit 2 includes: the output end of the third logic sub-circuit 21 is connected with the J input end of the second JK trigger U2, and the output end of the fourth logic sub-circuit 22 is connected with the K input end of the second JK trigger U2;

The third logic sub-circuit 21 comprises: the first input end of the third input AND gate U31 is connected with the Q non-output end of the third JK trigger U3, the second input end of the third input AND gate U32 is connected with the Q non-output end of the fourth JK trigger U4, and the third input end of the third input AND gate U31 is connected with the Q output end of the first JK trigger U1; the first input end of the third and fourth input AND gate U32 is connected with the Q non-output end of the third JK trigger U3, the second input end is connected with the Q non-output end of the fourth JK trigger U4, the third input end is connected with the data input end T3, and the fourth input end is connected with the data valid signal input end T4; the first input end of the second input or gate U33 is connected with the output end of the third input and gate U31, the second input end of the second input or gate U33 is connected with the output end of the third four input and gate U32, and the output end of the second input or gate U33 is connected with the J input end of the second JK trigger U2;

the fourth logic sub-circuit 22 comprises: the first input end of the fourth three-input AND gate U41 is connected with the Q non-output end of the fourth JK trigger U4, the second input end of the fourth three-input AND gate U41 is connected with the Q non-output end of the third JK trigger U3, and the third input end of the fourth three-input AND gate U42 is connected with the Q output end of the first JK trigger U1; the first input end of the fifth input AND gate U42 is connected with the Q non-output end of the fourth JK trigger U4, the second input end is connected with the Q output end of the third JK trigger U3, and the third input end is connected with the data valid signal input end T4 through the third NOT gate U44; the first input end of the sixth input AND gate U43 is connected with a data valid signal input end T4 through a third NOT gate U44, the second input end is connected with the Q non-output end of the fourth JK trigger U4, and the third input end is connected with the Q non-output end of the first JK trigger U1; the first input end of the first third input nor gate U45 is connected to the output end of the fourth third input and gate U41, the second input end is connected to the output end of the fifth third input and gate U42, the third input end is connected to the output end of the sixth third input and gate U43, and the output end is connected to the K input end of the second JK flip-flop U2.

As another alternative embodiment, the third logic circuit 3 includes: the output end of the fifth logic sub-circuit 31 is connected with the J input end of the third JK trigger U3, and the output end of the sixth logic sub-circuit 32 is connected with the K input end of the second JK trigger U2;

the fifth logic sub-circuit 31 includes: the first input end of the seventh three-input AND gate U51 is connected with the data input end T3, the second input end of the seventh three-input AND gate U51 is connected with the Q non-output end of the fourth JK trigger U4, and the third input end of the seventh three-input AND gate U52 is connected with the Q output end of the first JK trigger U1; the first input end of the eighth third input AND gate U52 is connected with the Q output end of the first JK trigger U1, the second input end is connected with the Q non-output end of the fourth JK trigger U4, and the third input end is connected with the Q output end of the second JK trigger U2; the first input end of the ninth input AND gate U53 is connected with the Q output end of the second JK trigger U2, the second input end is connected with the Q non-output end of the fourth JK trigger U4, and the third input end is connected with the data valid signal input end T4; the first input end of the first third input or gate U54 is connected with the output end of the seventh third input and gate U51, the second input end of the first third input or gate U54 is connected with the output end of the eighth third input and gate U52, the third input end of the first third input or gate U53, and the output end of the first third input or gate U54 is connected with the J input end of the third JK trigger U3;

The sixth logic sub-circuit 32 includes: the first input end of the third second input OR gate U61 is connected with the Q output end of the fourth JK trigger U4, the second input end of the third second input OR gate U61 is connected with the Q non-output end of the second JK trigger U2, and the output end of the third second input OR gate U61 is connected with the K input end of the third JK trigger U3.

As another alternative embodiment, the fourth logic circuit 4 includes: a seventh logic sub-circuit 41 connected to the J input terminal of the third JK flip-flop U3, and a power output terminal T7 connected to the K input terminal of the second JK flip-flop U2 for continuously outputting a high level;

the seventh logic sub-circuit 41 includes: the first input end of the fourth input AND gate U71 is connected with the Q output end of the first JK trigger U1, the second input end of the fourth input AND gate U71 is connected with the data valid signal input end T4, the third input end of the fourth input AND gate U72 is connected with the Q output end of the third JK trigger U3, and the fourth input end of the fourth input AND gate U73 is connected with the Q output end of the second JK trigger U2; the first input end of the fifth and gate U72 is connected with the data valid signal input end T4, the second input end is connected with the data input end T3, the third input end is connected with the Q output end of the second JK trigger U2, and the fourth input end is connected with the Q output end of the third JK trigger U3; the first input end of the fourth second input or gate U73 is connected to the output end of the fourth input and gate U71, the second input end is connected to the output end of the fifth and fourth input and gate U72, and the output end is connected to the J input end of the third JK flip-flop U3.

As another alternative embodiment, the fifth logic circuit 5 includes: the thirteenth input AND gate U81, the eleventh third input AND gate U82 and the fifth second input OR gate U83, wherein a first input end of the thirteenth input AND gate U81 is connected with a Q non-output end of the second JK trigger U2, a second input end of the thirteenth input AND gate U81 is connected with a Q output end of the third JK trigger U3, and a third input end of the thirteenth input AND gate U81 is connected with a Q non-output end of the fourth JK trigger U4; the first input end of the eleventh third input AND gate U82 is connected with the Q output end of the third JK trigger U3, the second input end is connected with the Q non-output end of the second JK trigger U2, and the third input end is connected with the Q non-output end of the first JK trigger U1; a first input end of the fifth second input or gate U83 is connected with an output end of the thirteenth input and gate U81, a second input end of the fifth second input or gate U83 is connected with an output end of the eleventh third input and gate U82, and an output end of the fifth second input or gate U83 is connected with a data valid signal output end T5;

the sixth logic circuit 6 includes: the first input end of the sixth fourth input AND gate U91 is connected with the Q non-output end of the first JK trigger U1, the second input end of the sixth fourth input AND gate U91 is connected with the Q non-output end of the second JK trigger U2, the third input end of the sixth fourth input AND gate U92 is connected with the Q output end of the third JK trigger U3, and the fourth input end of the sixth fourth input AND gate U93 is connected with the Q output end of the fourth JK trigger U4; the first input end of the seven-four input AND gate U92 is connected with the Q output end of the third JK trigger U3, the second input end is connected with the Q non-output end of the second JK trigger U2, the third input end is connected with the data input end T3, and the fourth input end is connected with the Q non-output end of the first JK trigger U1; a first input end of the sixth second input or gate U93 is connected to an output end of the sixth fourth input and gate U91, a second input end of the sixth second input or gate U93 is connected to an output end of the seventh fourth input and gate U92, and an output end of the sixth second input or gate U is connected to the data output end T6.

The second aspect of the embodiment of the invention discloses an LED display screen control card, which comprises:

a microcontroller circuit 100;

a synchronous dynamic random access memory 200;

a programmable logic device 300;

the synchronous dynamic random access memory 200 is externally connected to the programmable logic device 300;

the programmable logic device 300 includes:

an input buffer 301 for buffering input original image data after resolution is recognized;

a reduction processing module 302, configured to receive the raw image data read from the input buffer 301 and perform a reduction operation on the received raw image data according to a preset size template, so as to obtain reduced image data and store the reduced image data in the synchronous dynamic random access memory 200;

an SDRAM control module 302, configured to control writing of the original image data buffered in the input buffer 301 into the synchronous dynamic random access memory 200;

an output buffer 303, configured to receive and buffer the image data read from the synchronous dynamic random access memory 200 under the control of the SDRAM control module 302 for output;

the image reduction circuit according to any one of claims 1 to 7 is provided on the reduction processing module 302 to perform reduction processing on a monochrome image.

The third invention of the embodiment of the invention discloses an image zooming method which is applied to the LED display screen control card, wherein the control card is provided with the image shrinking circuit, and the image zooming method comprises the following steps:

reading data of an original image, inputting an image displayed as a single color in the original image into the reduction logic circuit for reduction processing, and inputting an image displayed as a non-single color into the programmable logic device for reduction processing;

taking the image displayed as a single color as a target image, acquiring four points corresponding to the target image and inputting pixel data of the four points to a reduction logic circuit;

the reduction logic circuit outputs the pixel data of four points into the pixel data of one point after reduction processing, namely, the pixel data is output into image effective data of one single bit and effective pulse for proving that the image effective data is effective, so as to realize the scaling of the target image.

As another alternative embodiment, the acquiring the four points in the target image corresponding to the image and inputting the data of the four points to the reduction logic circuit includes:

firstly, acquiring pixel data of two adjacent points of the previous row, and inputting the pixel data into a shrinking logic circuit;

and acquiring pixel data of two adjacent points of the next row, and inputting the pixel data into the shrinking logic circuit.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

1. in the embodiment of the invention, the image reduction circuit takes bilinear interpolation as a principle and designs a reduction logic circuit based on four JK triggers, so that the reduction of a monochromatic image or video can be realized by instantiating one or more circuit designs into the LED display screen control card and then matching with other logic image processing of the control card, the simple reduction of the monochromatic image or video can be realized only by the reduction logic circuit, the occupied register resource is very little, no other logic devices are required to process the monochromatic image, the unnecessary resource consumption can be effectively reduced, the excessive resource consumption of the logic devices of the LED display screen is prevented, and the wide application of the LED display screen control card is facilitated.

2. The invention is connected with different JK triggers through different logic circuits, so as to flexibly control the output states of the different JK triggers, and is beneficial to carrying out accurate reduction processing on the target image. Meanwhile, the different logic circuits are clear in division of work, different logic functions can be realized, and the method is suitable for different application scenes.

3. The embodiment of the invention is convenient to reduce the consumption of unnecessary logic devices by applying the reduction processing module and the image reduction circuit thereof into the LED display screen control card.

4. The embodiment of the invention can separate the monochromatic image and the non-monochromatic image for reduction processing, and apply the monochromatic image into the reduction logic circuit for processing, thereby being capable of effectively reducing unnecessary resource consumption while meeting the reduction function.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an overall image reduction circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a partial structure of a first embodiment including four JK flip-flops and input/output terminals;

FIG. 3 is a schematic diagram of a first logic circuit;

FIG. 4 is a schematic diagram of a second logic circuit;

FIG. 5 is a schematic diagram of a third logic circuit;

FIG. 6 is a schematic diagram of a fourth logic circuit;

FIG. 7 is a schematic diagram of a fifth logic circuit;

FIG. 8 is a schematic diagram of a sixth logic circuit;

fig. 9 is a schematic structural diagram of a second embodiment of the present invention.

Fig. 10 is a schematic structural diagram of a programmable logic device according to a second embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that the terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present invention are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the invention discloses a dotting method of an LED display screen, which can simplify the construction process of identification and improve the identification efficiency, and is favorable for accurately adjusting the identification method in the later period.

Example 1

Referring to fig. 1-8, fig. 1 is a schematic circuit diagram of an image reduction circuit according to an embodiment of the invention. As shown in fig. 1 to 8, the image reduction circuit is a reduction logic circuit based on four JK flip-flops, the reduction logic circuit is provided with a clock signal input end T1, a reset signal input end T2, a data input end T3, a data valid signal input end T4, a data valid signal output end T5 and a data output end T6, the reduction logic circuit is provided with four JK flip-flops, the clock signal input end T1 is respectively connected with the clock input ends of the four JK flip-flops, and the reset signal input end T2 is respectively connected with the reset ends of the four JK flip-flops; the four JK triggers are respectively a first JK trigger U1, a second JK trigger U2, a third JK trigger U3 and a fourth JK trigger U4, and a logic processing circuit is arranged between the four JK triggers and the data effective signal output end T5 and the data output end T6;

when the sum of the pixel values of four pixels of the original image is greater than or equal to 2 and the four pixel value signals are all valid, namely, at least two signals input four times by the data input end T3 are high level, and the four signals input four times by the data valid signal input end T4 are high level, outputting a pixel valid pulse and a pixel value which is high level by the logic processing circuit, namely, outputting high level to the data valid signal output end T5 and outputting high level to the data output end T6 by the logic processing circuit so as to realize image shrinkage; on the contrary, when the sum of the pixel values of the four pixels of the original image is smaller than 2 and the four pixel value signals are valid, that is, the signal input by the data input terminal T3 four times is only zero or is high level once, and the signal input by the data valid signal input terminal T4 four times is high level, one pixel valid pulse and one pixel value which is low level are output through the logic processing circuit, that is, the logic processing circuit outputs high level to the data valid signal output terminal T5 and outputs low level to the data output terminal T6.

In the implementation, the values of the four JK triggers in the initial state are all 0, namely the Q output ends of the four JK triggers in the initial state are all 0, and 0000 represents the initial state; the initial state represents a state when the original image is not input or a state when the original image is input. The pixel data of four points of the target image are divided into four shots and sequentially input to the image reduction circuit of the present invention, and the reduction of the image is performed. As for the first example below, when all four points of the target image are displayed in black, the pixel value signals of the pixel data of the four points are all low, the pixel value signal of each beat is represented by the numeral "0", and thus the content of the four beats to be input can be represented by "0000". Conversely, if the pixel value signals of the pixel data of the four points are all high, the pixel value signal entered for each beat is represented by the numeral "1".

Example one: when the first beat of incoming pixel value signals are valid and the incoming pixel value signals are low in the 0000 state, the four JK triggers are updated to be in a 0001 state, namely the Q output ends of the first JK trigger U1 are all 0, the Q output ends of the second JK trigger U2 are all 0, the Q output ends of the third JK trigger U3 are all 0, and the Q output ends of the fourth JK trigger U4 are all 1; the state is updated to 0010 when the second incoming pixel value signal is valid and the pixel value signal is still low and valid; the state update is 0101 when the pixel value signal is valid and the pixel value signal is low for the next third beat; then, the state is updated to 0000 when the incoming pixel value signal of the fourth beat is still low, and pixel data of one point is output at the same time, namely, a pixel value of low level can be represented by 0 and a pixel effective pulse can be represented by 1, so that the reduction of a certain target image is realized. The remaining target image is then scaled down, the image scaling circuit again encounters the incoming valid pulse, and the four JK flip-flops are updated to the 0001 or 0011 state, and the registers are updated to the 0010 or 0110 or 0111 state at the next clock cycle. Then the next clock cycle pulls up the output valid pin by one clock cycle and outputs the value of the interpolation point, and the value of the register is updated to 0000 to wait for four points of the next target image to be operated, so that the reduction processing is continuously performed until all the monochrome target images are completed. The four points are four points in the source image to be selected as reference points when the image is reduced, and the four points are used for calculating the size and the position of the reduced image.

In this way, it can be understood that when the input four shots of the target image have contents of 0000,0001,0010,0100,1000, the pixel value of the above four shots is 2 or less, and the output is 0 through the image reduction circuit, so that the scaled image is displayed as black. When the input four-shot content of the target image is 1111, 1110,1101,1011,0111,1100,1010,1001, 0011, 0101, 0110, the pixel value of the above four shots is 2 or more, and the output is 1 through the image reduction circuit, so that the scaled image is displayed as white.

As described above, the image reduction circuit of the invention uses bilinear interpolation as a principle and designs a reduction logic circuit based on four JK triggers, so that the reduction of a monochromatic image or video can be realized by instantiating one or more circuit designs into an LED display screen control card and then matching with other logic image processing of the control card, the reduction of the monochromatic image or video can be realized simply by reducing the logic circuit, the occupied register resources are very little, no other logic devices are required to process the monochromatic image, the unnecessary resource consumption can be effectively reduced, the excessive resource consumption of the logic devices of the LED display screen is prevented, and the wide application of the LED display screen control card is facilitated.

As shown in fig. 1, in the implementation, the logic processing circuit is provided with a first logic circuit 1 for changing the signal output state of a first JK trigger U1, a second logic circuit 2 for changing the signal output state of a second JK trigger U2, a third logic circuit 3 for changing the signal output state of a third JK trigger U3, a fourth logic circuit 4 for changing the signal output state of a fourth JK trigger U4, a fifth logic circuit 5 for changing the signal output state of a data valid signal output terminal T5, and a sixth logic circuit 6 for changing the signal output state of a data output terminal T6; the Q output end of the first JK trigger U1 is respectively connected with one input end of the fourth logic circuit 4, one input end of the second logic circuit 2 and one input end of the sixth logic circuit 6, and the Q non-output end of the first JK trigger U1 is respectively connected with one input end of the second logic circuit 2, one input end of the fifth logic circuit 5 and one input end of the sixth logic circuit 6; the Q output end of the second JK trigger U2 is respectively connected with one input end of the first logic circuit 1, one input end of the third logic circuit 3 and one input end of the fourth logic circuit 4, and the Q non-output end of the second JK trigger U2 is respectively connected with one input end of the first logic circuit 1, one input end of the third logic circuit 3, one input end of the fifth logic circuit 5 and one input end of the sixth logic circuit 6; the Q output end of the third JK trigger U3 is respectively connected with one input end of the first logic circuit 1, one input end of the second logic circuit 2, one input end of the fourth logic circuit 4, one input end of the fifth logic circuit 5 and one input end of the sixth logic circuit 6, and the Q non-output end of the third JK trigger U3 is respectively connected with one input end of the first logic circuit 1 and one input end of the second logic circuit 2; the Q output end of the fourth JK trigger U4 is respectively connected with one input end of the third logic circuit 3 and one input end of the sixth logic circuit 6, and the Q non-output end of the fourth JK trigger U4 is respectively connected with one input end of the first logic circuit 1, one input end of the second logic circuit 2, one input end of the third logic circuit 3 and one input end of the fifth logic circuit 5.

As described above, different logic circuits are connected with different JK triggers, so that the output states of the different JK triggers can be flexibly controlled, and accurate reduction processing of a target image is facilitated. Meanwhile, the different logic circuits are clear in division of work, different logic functions can be realized, and the method is suitable for different application scenes.

As shown in fig. 3, in the implementation, the first logic circuit 1 includes: the output end of the first logic sub-circuit 11 is connected with the J input end of the first JK trigger U1, and the output end of the second logic sub-circuit 12 is connected with the K input end of the first JK trigger U1;

As shown in fig. 4, in the implementation, the second logic circuit 2 includes: the output end of the third logic sub-circuit 21 is connected with the J input end of the second JK trigger U2, and the output end of the fourth logic sub-circuit 22 is connected with the K input end of the second JK trigger U2;

As shown in fig. 5, in the implementation, the third logic circuit 3 includes: the output end of the fifth logic sub-circuit 31 is connected with the J input end of the third JK trigger U3, and the output end of the sixth logic sub-circuit 32 is connected with the K input end of the second JK trigger U2;

As shown in fig. 6, in the implementation, the fourth logic circuit 4 includes: a seventh logic sub-circuit 41 connected to the J input terminal of the third JK flip-flop U3, and a power output terminal T7 connected to the K input terminal of the second JK flip-flop U2 for continuously outputting a high level;

As shown in fig. 7, in the implementation, the fifth logic circuit 5 includes: the thirteenth input AND gate U81, the eleventh third input AND gate U82 and the fifth second input OR gate U83, wherein a first input end of the thirteenth input AND gate U81 is connected with a Q non-output end of the second JK trigger U2, a second input end of the thirteenth input AND gate U81 is connected with a Q output end of the third JK trigger U3, and a third input end of the thirteenth input AND gate U81 is connected with a Q non-output end of the fourth JK trigger U4; the first input end of the eleventh third input AND gate U82 is connected with the Q output end of the third JK trigger U3, the second input end is connected with the Q non-output end of the second JK trigger U2, and the third input end is connected with the Q non-output end of the first JK trigger U1; a first input end of the fifth second input or gate U83 is connected with an output end of the thirteenth input and gate U81, a second input end of the fifth second input or gate U83 is connected with an output end of the eleventh third input and gate U82, and an output end of the fifth second input or gate U83 is connected with a data valid signal output end T5;

as shown in fig. 8, in the implementation, the sixth logic circuit 6 includes: the first input end of the sixth fourth input AND gate U91 is connected with the Q non-output end of the first JK trigger U1, the second input end of the sixth fourth input AND gate U91 is connected with the Q non-output end of the second JK trigger U2, the third input end of the sixth fourth input AND gate U92 is connected with the Q output end of the third JK trigger U3, and the fourth input end of the sixth fourth input AND gate U93 is connected with the Q output end of the fourth JK trigger U4; the first input end of the seven-four input AND gate U92 is connected with the Q output end of the third JK trigger U3, the second input end is connected with the Q non-output end of the second JK trigger U2, the third input end is connected with the data input end T3, and the fourth input end is connected with the Q non-output end of the first JK trigger U1; a first input end of the sixth second input or gate U93 is connected to an output end of the sixth fourth input and gate U91, a second input end of the sixth second input or gate U93 is connected to an output end of the seventh fourth input and gate U92, and an output end of the sixth second input or gate U is connected to the data output end T6.

Where an effective pulse in an image generally refers to a pulse that is effective in removing impulse noise from the image without excessive loss of the image.

Example two

As shown in fig. 9 and 10, an LED display screen control card includes:

a microcontroller circuit 100; the microcontroller circuit 100 may be a single-chip microcomputer.

A synchronous dynamic random access memory 200;

a programmable logic device 300;

the programmable logic device 300 includes:

The reduction processing module 302 is provided with the image reduction circuit according to the first embodiment, so as to perform reduction processing on the monochrome image.

In specific implementation, the video signal output by the PC is processed by the external video receiving and processing module before entering the programmable logic device 300.

As described above, by applying the reduction processing module 302 and the image reduction circuit thereof into the LED display screen control card, unnecessary consumption of logic devices is reduced.

Example III

An image scaling method is applied to the LED display screen control card of the second embodiment, the control card is provided with the image reduction circuit of the first embodiment, and the image scaling method includes:

reading data of an original image, inputting an image displayed as a single color in the original image into the reduction logic circuit for reduction processing, and inputting an image displayed as a non-single color into the programmable logic device for reduction processing; taking the image displayed as a single color as a target image, acquiring four points corresponding to the target image and inputting pixel data of the four points to a reduction logic circuit;

As described above, by the above scaling method, the monochrome image and the non-monochrome image can be separately subjected to the reduction processing, and the monochrome image is applied to the reduction logic circuit to be processed, so that the unnecessary resource consumption can be effectively reduced while the reduction function is satisfied.

As a preferred embodiment, the acquiring the four points in the target image corresponding to the image and inputting the data of the four points to the reduction logic circuit includes:

In particular, as shown, the data valid signal input terminal T4 is replaced with the row valid col_vld. The reduction from the original four random dinvld to two random col vld, col vld pulled one beat high indicates that the current beat and the subsequent beat of data are valid.

As described above, since the pixel data of the same line of the target image is adjacent, but is random when waiting for the next line of data, the pixel data of the two adjacent points of the previous line can be acquired together first, then the pixel data of the two adjacent points of the next line can be acquired without the need of acquiring each point by point, the acquisition steps are simpler, frequent memory access and data transmission during image processing are avoided, so that the processing efficiency is improved, and unnecessary calculation and storage consumption can be further avoided.

The image reduction circuit, the LED display screen control card and the image scaling method disclosed by the embodiment of the invention are described in detail, and specific examples are applied to the principle and implementation of the invention, and the description of the above embodiments is only used for helping to understand the method and core ideas of the invention; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the idea of the present invention, the present disclosure should not be construed as limiting the present invention in summary.

Claims

1. The image reduction circuit is characterized by being a reduction logic circuit based on four JK triggers, wherein the reduction logic circuit is provided with a clock signal input end (T1), a reset signal input end (T2), a data input end (T3), a data effective signal input end (T4), a data effective signal output end (T5) and a data output end (T6), the reduction logic circuit is provided with four JK triggers, the clock signal input end (T1) is respectively connected with the clock input ends of the four JK triggers, and the reset signal input end (T2) is respectively connected with the reset ends of the four JK triggers; the four JK triggers are respectively a first JK trigger (U1), a second JK trigger (U2), a third JK trigger (U3) and a fourth JK trigger (U4), and a logic processing circuit is arranged between the four JK triggers and a data effective signal output end (T5) and a data output end (T6);

When the sum of pixel values of four pixels of the original image is more than or equal to 2 and the four pixel value signals are all valid, namely, at least two signals input four times by the data input end (T3) are high level, and the signals input four times by the data valid signal input end (T4) are high level, outputting the high level to the data valid signal output end (T5) and the high level to the data output end (T6) through the logic processing circuit so as to realize the reduction of the image; on the contrary, when the sum of the pixel values of the four pixels of the original image is smaller than 2 and the four pixel value signals are all valid, namely, the signal input by the data input end (T3) is zero or high once, the signal input by the data valid signal input end (T4) is high once, the logic processing circuit outputs high level to the data valid signal output end (T5) and low level to the data output end (T6);

the logic processing circuit is provided with a first logic circuit (1) for changing the signal output state of a first JK trigger (U1), a second logic circuit (2) for changing the signal output state of a second JK trigger (U2), a third logic circuit (3) for changing the signal output state of a third JK trigger (U3), a fourth logic circuit (4) for changing the signal output state of a fourth JK trigger (U4), a fifth logic circuit (5) for changing the signal output state of a data effective signal output end (T5) and a sixth logic circuit (6) for changing the signal output state of a data output end (T6);

The Q output end of the first JK trigger (U1) is respectively connected with one input end of the fourth logic circuit (4), one input end of the second logic circuit (2) and one input end of the sixth logic circuit (6), and the Q non-output end of the first JK trigger (U1) is respectively connected with one input end of the second logic circuit (2), one input end of the fifth logic circuit (5) and one input end of the sixth logic circuit (6); the Q output end of the second JK trigger (U2) is respectively connected with one input end of the first logic circuit (1), one input end of the third logic circuit (3) and one input end of the fourth logic circuit (4), and the Q non-output end of the second JK trigger (U2) is respectively connected with one input end of the first logic circuit (1), one input end of the third logic circuit (3), one input end of the fifth logic circuit (5) and one input end of the sixth logic circuit (6); the Q output end of the third JK trigger (U3) is respectively connected with one input end of the first logic circuit (1), one input end of the second logic circuit (2), one input end of the fourth logic circuit (4), one input end of the fifth logic circuit (5) and one input end of the sixth logic circuit (6), and the Q non-output end of the third JK trigger (U3) is respectively connected with one input end of the first logic circuit (1) and one input end of the second logic circuit (2); the Q output end of the fourth JK trigger (U4) is respectively connected with one input end of the third logic circuit (3) and one input end of the sixth logic circuit (6), and the Q non-output end of the fourth JK trigger (U4) is respectively connected with one input end of the first logic circuit (1), one input end of the second logic circuit (2), one input end of the third logic circuit (3) and one input end of the fifth logic circuit (5).

2. The image reduction circuit according to claim 1, wherein the first logic circuit (1) includes: the output end of the first logic sub-circuit (11) is connected with the J input end of the first JK trigger (U1), and the output end of the second logic sub-circuit (12) is connected with the K input end of the first JK trigger (U1);

the first logic sub-circuit (11) comprises: the first input end of the first three-input AND gate (U11), the second three-input AND gate (U12), the first two-input AND gate (U13), the second two-input AND gate (U14), the first two-input OR gate (U15) and the first NOT gate (U16), the first input end of the first three-input AND gate (U11) is connected with the Q non-output end of the second JK trigger (U2), the second input end is connected with the Q non-output end of the third JK trigger (U3), and the third input end is connected with the data valid signal input end (T4); the first input end of the second three-input AND gate (U12) is connected with the Q output end of the second JK trigger (U2), the second input end is connected with the Q non-output end of the third JK trigger (U3), and the third input end is connected with the Q non-output end of the fourth JK trigger (U4); the first input end of the first two-input AND gate (U13) is connected with the data input end (T3) through the first NOT gate (U16), and the second input end is connected with the data valid signal input end (T4); the first input end of the second two-input AND gate (U14) is connected with the output end of the second three-input AND gate (U12), and the second input end of the second two-input AND gate (U13); a first input end of the first two-input OR gate (U15) is connected with an output end of the first three-input AND gate (U11), a second input end of the first two-input OR gate is connected with an output end of the second two-input AND gate (U14), and an output end of the first two-input OR gate is connected with a J input end of the first JK trigger (U1);

The second logic sub-circuit (12) comprises: the first input end of the first four-input AND gate (U21), the second four-input AND gate (U22), the second NOT gate (U23) and the first two-input NOR gate (U24) are connected with the Q output end of the second JK trigger (U2), the second input end of the first four-input AND gate (U21) is connected with the Q non-output end of the third JK trigger (U3), the third input end of the first four-input AND gate is connected with the Q non-output end of the fourth JK trigger (U4), and the fourth input end of the first four-input AND gate is connected with the data input end (T3); the first input end of the second four-input AND gate (U22) is connected with the Q output end of the second JK trigger (U2), the second input end is connected with the Q output end of the third JK trigger (U3), the third input end is connected with the Q non-output end of the fourth JK trigger (U4), and the fourth input end is connected with the data valid signal input end (T4) through the second NOT gate (U23); the first input end of the first two-input NOR gate (U24) is connected with the output end of the first four-input AND gate (U21), the second input end of the first two-input NOR gate is connected with the output end of the second four-input AND gate (U22), and the output end of the first two-input NOR gate is connected with the K input end of the first JK trigger (U1).

3. The image reduction circuit according to claim 1, wherein the second logic circuit (2) includes: the output end of the third logic sub-circuit (21) is connected with the J input end of the second JK trigger (U2), and the output end of the fourth logic sub-circuit (22) is connected with the K input end of the second JK trigger (U2);

The third logic sub-circuit (21) comprises: the first input end of the third input AND gate (U31) is connected with the Q non-output end of the third JK trigger (U3), the second input end of the third input AND gate is connected with the Q non-output end of the fourth JK trigger (U4), and the third input end of the third input AND gate is connected with the Q output end of the first JK trigger (U1); the first input end of the third and fourth input AND gate (U32) is connected with the Q non-output end of the third JK trigger (U3), the second input end is connected with the Q non-output end of the fourth JK trigger (U4), the third input end is connected with the data input end (T3), and the fourth input end is connected with the data valid signal input end (T4); the first input end of the second input OR gate (U33) is connected with the output end of the third input AND gate (U31), the second input end of the second input OR gate is connected with the output end of the third four input AND gate (U32), and the output end of the second input OR gate is connected with the J input end of the second JK trigger (U2);

the fourth logic sub-circuit (22) comprises: the first input end of the fourth three-input AND gate (U41) is connected with the Q non-output end of the fourth JK trigger (U4), the second input end of the fourth three-input AND gate is connected with the Q non-output end of the third JK trigger (U3), and the third input end of the fourth three-input AND gate is connected with the Q output end of the first JK trigger (U1); the first input end of the fifth input AND gate (U42) is connected with the Q non-output end of the fourth JK trigger (U4), the second input end of the fifth input AND gate is connected with the Q output end of the third JK trigger (U3), and the third input end of the fifth input AND gate is connected with the data effective signal input end (T4) through a third NOT gate (U44); the first input end of the sixth three-input AND gate (U43) is connected with the data valid signal input end (T4) through a third NOT gate (U44), the second input end is connected with the Q NOT end of the fourth JK trigger (U4), and the third input end is connected with the Q NOT end of the first JK trigger (U1); the first input end of the first third input NOR gate (U45) is connected with the output end of the fourth third input AND gate (U41), the second input end of the first third input NOR gate is connected with the output end of the fifth third input AND gate (U42), the third input end of the first third input NOR gate is connected with the output end of the sixth third input AND gate (U43), and the output end of the first third input NOR gate is connected with the K input end of the second JK trigger (U2).

4. The image reduction circuit according to claim 1, wherein the third logic circuit (3) includes: the output end of the fifth logic sub-circuit (31) is connected with the J input end of the third JK trigger (U3), and the output end of the sixth logic sub-circuit (32) is connected with the K input end of the second JK trigger (U2);

the fifth logic sub-circuit (31) comprises: a seventh three-input AND gate (U51), an eighth three-input AND gate (U52), a ninth three-input AND gate (U53) and a first three-input OR gate (U54), wherein a first input end of the seventh three-input AND gate (U51) is connected with a data input end (T3), a second input end of the seventh three-input AND gate is connected with a Q non-output end of a fourth JK trigger (U4), and a third input end of the seventh three-input AND gate is connected with a Q output end of the first JK trigger (U1); the first input end of the eighth third input AND gate (U52) is connected with the Q output end of the first JK trigger (U1), the second input end is connected with the Q non-output end of the fourth JK trigger (U4), and the third input end is connected with the Q output end of the second JK trigger (U2); a first input end of the ninth third input AND gate (U53) is connected with a Q output end of the second JK trigger (U2), a second input end of the ninth third input AND gate is connected with a Q non-output end of the fourth JK trigger (U4), and a third input end of the ninth third input AND gate is connected with a data valid signal input end (T4); the first input end of the first third input OR gate (U54) is connected with the output end of the seventh third input AND gate (U51), the second input end of the first third input OR gate is connected with the output end of the eighth third input AND gate (U52), the third input end of the first third input OR gate is connected with the output end of the ninth third input AND gate (U53), and the output end of the first third input OR gate is connected with the J input end of the third JK trigger (U3);

The sixth logic sub-circuit (32) includes: the first input end of the third second input OR gate (U61) is connected with the Q output end of the fourth JK trigger (U4), the second input end of the third second input OR gate (U61) is connected with the Q non-output end of the second JK trigger (U2), and the output end of the third second input OR gate (U61) is connected with the K input end of the third JK trigger (U3).

5. The image reduction circuit according to claim 1, wherein the fourth logic circuit (4) includes: a seventh logic sub-circuit (41) connected to the J input terminal of the third JK flip-flop (U3), and a power output terminal (T7) connected to the K input terminal of the second JK flip-flop (U2) for continuously outputting a high level;

the seventh logic sub-circuit (41) comprises: the first input end of the fourth input AND gate (U71) is connected with the Q output end of the first JK trigger (U1), the second input end of the fourth input AND gate is connected with the data valid signal input end (T4), the third input end of the fourth input AND gate is connected with the Q output end of the third JK trigger (U3), and the fourth input end of the fourth input AND gate is connected with the Q output end of the second JK trigger (U2); the first input end of the fifth input AND gate (U72) is connected with a data effective signal input end (T4), the second input end is connected with a data input end (T3), the third input end is connected with the Q output end of the second JK trigger (U2), and the fourth input end is connected with the Q output end of the third JK trigger (U3); the first input end of the fourth second input OR gate (U73) is connected with the output end of the fourth input AND gate (U71), the second input end of the fourth second input OR gate is connected with the output end of the fifth input AND gate (U72), and the output end of the fourth second input OR gate is connected with the J input end of the third JK trigger (U3).

6. The image reduction circuit according to claim 1, wherein the fifth logic circuit (5) includes: a thirteenth input AND gate (U81), an eleventh third input AND gate (U82) and a fifth second input OR gate (U83), wherein a first input end of the thirteenth input AND gate (U81) is connected with a Q non-output end of the second JK trigger (U2), a second input end of the thirteenth input AND gate is connected with a Q output end of the third JK trigger (U3), and a third input end of the thirteenth input AND gate is connected with a Q non-output end of the fourth JK trigger (U4); the first input end of the eleventh third input AND gate (U82) is connected with the Q output end of the third JK trigger (U3), the second input end of the eleventh third input AND gate is connected with the Q non-output end of the second JK trigger (U2), and the third input end of the eleventh third input AND gate is connected with the Q non-output end of the first JK trigger (U1); a first input end of the fifth second input OR gate (U83) is connected with an output end of the thirteenth input AND gate (U81), a second input end of the fifth second input OR gate is connected with an output end of the eleventh input AND gate (U82), and an output end of the fifth second input OR gate is connected with a data valid signal output end (T5);

the sixth logic circuit (6) includes: a sixth four-input AND gate (U91), a seventh four-input AND gate (U92) and a sixth two-input OR gate (U93), wherein a first input end of the sixth four-input AND gate (U91) is connected with a Q non-output end of a first JK trigger (U1), a second input end of the sixth four-input AND gate is connected with a Q non-output end of a second JK trigger (U2), a third input end of the sixth four-input AND gate is connected with a Q output end of a third JK trigger (U3), and a fourth input end of the sixth four-input AND gate is connected with a Q output end of a fourth JK trigger (U4); the first input end of the seven-four input AND gate (U92) is connected with the Q output end of the third JK trigger (U3), the second input end is connected with the Q non-output end of the second JK trigger (U2), the third input end is connected with the data input end (T3), and the fourth input end is connected with the Q non-output end of the first JK trigger (U1); the first input end of the sixth second input OR gate (U93) is connected with the output end of the sixth fourth input AND gate (U91), the second input end of the sixth second input OR gate is connected with the output end of the seventh fourth input AND gate (U92), and the output end of the sixth second input OR gate is connected with the data output end (T6).

7. An LED display screen control card, comprising:

a microcontroller circuit (100);

a synchronous dynamic random access memory (200);

a programmable logic device (300);

the synchronous dynamic random access memory (200) is externally connected with the programmable logic device (300);

the programmable logic device (300) includes:

a reduction processing module (302) for receiving the original image data read from the input buffer (301) and performing a reduction operation on the received original image data according to a preset size template to obtain reduced image data and storing the reduced image data in the synchronous dynamic random access memory (200);

an SDRAM control module (302) for controlling writing of the original image data buffered to the input buffer (301) into the synchronous dynamic random access memory (200);

an output buffer (303) for receiving and buffering the image data read from the synchronous dynamic random access memory (200) for output under the control of the SDRAM control module (302);

Wherein the reduction processing module (302) is provided with the image reduction circuit as claimed in any one of claims 1 to 6 for performing reduction processing on a monochrome image.

8. An image scaling method, applied to the LED display screen control card of claim 7, the control card being provided with the image reduction circuit of any one of claims 1 to 6, the image scaling method comprising:

9. The image scaling method of claim 8, wherein the acquiring four points in the target image and inputting the data of the four points to the reduction logic circuit comprises: