CN109687848A - A kind of reversible trigger and its configuration method that logic function is configurable - Google Patents
A kind of reversible trigger and its configuration method that logic function is configurable Download PDFInfo
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- CN109687848A CN109687848A CN201811432160.8A CN201811432160A CN109687848A CN 109687848 A CN109687848 A CN 109687848A CN 201811432160 A CN201811432160 A CN 201811432160A CN 109687848 A CN109687848 A CN 109687848A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
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Abstract
The reversible trigger and its configuration method that can configure the invention discloses a kind of logic function, the reversible trigger includes the 7 Toffoli reversible logic gates and 4 Fredkin reversible logic gates for there was only 1 target position, by 45 Toffoli reversible logic gates logic function configuration circuits in series, subject clock signal controls and is made of edge sampling and storage circuit 22 Toffoli reversible logic gates and 2 Fredkin reversible logic gates, by it is asynchronous set number control signals control and be made of another 2 Fredkin reversible logic gates asynchronous set several circuits, logical inversion circuit is constituted by 12 Toffoli reversible logic gate of residue；4 control bit lines are set in logic function configuration circuit, by the way that every control bit line is configured to the state of being turned on or off with the connection status that 45 Toffoli reversible logic gates respectively correspond to control bit, the reversible trigger may make to be respectively provided with the logic function of d type flip flop, T trigger and JK flip-flop.
Description
Technical field
The present invention relates to a kind of Digital Logical Circuits, more particularly, to it is a kind of using Toffoli reversible logic gate and
The logic function that Fredkin reversible logic gate is constituted configurable reversible trigger and its configuration method, so that this can de-activated
Device can be configured to reversible d type flip flop, reversible T trigger or reversible JK flip-flop.
Background technique
How to reduce circuit power consumption is an emphasis in current IC design.Studies have shown that irreversible operation
The loss of each information bit can generate KT × ln2 joules of heat, wherein K is Boltzmann's constant, and T is absolute temperature.
The irreversible of the logical operation process of traditional digital circuit is the main reason for causing power consumption；And in reversible logic circuits,
Logic gate due to constituting reversible logic circuits is all reversible, ideally reversible logic circuits will not be because of letter
It ceases the loss of position and generates the loss of heat, the power consumption of reversible logic circuits is very low.In addition, in the application of quantum calculation field,
Quantum reversible logic circuits are the basic units for constructing quantum computer.Therefore, reversible logic circuits designing technique application prospect
It is wide.
Digital Logical Circuits has two class of combinational logic circuit and sequential logical circuit, wherein trigger is to constitute timing to patrol
Collect a basic device of circuit.Generally according to the logic function of trigger, trigger can be divided into rest-set flip-flop, d type flip flop,
T trigger and JK flip-flop.In the past in flip-flop design, the circuit structure of each trigger is different from.In order to realize
Conversion between different triggers needs additional additional logic gate, and not can convert between any two classes trigger, such as JK
Trigger can be converted d type flip flop, but d type flip flop cannot be converted into JK flip-flop.In addition, being designed in contemporary integrated circuits
In, Programmable Analog Circuits have become a main circuit realization means, support the key factor of Programmable Analog Circuits
First is that the logic function of circuit can configure, i.e., the inside connection of one circuit can configure, and pass through and change circuit
Different logic functions is realized in inside connection.Therefore, a kind of reversible trigger is studied, the inside by changing reversible trigger connects
Connect so that reversible trigger have variety classes trigger logic function, be very it is necessary to.
Summary of the invention
The reversible trigger that can configure technical problem to be solved by the invention is to provide a kind of logic function and its configuration
Method can be configured to reversible d type flip flop, reversible T trigger or can by changing the inside connection of reversed flip-flop circuit
Inverse JK flip-flop.
The technical scheme of the invention to solve the technical problem is: a kind of logic function it is configurable can de-activated
Device, it is characterised in that the reversible trigger it is asynchronous set number control signals be M, clock signal CLK, the first data input signal
For I1, the second data input signal be I2, to preset number be A, the state of the reversible trigger is Q, the benefit of state isM、
CLK、I1And I2, A, Q andBit wide be 1, M be described as " M is effective " when being logical one i.e. and allow it is asynchronous set number, M is patrols
It is described as " M is invalid " i.e. when volume " 0 " and does not allow asynchronous to set number；The reversible trigger includes 7 and there was only 1 target position
Toffoli reversible logic gate and 4 Fredkin reversible logic gates；Enable t0,t1,t2,t3,t4,t5,t67 are respectively indicated to only have
The Toffoli reversible logic gate of 1 target position, wherein t0,t1,t2,t3It is 5 Toffoli reversible logic gates, and provides t0,
t1,t2,t3The 1st to the 4th be control bit and the 5th is target position, t4,t5,t6It is 2 Toffoli reversible logic gates,
And provide t4,t5,t6The 1st be control bit and the 2nd is target position；Two input terminals of each Fredkin reversible logic gate
In any one input terminal be defined as first input end, a remaining input terminal is defined as the second input terminal, at this
When the control signal of Fredkin reversible logic gate is 0, in two output ends of the Fredkin reversible logic gate, if there is one
The output signal of a output end and the input signal of first input end are consistent, then the output end is defined as the first output end, and another
One output end is defined as second output terminal；Enable f0,f1,f2,f3Respectively indicate 4 Fredkin reversible logic gates；By t0,t1,
t2,t3Logic function configuration circuit in series is controlled and by t at " M is invalid " by CLK4,t5And f1,f3Constitute edge sampling
With storage circuit, controlled by M and at " M is effective " by f0,f2Constitute it is asynchronous set several circuits, by t6Constitute logical inversion circuit；
For logic function configuration circuit, 4 control bit lines, the 1st control bit line and t are set0,t1,t2,t3It is respective
The connection status of 1st control bit is configured to the state of being turned on or off, the 2nd control bit line and t0,t1,t2,t3Respective
The connection status of 2 control bits is configured to the state of being turned on or off, the 3rd control bit line and t0,t1,t2,t3Respective 3rd
The connection status of position control bit is configured to the state of being turned on or off, the 4th control bit line and t0,t1,t2,t3Respective 4th
The connection status of control bit is configured to the state of being turned on or off, t0,t1,t2,t3Respective target position is sequentially connected, i.e. t0Mesh
Mark output and t1Target position input be connected, t1Target position output and t2Target position input be connected, t2Target position output
With t3Target position input be connected, any piece-root grafting in 4 control bit lines enters CLK and and f0The second input terminal connection, Ling Yigen
Access I1, another piece-root grafting enter I2, it is one and f remaining1The first output end connection, t0Target position input and f3The first output end
Connection, t3Target position output and f1First input end connection；
For edge sampling and storage circuit, t4,t5Respective 1 control bit is and f1The first output end connection, t4,t5
Respective target position input accesses logical zero, t4Target position output and f2First input end connection, t5Target position it is defeated
Out and f3First input end connection, f1Control signal be f0Second output terminal output signal, f1First input end with
t3Target position export connection, f1The second input terminal and f2The first output end connection, f1The first output end output signal
For Q, f1Second output terminal be rubbish position output end, f3Control signal be CLK, f3The second input terminal access logical zero,
f3The first output end and t0Target position input connection, f3Second output terminal be rubbish position output end；
Several circuits, f are set for asynchronous0Control signal be M, f0First input end access logical one, f0It is second defeated
Enter end and is connect with the control bit line for accessing CLK, f0The first output end be rubbish position output end, f0Second output terminal output
Signal is as f1Control signal, f2Control signal be M, f2First input end and t4Target position export connection, f2?
Two input terminals access A, f2The first output end and f1The second input terminal connection, f2Second output terminal be rubbish position output end；
For negating circuit, t61 control bit and f1The first output end connection, t6Target position input access logic
" 1 ", t6Target position output output signal be
The configuration method of the configurable reversible trigger of above-mentioned logic function, it is characterised in that the configuration method is by changing
Become the t in reversible trigger0,t1,t2,t3Each control bit and 4 control bit lines connection status, to realize reversible D triggering
Device logic function；Realize the configuration process of reversible d type flip flop logic function are as follows: in I1And I2In it is optional one as reversible D trigger
The data input signal of device and another is connected with logical zero；In t0,t1,t2,t3In optional one, for what is chosen
Toffoli reversible logic gate configures the connection status of itself and the control bit line for the data input signal for accessing reversible d type flip flop
On state is configured on state, and by the connection status of itself and the control bit line of access CLK；For in t0,t1,t2,t3
In not selected 3 Toffoli reversible logic gates, will with access connection logical zero data input signal control bit
The connection status of line is configured on state.
The configuration method of the configurable reversible trigger of above-mentioned logic function, it is characterised in that the configuration method is by changing
Become the t in reversible trigger0,t1,t2,t3Each control bit and 4 control bit lines connection status, to realize reversible T triggering
Device logic function；Realize the configuration process of reversible T trigger logic function are as follows: in I1And I2In it is optional one as reversible T trigger
The data input signal of device and another access logical zero；In t0,t1,t2,t3In optional one, for the Toffoli chosen
The connection status of itself and the control bit line for the data input signal for accessing reversible T trigger is configured to be connected by reversible logic gate
State, and the connection status of itself and the control bit line of access CLK is configured on state；In t0,t1,t2,t3In be not selected
3 Toffoli reversible logic gates in optional one, by itself and f1The first output end connection control bit line connection status
It is configured on state, and the connection status of itself and the control bit line of access CLK is configured on state；For in t0,t1,
t2,t3In 2 Toffoli reversible logic gates not being selected, this 2 Toffoli reversible logic gates are respectively connected with access
The connection status of the control bit line of the data input signal of logical zero is configured on state.
The configuration method of the configurable reversible trigger of above-mentioned logic function, it is characterised in that the configuration method is by changing
Become the t in reversible trigger0,t1,t2,t3Each control bit and 4 control bit lines connection status, to realize reversible JK touching
Send out device logic function；Realize the configuration process of reversible JK flip-flop logic function are as follows: in I1And I2In it is optional one be used as reversible JK
The J end data input signal of trigger and another K end data input signal as reversible JK flip-flop；In t0,t1,t2,t3
In optional 3, for the 3 Toffoli reversible logic gates chosen, respectively and f by it1The first output end connection control bit
The connection status of line is configured on state；Optional 2 again in the 3 Toffoli reversible logic gates chosen, for selecting again
In 2 Toffoli reversible logic gates, the Toffoli reversible logic gate that any one is chosen again and access reversible JK and trigger
The connection status of the control bit line of the J end data input signal of device is configured on state, and another is chosen again
The connection status of the control bit line of the K end data input signal of Toffoli reversible logic gate and the reversible JK flip-flop of access configures
At on state；For in t0,t1,t2,t3In a Toffoli reversible logic gate not being selected, by its with access it is reversible
The connection status of the control bit line of the J end data input signal of JK flip-flop is configured on state；By t0,t1,t2,t3Respectively
On state is configured to the connection status of the control bit line of access CLK.
Compared with the prior art, the advantages of the present invention are as follows:
1) reversible trigger proposed by the present invention, it is reversible with this by changing the control bit line being arranged in the reversible trigger
The connection status of the control bit of Toffoli reversible logic gate in trigger, the reversible trigger can be made to be respectively provided with can
The logic function of inverse d type flip flop, reversible T trigger and reversible JK flip-flop, so that the reversible trigger has logic function
It can configurable characteristic.
2) reversible trigger proposed by the present invention sets several functions with asynchronous, by changing the value to preset number, Ke Yishi
The now clearing and set of the reversible trigger.
Detailed description of the invention
Fig. 1 a is the schematic diagram of n Toffoli reversible logic gates；
Fig. 1 b is the schematic diagram of 3 Toffoli reversible logic gates；
Fig. 2 is the schematic diagram of Fredkin reversible logic gate (also known as control swap gate)；
Fig. 3 is the reversible electricity with store function being made of Toffoli reversible logic gate and Fredkin reversible logic gate
The schematic diagram of line structure；
Fig. 4 is the circuit diagram for the reversible trigger that logic function of the invention can configure.
Specific embodiment
The present invention will be described in further detail below with reference to the embodiments of the drawings.
In the present invention, Toffoli reversible logic gate and Fredkin reversible logic gate is mainly utilized.Fig. 1 a gives
The schematic diagram of the position the n Toffoli reversible logic gate of only 1 target position, the logic function of the n Toffoli reversible logic gate
It can be expressed as TOF (Ctrl, T),Wherein, Ctrl indicates that control bit is defeated
Enter set, Ctrl={ x0,…,xj-1,xj+1,…,xn-1, T indicates target position input set, T={ xj, and meetCtrl ∪ T=I, " ∩ " is set intersection oeprator, and " ∪ " is collection union operation symbol,Indicate empty set, I table
Show the set that n input variable is constituted, x0,…,xj-1,xj+1,…,xn-1It is inputted for n-1 control bit, xjIt is defeated for 1 target position
Enter, 0≤j≤(n-1), i.e. xjFor any one input variable in n input variable, and remaining input variable is that control bit is defeated
Enter, Pj=Π xi, xiThe corresponding output of ∈ Ctrl, T is known as target position output set, and target position output set is herein
SymbolXOR operation symbol.Fig. 1 b gives the schematic diagram of 3 Toffoli reversible logic gates, Ctrl={ x0,x1, T=
{x2, target position output set isFig. 2 gives the signal of Fredkin reversible logic gate (also known as control swap gate)
Figure, C are control signal, and x and y are input signal, and W and Z are output signal, and as C=1, output signal is the friendship of input signal
It changes, i.e. W=y, Z=x；As C=0, output signal is corresponding input signal, i.e. W=x, Z=y.Fig. 3 give by
The reciprocal circuit structure with store function that Toffoli reversible logic gate and Fredkin reversible logic gate are constituted, C are control
Signal, Q2For input signal, Q1For output signal, F0Indicate Fredkin reversible logic gate, T0Indicate Toffoli reversible logic
Door, as C=1, F0In swap status, T0Output beThat is T0Output equal to control bit input, at this time this
Kind state can be described as T0Output replicate control bit input, that is, be in duplication state, therefore as C=1, Q2Variation will not
Cause Q1Variation, i.e. Q1In latch mode；As C=0, which, which is in, receives data mode, and Q1By more
It is newly Q2, therefore the reciprocal circuit structure has data storage function, and the update of storing data is realized in low level.This hair
The configurable reversible trigger of a kind of logic function of bright proposition, as shown in figure 4, the asynchronous of the reversible trigger sets number control letter
It number is M, clock signal CLK, the first data input signal are I1, the second data input signal be I2, to preset number be A, this can
The state of de-activated device is Q, the benefit of state isM、CLK、I1And I2, A, Q andBit wide be 1, M be logical one when
Be described as " M is effective " i.e. and allow it is asynchronous set number, M is described as " M is invalid " i.e. when being logical zero and does not allow asynchronous to set number；This is reversible
Trigger includes the 7 Toffoli reversible logic gates and 4 Fredkin reversible logic gates for there was only 1 target position；Enable t0,t1,
t2,t3,t4,t5,t67 Toffoli reversible logic gates for there was only 1 target position are respectively indicated, wherein t0,t1,t2,t3It is 5
Position Toffoli reversible logic gate, and provide t0,t1,t2,t3The 1st to the 4th be control bit and the 5th is target position, t4,
t5,t6It is 2 Toffoli reversible logic gates, and provides t4,t5,t6The 1st be control bit and the 2nd is target position；Each
Any one input terminal in two input terminals of Fredkin reversible logic gate be defined as first input end, remaining one it is defeated
Enter end and be defined as the second input terminal, when the control signal of the Fredkin reversible logic gate is 0, in the Fredkin reversible logic
In two output ends of door, if there is the output signal of an output end and the input signal of first input end are consistent, then this is defeated
Outlet is defined as the first output end, and another output is defined as second output terminal；Enable f0,f1,f2,f3Respectively indicate 4
Fredkin reversible logic gate；By t0,t1,t2,t3Logic function configuration circuit in series, controlled at " M is invalid " by CLK and
By t4,t5And f1,f3Edge sampling and storage circuit are constituted, is controlled by M and at " M is effective " by f0,f2It constitutes asynchronous set and counts electricity
Road, by t6Constitute logical inversion circuit.
For logic function configuration circuit, 4 control bit lines, the 1st control bit line and t are set0,t1,t2,t3It is respective
The connection status of 1st control bit is configured to the state of being turned on or off, the 2nd control bit line and t0,t1,t2,t3Respective
The connection status of 2 control bits is configured to the state of being turned on or off, the 3rd control bit line and t0,t1,t2,t3Respective 3rd
The connection status of position control bit is configured to the state of being turned on or off, the 4th control bit line and t0,t1,t2,t3Respective 4th
The connection status of control bit is configured to the state of being turned on or off, t0,t1,t2,t3Respective target position is sequentially connected, i.e. t0Mesh
Mark output and t1Target position input be connected, t1Target position output and t2Target position input be connected, t2Target position output
With t3Target position input be connected, any piece-root grafting in 4 control bit lines enters CLK and and f0The second input terminal connection, Ling Yigen
Access I1, another piece-root grafting enter I2, it is one and f remaining1The first output end connection, t0Target position input and f3The first output end
Connection, t3Target position output and f1First input end connection.
For edge sampling and storage circuit, t4,t5Respective 1 control bit is and f1The first output end connection, t4,t5
Respective target position input accesses logical zero, t4Target position output and f2First input end connection, t5Target position it is defeated
Out and f3First input end connection, f1Control signal be f0Second output terminal output signal, f1First input end with
t3Target position export connection, f1The second input terminal and f2The first output end connection, f1The first output end output signal
For Q, " M is invalid " and t when CLK is low level 0 in this way3Target position output output signal be Q, f1Second output terminal be rubbish
Rubbish position output end, f3Control signal be CLK, f3The second input terminal access logical zero, f3The first output end and t0Mesh
Mark input connection, the in this way f when CLK is high level 13The first output end output signal be logical zero, f3It is second defeated
Outlet is rubbish position output end.
Several circuits, f are set for asynchronous0Control signal be M, f0First input end access logical one, f0It is second defeated
Enter end and is connect with the control bit line for accessing CLK, f0The first output end be rubbish position output end, f0Second output terminal output
Signal is as f1Control signal, f2Control signal be M, f2First input end and t4Target position export connection, f2?
Two input terminals access A, f2The first output end and f1The second input terminal connection, in this way " M is effective " when f2First output end
Output signal is A, f2Second output terminal be rubbish position output end.
For negating circuit, t61 control bit and f1The first output end connection, t6Target position input access logic
" 1 ", t6Target position output output signal be
In Fig. 4, the 1st control bit line access CLK, the 2nd control bit line access I1, the 3rd piece control bit line access I2、
4th control bit line and f1The first output end connection, t0,t1,t2,t3It sequentially connects, wherein t0Target position input and f3's
First output end is connected, t3Target position output and f1First input end be connected.
Assuming that the present status of the reversible trigger is Q0, as can be known from Fig. 4, t3Target position output can be expressed as closing
In CLK, I1,I2,Q0Logical function, use T3(CLK,I1,I2,Q0) indicate, as M=0, f0The first output end output
It is logical one, f that signal, which is equal to corresponding input signal,0Second output terminal output signal be equal to corresponding input signal
As CLK, f2The first output end output signal be equal to corresponding input signal be t4Target position output output letter
Number, due to t4For 2 Toffoli reversible logic gates, and the input of target position connects logical zero, it is contemplated that Toffoli reversible logic gate
Target position output output signal be equal to its target position input input signal and its each control bit signal logical "and"
Distance, therefore t4Target position output output signal be equal tof2Second output terminal output signal
It is A equal to corresponding input signal；Due to M=0, f1Control signal be exactly CLK, as CLK=1, f1And f3Output letter
Number be equal to corresponding input signal exchange, i.e. f1The first output end output signal be equal to its second input terminal input believe
Number, f1Second output terminal output signal be equal to its first input end input signal, f3The first output end output signal
Equal to the input signal of its second input terminal, f3Second output terminal output signal be equal to its first input end input believe
Number, so that t4、f2And f1Constitute the reciprocal circuit with store function, and I1,I2Variation can only cause T3(CLK,
I1,I2,Q0) variation, but do not influence the output of the reversible trigger；When CLK becomes " 0 " from " 1 ", due to M=0,
f0、f2、f1And f3Respective first output end, second output terminal output signal be equal to respective first input end, second defeated
Enter the input signal at end, the output of the reversible trigger is by Q0Become T3(CLK,I1,I2,Q0)；Simultaneously as CLK=0, therefore
t3Target position output output signal be equal to t0The input of target position input signal, and t0Target position input input letter
Number be equal to t5Target position output output signal, value be equal to T3(CLK,I1,I2,Q0), that is, the output of reversible trigger, because
This, is in CLK=0, t5、f3、t0,t1,t2,t3And f1Constitute the reciprocal circuit with store function, and the number latched
According to being updated to T3(CLK,I1,I2,Q0)；Therefore, reversible trigger shown in Fig. 4 has failing edge Trigger Function, and next shape
State output is T3(CLK,I1,I2,Q0)。
As M=1, f1Control signal become logical one, so f0,f1,f2Respective output signal is equal to respectively defeated
Enter the exchange of signal, A is through f2And f1It is transmitted to the output end of the reversible trigger, the output of the reversible trigger becomes A, and in M
When=1, the variation of CLK will not influence the output of the reversible trigger；In addition, at this time should when M occurs to become " 0 " variation from " 1 "
The following 2 kinds of situation discussion of the state of reversible trigger point: (1) work as CLK=1, in this case f1Output signal it is constant, and t4、
f2And f1The reciprocal circuit with store function is constituted, so that the output of the reversible trigger keeps A constant；(2) when
CLK=0, t5、f3、t0,t1,t2,t3And f1The reciprocal circuit with store function is constituted, and the data latched are exactly A.
From being analyzed above it is found that the reversible trigger, which is one, asynchronous can set several edge triggered flip flops, the reversible trigger it is next
The output of a state and T3(CLK,I1,I2,Q0) related.
The configuration method of the configurable reversible trigger of above-mentioned logic function, the configuration method can de-activateds by changing
T in device0,t1,t2,t3Each control bit and 4 control bit lines connection status, to realize reversible d type flip flop logic function
Energy, reversible T trigger logic function or reversible JK flip-flop logic function.
Realize the configuration process of reversible d type flip flop logic function are as follows: in I1And I2In it is optional one be used as reversible d type flip flop
Data input signal and another is connected with logical zero；In t0,t1,t2,t3In optional one, for what is chosen
Toffoli reversible logic gate configures the connection status of itself and the control bit line for the data input signal for accessing reversible d type flip flop
On state is configured on state, and by the connection status of itself and the control bit line of access CLK；For in t0,t1,t2,t3
In not selected 3 Toffoli reversible logic gates, will with access connection logical zero data input signal control bit
The connection status of line is configured on state.
Realize the configuration process of reversible T trigger logic function are as follows: in I1And I2In it is optional one be used as reversible T trigger
Data input signal and another access logical zero；In t0,t1,t2,t3In optional one, can for the Toffoli chosen
The connection status of itself and the control bit line for the data input signal for accessing reversible T trigger is configured to conducting shape by inverse logic gate
State, and the connection status of itself and the control bit line of access CLK is configured on state；In t0,t1,t2,t3In it is not selected
Optional one in 3 Toffoli reversible logic gates, by itself and f1The connection status of control bit line of the first output end connection match
It is set on state, and the connection status of itself and the control bit line of access CLK is configured on state；For in t0,t1,t2,
t3In 2 Toffoli reversible logic gates not being selected, this 2 Toffoli reversible logic gates are respectively patrolled with access connection
The connection status for collecting the control bit line of the data input signal of " 0 " is configured on state.
Realize the configuration process of reversible JK flip-flop logic function are as follows: in I1And I2In it is optional one as reversible JK trigger
The J end data input signal of device and another K end data input signal as reversible JK flip-flop；In t0,t1,t2,t3In appoint
3 are selected, for the 3 Toffoli reversible logic gates chosen, respectively and f by it1The connection of first output end control bit line
Connection status is configured on state；Optional 2 again in the 3 Toffoli reversible logic gates chosen, for what is chosen again
2 Toffoli reversible logic gates, the Toffoli reversible logic gate that any one is chosen again and the J for accessing reversible JK flip-flop
The connection status of the control bit line of end data input signal is configured on state, and the Toffoli that another is chosen again
The connection status of the control bit line of the K end data input signal of reversible logic gate and the reversible JK flip-flop of access is configured to conducting shape
State；For in t0,t1,t2,t3In a Toffoli reversible logic gate not being selected, by itself and the reversible JK flip-flop of access
The connection status of control bit line of J end data input signal be configured on state；By t0,t1,t2,t3Respectively with access CLK
The connection status of control bit line be configured on state.
The method of the present invention is tested below in conjunction with Fig. 4, to verify the feasibility and validity of the method for the present invention.Scheming
In 4, the symbol "×" in 4 control bit lines indicates that the connection status on the aspect can be configured to the state of being turned on or off, symbol
" " indicates that the point is in the conductive state.In order to facilitate the "×" distinguished on different location, to t in Fig. 40,t1,t2,t3It is related
Signal wire be numbered, 4 articles of lateral signal wire i.e. the 1st piece control bit lines, the 2nd control bit line, the 3rd control bit line and the
Number is 1,2,3,4 to 4 control bit lines respectively from top to bottom；Number is α, β, γ, τ to 4 longitudinal signal lines respectively from left to right.
Obviously, the position of the "×" in the most upper left corner can be expressed as (α, 1), and similarly, the position of other "×" can also be where it
The vertical line combination numbered with x wire of number indicate；In Fig. 4, if the original state of reversible trigger is Q0。
Its logic is verified by reversible trigger arrangement shown in Fig. 4 at a reversible d type flip flop according to the method for the present invention
The correctness of function.Such as: in I1And I2Middle selection I1Data input signal, I as reversible d type flip flop2It is connected with logical zero
It connects, in t0,t1,t2,t3Middle selection t0, by t0With access I1The connection status of control bit line be configured on state (position in Fig. 4
It is set at (α, 2) as on state), and by t0On state (Fig. 4 is configured to the connection status of the control bit line of access CLK
It is on state that middle position, which is at (α, 1)), by t1With access I2The connection status of control bit line be configured on state (Fig. 4
It is on state that middle position, which is at (β, 3)), by t2With access I2The connection status of control bit line be configured on state (Fig. 4
It is on state that middle position, which is at (γ, 3)), by t3With access I2The connection status of control bit line be configured on state (Fig. 4
It is on state that middle position, which is at (τ, 3)).Therefore position is (α, 1), (α, 2), (β, 3), (γ, 3), 5 positions of (τ, 3)
On the corresponding signal wire of "×" intersection point it is in the conductive state, the "×" in other positions is in an off state.Due to t0's
The input signal of target position input is Q in CLK=00, and t1,t2,t3The output signal of respective target position output is equal to each
The input signal inputted from target position, i.e., final t3Target position output output signal be equal to t0Target position input input
Signal.The t in CLK=10Target position input input signal be f3The input signal of second input terminal is equal to 0.Therefore in M
When=0, under above-mentioned configuration, t3Target position output output signal T3(CLK,I1,I2,Q0) indicate, thenI.e. in CLK=1,
T3(CLK,d,0,Q0) it is updated to d, Q is kept in CLK=00It is constant, so reversible d type flip flop logic function is realized in above-mentioned configuration
Energy.And as M=1, f2The output signal of the first output end be A so that the output Q of reversible trigger is also equal to A, realize different
Step sets several functions.
Its logic is verified by reversible trigger arrangement shown in Fig. 4 at a reversible T trigger according to the method for the present invention
The correctness of function.Such as: in I1And I2Middle selection I1Data input signal, I as reversible T trigger2It is set to logical zero,
t0,t1,t2,t3Middle selection t0, by t0With access I1The connection status of control bit line be configured on state (position be in Fig. 4
It is on state at (α, 2)), and by t0On state (position in Fig. 4 is configured to the connection status of the control bit line of access CLK
It is set at (α, 1) as on state), in t1,t2,t3Middle selection t1, by t1With f1The connection of first output end control bit line
Connection status be configured on state (in Fig. 4 position be (β, 4) at be on state), and by itself and access CLK control bit
The connection status of line is configured on state (it is on state that position, which is at (β, 1), in Fig. 4), by t2With access I2Control bit
The connection status of line is configured on state (it is on state that position, which is at (γ, 3), in Fig. 4), by t3With access I2Control bit
The connection status of line is configured on state (it is on state that position, which is at (τ, 3), in Fig. 4).Therefore position be (α, 1), (α,
2) intersection point of, (β, 1), (β, 4), (γ, 3), the corresponding signal wire of "×" on 6 positions of (τ, 3) are in the conductive state,
"×" on his position is in an off state.In this configuration, as M=0, T3(CLK,I1,I2,Q0) logic function can
To be expressed asI.e. in CLK=1, T3
(CLK,T,0,Q0) be updated toQ is kept in CLK=00It is constant, so reversible T trigger logic function is realized in above-mentioned configuration
Energy；And as M=1, f2The output signal of the first output end be A so that the output of reversible trigger also becomes A, realize asynchronous
Set several functions.
Its logic is verified by reversible trigger arrangement shown in Fig. 4 at a reversible JK flip-flop according to the method for the present invention
The correctness of function.Such as: by I1As the J end data input signal of reversible JK flip-flop, by I2K as reversible JK flip-flop
End data input signal；Select t1,t2,t3, by t1With f1The connection status of control bit line of the first output end connection be configured to
On state (it is on state that position, which is at (β, 4), in Fig. 4), by t2With f1The first output end connection control bit line company
The state of connecing is configured on state (it is on state that position, which is at (γ, 4), in Fig. 4), by t3With f1The first output end connection
The connection status of control bit line is configured on state (it is on state that position, which is at (τ, 4), in Fig. 4)；T is selected again2,t3,
By t2With access I1Control bit line connection status be configured on state (in Fig. 4 position be (γ, 2) at be on state),
By t3With access I2Control bit line connection status be configured on state (in Fig. 4 position be (τ, 3) at be on state)；
By t0With access I1Control bit line connection status be configured on state (in Fig. 4 position be (α, 2) at be on state)；
By t0,t1,t2,t3Respectively with access CLK control bit line connection status be configured on state (in Fig. 4 position be (α, 1),
It is on state at (β, 1), (γ, 1), (τ, 1)).Therefore position be (α, 1), (α, 2), (β, 1), (β, 4), (γ, 1), (γ,
2) intersection point of, (γ, 4), (τ, 1), (τ, 3), the corresponding signal wire of "×" on the position (τ, 4) are in the conductive state, other positions
The "×" set is in an off state.As M=0, in this configuration, T3(CLK,I1,I2,Q0) logic function can be with table
It is shown asIt can be obtained after abbreviationI.e. in CLK=1, T3(CLK,J,K,Q0) be updated toQ is kept in CLK=00It is constant, so reversible JK flip-flop logic function is realized in above-mentioned configuration.And as M=1,
f2The output signal of the first output end be A so that the output of reversible trigger becomes A, realize and asynchronous set several functions.
Claims (4)
1. a kind of configurable reversible trigger of logic function, it is characterised in that the asynchronous of the reversible trigger sets number control signal
It is I for M, clock signal CLK, the first data input signal1, the second data input signal be I2, to preset number be A, this is reversible
The state of trigger is Q, the benefit of state isM、CLK、I1And I2, A, Q andBit wide be 1, M be logical one when retouch
State for " M is effective " allow it is asynchronous set number, M is described as " M is invalid " i.e. when being logical zero and does not allow asynchronous to set number；The reversible touching
Hair device includes the 7 Toffoli reversible logic gates and 4 Fredkin reversible logic gates for there was only 1 target position；Enable t0,t1,
t2,t3,t4,t5,t67 Toffoli reversible logic gates for there was only 1 target position are respectively indicated, wherein t0,t1,t2,t3It is 5
Position Toffoli reversible logic gate, and provide t0,t1,t2,t3The 1st to the 4th be control bit and the 5th is target position, t4,
t5,t6It is 2 Toffoli reversible logic gates, and provides t4,t5,t6The 1st be control bit and the 2nd is target position；Each
Any one input terminal in two input terminals of Fredkin reversible logic gate be defined as first input end, remaining one it is defeated
Enter end and be defined as the second input terminal, when the control signal of the Fredkin reversible logic gate is 0, in the Fredkin reversible logic
In two output ends of door, if there is the output signal of an output end and the input signal of first input end are consistent, then this is defeated
Outlet is defined as the first output end, and another output is defined as second output terminal；Enable f0,f1,f2,f3Respectively indicate 4
Fredkin reversible logic gate；By t0,t1,t2,t3Logic function configuration circuit in series, controlled at " M is invalid " by CLK and
By t4,t5And f1,f3Edge sampling and storage circuit are constituted, is controlled by M and at " M is effective " by f0,f2It constitutes asynchronous set and counts electricity
Road, by t6Constitute logical inversion circuit；
For logic function configuration circuit, 4 control bit lines, the 1st control bit line and t are set0,t1,t2,t3Respective 1st
The connection status of control bit is configured to the state of being turned on or off, the 2nd control bit line and t0,t1,t2,t3Respective 2nd control
The connection status of position processed is configured to the state of being turned on or off, the 3rd control bit line and t0,t1,t2,t3Respective 3rd control
The connection status of position is configured to the state of being turned on or off, the 4th control bit line and t0,t1,t2,t3Respective 4th control bit
Connection status be configured to the state of being turned on or off, t0,t1,t2,t3Respective target position is sequentially connected, i.e. t0Target position it is defeated
Out and t1Target position input be connected, t1Target position output and t2Target position input be connected, t2Target position output and t3's
The input of target position is connected, and any piece-root grafting in 4 control bit lines enters CLK and and f0The connection of the second input terminal, another piece-root grafting enters
I1, another piece-root grafting enter I2, it is one and f remaining1The first output end connection, t0Target position input and f3The first output end connect
It connects, t3Target position output and f1First input end connection；
For edge sampling and storage circuit, t4,t5Respective 1 control bit is and f1The first output end connection, t4,t5Respectively
Target position input access logical zero, t4Target position output and f2First input end connection, t5Target position output with
f3First input end connection, f1Control signal be f0Second output terminal output signal, f1First input end and t3's
The output connection of target position, f1The second input terminal and f2The first output end connection, f1The first output end output signal be Q,
f1Second output terminal be rubbish position output end, f3Control signal be CLK, f3The second input terminal access logical zero, f3's
First output end and t0Target position input connection, f3Second output terminal be rubbish position output end；
Several circuits, f are set for asynchronous0Control signal be M, f0First input end access logical one, f0The second input terminal
It is connect with the control bit line of access CLK, f0The first output end be rubbish position output end, f0Second output terminal output signal
As f1Control signal, f2Control signal be M, f2First input end and t4Target position export connection, f2It is second defeated
Enter and terminates into A, f2The first output end and f1The second input terminal connection, f2Second output terminal be rubbish position output end；
For negating circuit, t61 control bit and f1The first output end connection, t6Target position input access logical one, t6
Target position output output signal be
2. a kind of configuration method of the configurable reversible trigger of logic function described in claim 1, it is characterised in that this is matched
Method is set by changing the t in reversible trigger0,t1,t2,t3Each control bit and 4 control bit lines connection status, with
Realize reversible d type flip flop logic function；Realize the configuration process of reversible d type flip flop logic function are as follows: in I1And I2In optional one
As reversible d type flip flop data input signal and another is connected with logical zero；In t0,t1,t2,t3In optional one,
For the Toffoli reversible logic gate chosen, by the company of itself and the control bit line for the data input signal for accessing reversible d type flip flop
The state of connecing is configured on state, and the connection status of itself and the control bit line of access CLK is configured on state；For
t0,t1,t2,t3In not selected 3 Toffoli reversible logic gates, will with access connection logical zero data input believe
Number the connection status of control bit line be configured on state.
3. a kind of configuration method of the configurable reversible trigger of logic function described in claim 1, it is characterised in that this is matched
Method is set by changing the t in reversible trigger0,t1,t2,t3Each control bit and 4 control bit lines connection status, with
Realize reversible T trigger logic function；Realize the configuration process of reversible T trigger logic function are as follows: in I1And I2In optional one
As reversible T trigger data input signal and another access logical zero；In t0,t1,t2,t3In optional one, for
The Toffoli reversible logic gate chosen, by the connection shape of itself and the control bit line for the data input signal for accessing reversible T trigger
State is configured on state, and the connection status of itself and the control bit line of access CLK is configured on state；In t0,t1,t2,
t3In optional one in not selected 3 Toffoli reversible logic gates, by itself and f1The first output end connection control bit
The connection status of line is configured on state, and the connection status of itself and the control bit line of access CLK is configured on state；
For in t0,t1,t2,t3In 2 Toffoli reversible logic gates not being selected, this 2 Toffoli reversible logic gates are each
On state is configured to from the connection status of the control bit line of the data input signal with access connection logical zero.
4. a kind of configuration method of the configurable reversible trigger of logic function described in claim 1, it is characterised in that this is matched
Method is set by changing the t in reversible trigger0,t1,t2,t3Each control bit and 4 control bit lines connection status, with
Realize reversible JK flip-flop logic function；Realize the configuration process of reversible JK flip-flop logic function are as follows: in I1And I2In optional one
A J end data input signal as reversible JK flip-flop and another K end data input signal as reversible JK flip-flop；
In t0,t1,t2,t3In optional 3, for the 3 Toffoli reversible logic gates chosen, respectively and f by it1The first output end
The connection status of the control bit line of connection is configured on state；Again optional 2 in the 3 Toffoli reversible logic gates chosen
It is a, for the 2 Toffoli reversible logic gates chosen again, Toffoli reversible logic gate that any one is chosen again with connect
The connection status for entering the control bit line of the J end data input signal of reversible JK flip-flop is configured on state, and by another
The company of the control bit line of the K end data input signal of the Toffoli reversible logic gate and the reversible JK flip-flop of access chosen again
The state of connecing is configured on state；For in t0,t1,t2,t3In a Toffoli reversible logic gate not being selected, by it
On state is configured to the connection status of the control bit line for the J end data input signal for accessing reversible JK flip-flop；By t0,t1,
t2,t3Respectively the connection status with the control bit line of access CLK is configured on state.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112865756A (en) * | 2021-01-15 | 2021-05-28 | 宁波大学 | Reversible double-edge D trigger capable of asynchronously setting number |
| CN112865757A (en) * | 2021-01-15 | 2021-05-28 | 宁波大学 | Logic function configurable reversible single edge trigger |
| CN112865758A (en) * | 2021-01-15 | 2021-05-28 | 宁波大学 | Reversible single-edge T trigger capable of asynchronously setting number |
| CN112910444A (en) * | 2021-01-15 | 2021-06-04 | 宁波大学 | Reversible single-edge D trigger capable of asynchronously setting number |
| CN112910454A (en) * | 2021-01-15 | 2021-06-04 | 宁波大学 | Reversible single-edge JK trigger capable of asynchronously setting number |
| CN112910442A (en) * | 2021-01-15 | 2021-06-04 | 宁波大学 | Reversible double-edge trigger with configurable logic function |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1333869A (en) * | 1971-05-04 | 1973-10-17 | Tesla Np | Electrical circuit for digital control of stepping motor without inadvertent reverse direction of rotation |
| US7427876B1 (en) * | 2007-03-19 | 2008-09-23 | National Tsing Hua University | Reversible sequential element and reversible sequential circuit thereof |
| CN102624380A (en) * | 2012-04-13 | 2012-08-01 | 南通大学 | Three-position reversible ternary-binary logic converter |
| CN204631850U (en) * | 2015-04-22 | 2015-09-09 | 宜宾学院 | Eight the three reversible totalizers of value and encapsulating structure thereof |
-
2018
- 2018-11-28 CN CN201811432160.8A patent/CN109687848B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1333869A (en) * | 1971-05-04 | 1973-10-17 | Tesla Np | Electrical circuit for digital control of stepping motor without inadvertent reverse direction of rotation |
| US7427876B1 (en) * | 2007-03-19 | 2008-09-23 | National Tsing Hua University | Reversible sequential element and reversible sequential circuit thereof |
| CN102624380A (en) * | 2012-04-13 | 2012-08-01 | 南通大学 | Three-position reversible ternary-binary logic converter |
| CN204631850U (en) * | 2015-04-22 | 2015-09-09 | 宜宾学院 | Eight the three reversible totalizers of value and encapsulating structure thereof |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112865756A (en) * | 2021-01-15 | 2021-05-28 | 宁波大学 | Reversible double-edge D trigger capable of asynchronously setting number |
| CN112865757A (en) * | 2021-01-15 | 2021-05-28 | 宁波大学 | Logic function configurable reversible single edge trigger |
| CN112865758A (en) * | 2021-01-15 | 2021-05-28 | 宁波大学 | Reversible single-edge T trigger capable of asynchronously setting number |
| CN112910444A (en) * | 2021-01-15 | 2021-06-04 | 宁波大学 | Reversible single-edge D trigger capable of asynchronously setting number |
| CN112910454A (en) * | 2021-01-15 | 2021-06-04 | 宁波大学 | Reversible single-edge JK trigger capable of asynchronously setting number |
| CN112910442A (en) * | 2021-01-15 | 2021-06-04 | 宁波大学 | Reversible double-edge trigger with configurable logic function |
| CN112910441A (en) * | 2021-01-15 | 2021-06-04 | 宁波大学 | Reversible double-edge JK trigger capable of asynchronously setting number |
| CN112910454B (en) * | 2021-01-15 | 2022-03-29 | 宁波大学 | Reversible single-edge JK trigger capable of asynchronously setting number |
| CN112910441B (en) * | 2021-01-15 | 2022-03-29 | 宁波大学 | Reversible double-edge JK trigger capable of asynchronously setting number |
| CN112865758B (en) * | 2021-01-15 | 2022-03-29 | 宁波大学 | Reversible single-edge T trigger capable of asynchronously setting number |
| CN112865756B (en) * | 2021-01-15 | 2022-03-29 | 宁波大学 | Reversible double-edge D trigger capable of asynchronously setting number |
| CN112910442B (en) * | 2021-01-15 | 2022-03-29 | 宁波大学 | Reversible double-edge trigger with configurable logic function |
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| CN117275401B (en) * | 2023-11-03 | 2024-02-27 | 中山市智牛电子有限公司 | Image reduction circuit, LED display screen control card and image scaling method |
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