CN112910441A - Reversible double-edge JK trigger capable of asynchronously setting number - Google Patents

Reversible double-edge JK trigger capable of asynchronously setting number Download PDF

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CN112910441A
CN112910441A CN202110055801.8A CN202110055801A CN112910441A CN 112910441 A CN112910441 A CN 112910441A CN 202110055801 A CN202110055801 A CN 202110055801A CN 112910441 A CN112910441 A CN 112910441A
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CN112910441B (en
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吴钰
王伦耀
储著飞
夏银水
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Ningbo University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

Abstract

The invention discloses a reversible double-edge JK trigger capable of asynchronously setting numbers, which consists of 1 NOT reversible logic gate, 4 Feynman reversible logic gates and 7 Fredkin reversible logic gates, and is provided with an asynchronous number setting enabling signal input end, a clock signal input end, a first data input end, a second data input end, a preset number input end, a first logic low level input end, a second logic low level input end, a third logic low level input end, a fourth logic low level input end, an asynchronous number setting enabling signal output end, a trigger present signal output end, a first garbage position output end, a second garbage position output end, a third garbage position output end, a fourth garbage position output end, a fifth garbage position output end, a sixth garbage position output end and a seventh garbage position output end; the reversible sequential logic circuit has the advantages of having the function of a double-edge JK trigger and an asynchronous number setting function, and enabling the reversible sequential logic circuit to run from a determined initial state or return to a controllable determined state from an error state after the asynchronous number setting.

Description

Reversible double-edge JK trigger capable of asynchronously setting number
Technical Field
The invention relates to a reversible logic circuit, in particular to a reversible double-edge JK trigger capable of asynchronously setting numbers, which is formed by a NOT reversible logic gate, a Feynman reversible logic gate and a Fredkin reversible logic gate.
Background
How to reduce the power consumption of the circuit is a key issue in the current integrated circuit design. In a conventional irreversible logic circuit, information bit data loss is a main cause of circuit power consumption, and therefore, a reversible logic circuit design capable of avoiding information bit data loss has become an approach to low power consumption design. Meanwhile, the reversible logic circuit is also an important component for quantum computation and quantum information technology research.
The reversible logic circuit includes a reversible combinational logic circuit and a reversible sequential logic circuit. In a reversible sequential logic circuit, the significance of the set-up signal is second only to the clock signal, and the most basic purpose of asynchronous set-up is to bring the circuit into a certain state that can operate stably. The reversible flip-flop is a basic device constituting the reversible sequential logic circuit, how to initialize the reversible sequential logic circuit is a link which must be faced in the design process of the reversible sequential logic circuit, and the initialization of the reversible sequential logic circuit can be generally realized by initializing the reversible flip-flop.
The reversible flip-flop can be implemented using a NOT reversible logic gate, a Feynman reversible logic gate, and a Fredkin reversible logic gate. Fig. 1 is a schematic circuit diagram of a NOT reversible logic gate. NOT reversible logic gate has 1 input terminal, marked as Iv(ii) a NOT reversible logic gate has 1 output, noted as Ov. Suppose an input to an input terminal IvThe input value of is W, the output value of the output end is
Figure BDA0002900556150000011
Wherein the content of the first and second substances,
Figure BDA0002900556150000012
indicating that W is not logically operated. Fig. 2 is a schematic circuit diagram of a Feynman reversible logic gate. The Feynman reversible logic gate has 2 input ends, namely a control input end and a target input end which are correspondingly marked as It1And It2(ii) a The Feynman reversible logic gate has 2 output terminals, namely a control output terminal and a target output terminal, which are correspondingly marked as Ot1And Ot2. Assume input to control inputInput terminal It1Is A and is input to a target input terminal It2If the input value is B, the output terminal O is controlledt1The output value is A, and the target output end is Ot2Output an output value of
Figure BDA0002900556150000013
Wherein, the symbol
Figure BDA0002900556150000014
Is an exclusive or operation sign. Fig. 3 is a schematic diagram of a circuit structure of a Fredkin reversible logic gate. Fredkin reversible logic gate has 3 input ends, respectively control input end, first target input end and second target input end, and are marked as If1、If2And If3The Fredkin reversible logic gate has 3 output terminals, namely a control output terminal, a first target output terminal and a second target output terminal, which are correspondingly marked as Of1、Of2And Of3. Assume input to control input If1Is X, is input to a first target input terminal If2Is Y, is input to a second target input terminal If3Is Z, the output terminal O is controlledf1The output value of X, i.e. the control output Of1The output value of the output is equal to the input value of the control input terminal If1Input value of, first target output terminal Of2Output an output value of
Figure BDA0002900556150000021
Second target output terminal Of3Output an output value of
Figure BDA0002900556150000022
When input to the control input terminal If1When the input value of (1) is "0", the first target output terminal Of2The output value is Y, and the second target output end is Of3The output value is Z, i.e. the first target output terminal Of2The output value of the output is equal to the input value of the first target input end If2Input value of, second target output terminal Of3The output value of the output is equal to the input to the second target outputInput terminal If3An input value of (a); when input to the control input terminal If1When the input value of (1) is zero, the first target output terminal Of2Output value Z, second target output terminal Of3The output value is Y, i.e. the first target output terminal Of2The output value of the output is equal to the input value of the second target input end If3Input value of, second target output terminal Of3The output value of the output is equal to the input value of the first target input end If2The input value of (a), wherein,
Figure BDA0002900556150000023
indicating that X is not logically operated on.
However, the conventional reversible flip-flop does not have an asynchronous setting function, and therefore, it is advantageous to develop a reversible double-edge JK flip-flop having an asynchronous setting function to make the reversible sequential logic circuit operate from a certain initial state or return from an error state to a certain state which can be controlled after the asynchronous setting.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a reversible double-edge JK trigger capable of asynchronously setting numbers, which has the function of the double-edge JK trigger and the function of asynchronously setting numbers, and is beneficial to enabling a reversible sequential logic circuit to run from a determined initial state or return from an error state to a controllable determined state after the asynchronous setting numbers.
The technical scheme adopted by the invention for solving the technical problems is as follows: a reversible double-edge JK trigger capable of asynchronously setting numbers is characterized by being composed of 1 NOT reversible logic gate, 4 Feynman reversible logic gates and 7 Fredkin reversible logic gates, wherein the 4 Feynman reversible logic gates are respectively marked as t1、t2、t3And t4Will t1、t2、t3And t4Respective control input terminal as first input terminal, let t1、t2、t3And t4Respective target input terminal as second input terminal, let t1、t2、t3And t4Respective control output terminal asAn output terminal for outputting t1、t2、t3And t4Respective target output terminal as second output terminal at t1、t2、t3And t4The output value of the first output end is equal to the input value of the first input end, the output value of the second output end is equal to the logical exclusive OR of the input value of the first input end and the input value of the second input end, and the NOT reversible logic gate is marked as t57 Fredkin reversible logic gates are respectively recorded as f1、f2、f3、f4、f5、f6And f7A 1 is to f1、f2、f3、f4、f5、f6And f7Respective control input terminal as first input terminal, f1、f2、f3、f4、f5、f6And f7Respective first target input terminal as second input terminal, and f1、f2、f3、f4、f5、f6And f7Respective second target input terminal as third input terminal, and f1、f2、f3、f4、f5、f6And f7Respective control output terminal as the first output terminal, and f1、f2、f3、f4、f5、f6And f7Respective first target output terminal as second output terminal, and f1、f2、f3、f4、f5、f6And f7Respective second target output terminal as third output terminal at f1、f2、f3、f4、f5、f6And f7In each case, the output value of the first output terminal is equal to the input value of the first input terminal, the output value of the second output terminal is equal to the input value of the second input terminal and the output value of the third output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "0", the output value of the second output terminal is equal to the input value of the third input terminal and the output value of the third output terminal is equal to the like when the input value of the first input terminal is "1An input value at a second input terminal;
the reversible double-edge JK flip-flop comprises an asynchronous digital enable signal input end M, a clock signal input end C and a first data input end I1A second data input terminal I2A preset number input terminal P, a first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3A fourth logic low level input terminal L4And an asynchronous setting enable signal output end M', a trigger present signal output end Q and a first garbage position output end g1And a second garbage position output end g2And a third garbage position output end g3And a fourth garbage position output end g4The fifth garbage position output end g5And a sixth garbage position output end g6And a seventh garbage position output end g7(ii) a In the reversible double-edge JK flip-flop, a logic low level is represented by "0", a logic high level is represented by "1", and Q is setnIndicating a flip-flop substate;
in the reversible double-edge JK flip-flop, f1Is connected to an asynchronous set-number enable signal input M, f1And a first logic low level input terminal L1Connection of f1Is connected to the clock signal input C, f1First output terminal and t1Is connected to the first input terminal of f1Second output terminal and first garbage level output terminal g1Connection of f1Third output terminal of (d) and f2Is connected to the first input terminal of f2Second input terminal of and f7Is connected with the second output end of the trigger, and the trigger is in a secondary state QnAt f2And f is a second input terminal7On the second output terminal of (f)2Third input terminal of (d) and f7Is connected to the first output terminal of f2First output terminal and t1Is connected to the second input terminal of f2Second output terminal of and f3Is connected to the second input terminal of f2Third output terminal of (d) and f5Is connected to the second input terminal of f3First input terminal and t1Is connected to the second output terminal of f3Third input terminal of (d) and f4Is connected to the second output terminal of f3First output terminal and f5Is connected to the first input terminal of f3Second output terminal and t2Is connected to the first input terminal of f3Third output terminal and third garbage level output terminal g3Connection of f4First input terminal and t1Is connected to the first output terminal of f4Second input terminal and t2Is connected to the second output terminal of f4Is connected to the preset number input P, f4Is connected with an asynchronous setting enable signal output M', f4Third output terminal and fourth garbage level output terminal g4Connection of f5Third input terminal of and t3Is connected to the second output terminal of f5First output terminal and f6Is connected to the first input terminal of f5Second output terminal and sixth garbage level output terminal g6Connection of f5Third output terminal and t3Is connected to the first input terminal of f6Second input terminal and t2Is connected to the first output terminal of f6Third input terminal of and t3Is connected to the first output terminal of f6First output end and second garbage position output end g2Connection of f6Second output terminal and fifth garbage level output terminal g5Connection of f6Third output terminal and t4Is connected to the first input terminal of f7First input terminal and t4Is connected to the second output terminal of f7Second input terminal and second data input terminal I2Connection of f7Third input terminal of and t5Is connected to the output terminal of f7Third output end and seventh garbage position output end g7Connection, t2And a second logic low level input terminal L2Connection, t3And a third logic low level input terminal L3Connection, t4And a fourth logic low level input terminal L4Connection, t4Is connected with the flip-flop present signal output Q, t5And a first data input terminal I1And (4) connecting.
Inputting an asynchronous reset enable signal SR to an asynchronous reset enable signal input end M, inputting a clock signal clk to a clock signal input end C, and inputting JK flip-flop data K to a first data input end I1Inputting the JK flip-flop data J to the second data input terminal I2Inputting the preset number N to the preset number input terminal P to make the first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3A fourth logic low level input terminal L4Are all connected with logic '0', and the signal output by the current signal output end Q of the trigger is recorded as QCJK；
When the asynchronous set enable signal SR equals to logic '0', i.e. logic low level, f2、f3、f5、f6The input values of the respective first inputs are equal to the clock signals clk, f4Has an input value of logic '0', t5Has an output value of
Figure BDA0002900556150000051
I.e. f7Has an input value of
Figure BDA0002900556150000052
f7The input value of the second input terminal is JK trigger data J, t4Terminates the second input of logic "0" such that t4Is equal to t4Input value Q of the first input terminalCJKI.e. f7The input value of the first input end is a trigger present state signal QCJKThus f is7Output value of the second output terminal of
Figure BDA0002900556150000053
When the clock signal clk is logic "1", i.e. logic high, the clock signal is driven by f3,f4,t2The latch circuit is in data latch state, and the latched data is passed through f6And t4Then output by the trigger present signal output end Q, and JK trigger data K and JK trigger dataJ does not affect the output of the current signal output end Q of the trigger, and f5,t3The latch circuit is in data receiving state, and the received data is Qn，
Figure BDA0002900556150000054
I.e. by f5,t3The latch circuit is configured to actually receive data of
Figure BDA0002900556150000055
When the clock signal clk changes from logic "1" to logic "0", i.e. from logic high to logic low, i.e. the falling edge of the clock signal clk is changed from f5,t3The latch circuit is changed from a data receiving state to a data latching state, and the latched data is equal to the corresponding Q when the clock signal clk is to be changed from logic '1' to logic '0', namely from a logic high level to a logic low levelnA value of (d); when the clock signal clk is logic "0", i.e. logic low, the clock signal is driven by f5,t3The data latched in the latch circuit is passed through f6And t4Then the current state signal of the trigger is output by a signal output end Q, and the change of JK trigger data K and JK trigger data J does not influence the output of the current state signal of the trigger Q, and f3,f4,t2The latch circuit is configured to change from a data latching state to a data receiving state, the received data being Qn，
Figure BDA0002900556150000056
I.e. by f3,f4,t2The latch circuit is configured to actually receive data of
Figure BDA0002900556150000057
When the clock signal clk changes from logic "0" to logic "1", i.e. from a logic low level to a logic high level, i.e. the rising edge of the clock signal clk is changed from f3,f4,t2The latch circuit is configured to change from a data receiving state to a data latching state, the latched data being equal to the clock signal clk about to change from a logic "0" stateQ corresponding to logic "1", i.e. change from logic low level to logic high levelnValue of (f), latched data via6And t4Then the current signal is output by a trigger current signal output end Q; when the clock signal clk is at logic high level, i.e. at logic "1" again, the clock signal is at the logic high level5,t3The latch circuit is changed from the data latch state to the data receiving state again, and receives QnThe function of the double-edge JK trigger is realized; wherein the content of the first and second substances,
Figure BDA0002900556150000061
meaning that a non-logical operation is performed on K,
Figure BDA0002900556150000062
represents a pair QCJKPerforming a non-logical operation;
when the asynchronous set enable signal SR is equal to logic '1', i.e. logic high level, f2The input value of the first input terminal of (1) is kept constant at logic "0", f3,f4,f5,f6The input value of the respective first input terminal remains constant at logic "1", the preset number N being passed through f4Enter from f3,f4,t2The output value of the trigger present state signal output end Q is set to be N; t is t4Is terminated by a logical "0", t4Is equal to t4Is the input value of N, f2Has an input value of logic '0', t4The output value N of the second output terminal of (1) is via f7,f2Enter from f5,t3In the latch circuit constructed so as to be composed of3,f4,t2Latch circuit formed of5,t3The data stored in the formed latch circuit are all N, and the asynchronous number setting function is realized.
Compared with the prior art, the invention has the advantages that:
1) the reversible double-edge JK trigger not only has the function of a double-edge JK trigger, but also can register the preset number into the trigger and output the preset number when the asynchronous number setting enabling signal is effective, and can respectively realize the asynchronous zero clearing or 1 setting of the trigger by changing the value of the preset number, thereby being beneficial to leading the reversible sequential logic circuit to run from a determined initial state or return from an error state to a controllable determined state after the asynchronous number setting.
2) When the reversible double-edge JK trigger is used for forming the reversible sequential logic circuit, the initialization of the reversible sequential logic circuit can be conveniently realized by using an asynchronous number setting enabling signal and a preset number.
Drawings
Fig. 1 is a schematic circuit diagram of a NOT reversible logic gate;
FIG. 2 is a schematic diagram of a circuit structure of a Feynman reversible logic gate;
FIG. 3 is a schematic diagram of a Fredkin reversible logic gate circuit;
FIG. 4 is a schematic circuit diagram of a reversible double-edge JK flip-flop capable of asynchronous setting according to the present invention;
FIG. 5 is a schematic diagram of the circuit configuration of FIG. 4 with the addition of input and output signals;
fig. 6 is a schematic diagram of a simulation result of the functional simulation performed on fig. 5.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The reversible double-edge JK trigger capable of asynchronously setting numbers is characterized by being composed of 1 NOT reversible logical gate, 4 Feynman reversible logical gates and 7 Fredkin reversible logical gates, and the 4 Feynman reversible logical gates are respectively recorded as t1、t2、t3And t4Will t1、t2、t3And t4Respective control input terminal as first input terminal, let t1、t2、t3And t4Respective target input terminal as second input terminal, let t1、t2、t3And t4Respective control output terminal as the first output terminal, and t1、t2、t3And t4Respective target output terminal as second output terminal at t1、t2、t3And t4The output value of the first output end is equal to the input value of the first input end, the output value of the second output end is equal to the logical exclusive OR of the input value of the first input end and the input value of the second input end, and the NOT reversible logic gate is marked as t57 Fredkin reversible logic gates are respectively recorded as f1、f2、f3、f4、f5、f6And f7A 1 is to f1、f2、f3、f4、f5、f6And f7Respective control input terminal as first input terminal, f1、f2、f3、f4、f5、f6And f7Respective first target input terminal as second input terminal, and f1、f2、f3、f4、f5、f6And f7Respective second target input terminal as third input terminal, and f1、f2、f3、f4、f5、f6And f7Respective control output terminal as the first output terminal, and f1、f2、f3、f4、f5、f6And f7Respective first target output terminal as second output terminal, and f1、f2、f3、f4、f5、f6And f7Respective second target output terminal as third output terminal at f1、f2、f3、f4、f5、f6And f7In each case, the output value of the first output terminal is equal to the input value of the first input terminal, the output value of the second output terminal is equal to the input value of the second input terminal and the output value of the third output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "0", the output value of the second output terminal is equal to the input value of the third input terminal and the output value of the third output terminal is equal to the input value of the second input terminal when the input value of the first input terminal is "1". TheThe reversible double-edge JK flip-flop comprises an asynchronous digital enable signal input end M, a clock signal input end C and a first data input end I1A second data input terminal I2A preset number input terminal P, a first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3A fourth logic low level input terminal L4And an asynchronous setting enable signal output end M', a trigger present signal output end Q and a first garbage position output end g1And a second garbage position output end g2And a third garbage position output end g3And a fourth garbage position output end g4The fifth garbage position output end g5And a sixth garbage position output end g6And a seventh garbage position output end g7(ii) a In the reversible double-edge JK flip-flop, a logic low level is represented by "0", a logic high level is represented by "1", and Q is setnIndicating a flip-flop substate. In the reversible double-edge JK flip-flop, f1Is connected to an asynchronous set-number enable signal input M, f1And a first logic low level input terminal L1Connection of f1Is connected to the clock signal input C, f1First output terminal and t1Is connected to the first input terminal of f1Second output terminal and first garbage level output terminal g1Connection of f1Third output terminal of (d) and f2Is connected to the first input terminal of f2Second input terminal of and f7Is connected with the second output end of the trigger, and the trigger is in a secondary state QnAt f2And f is a second input terminal7On the second output terminal of (f)2Third input terminal of (d) and f7Is connected to the first output terminal of f2First output terminal and t1Is connected to the second input terminal of f2Second output terminal of and f3Is connected to the second input terminal of f2Third output terminal of (d) and f5Is connected to the second input terminal of f3First input terminal and t1Is connected to the second output terminal of f3Third input terminal of (d) and f4Is connected to the second output terminal of f3First output terminal and f5Is connected to the first input terminal of f3Second output terminal and t2Is connected to the first input terminal of f3Third output terminal and third garbage level output terminal g3Connection of f4First input terminal and t1Is connected to the first output terminal of f4Second input terminal and t2Is connected to the second output terminal of f4Is connected to the preset number input P, f4Is connected with an asynchronous setting enable signal output M', f4Third output terminal and fourth garbage level output terminal g4Connection of f5Third input terminal of and t3Is connected to the second output terminal of f5First output terminal and f6Is connected to the first input terminal of f5Second output terminal and sixth garbage level output terminal g6Connection of f5Third output terminal and t3Is connected to the first input terminal of f6Second input terminal and t2Is connected to the first output terminal of f6Third input terminal of and t3Is connected to the first output terminal of f6First output end and second garbage position output end g2Connection of f6Second output terminal and fifth garbage level output terminal g5Connection of f6Third output terminal and t4Is connected to the first input terminal of f7First input terminal and t4Is connected to the second output terminal of f7Second input terminal and second data input terminal I2Connection of f7Third input terminal of and t5Is connected to the output terminal of f7Third output end and seventh garbage position output end g7Connection, t2And a second logic low level input terminal L2Connection, t3And a third logic low level input terminal L3Connection, t4And a fourth logic low level input terminal L4Connection, t4Is connected with the flip-flop present signal output Q, t5And a first data input terminal I1And (4) connecting.
FIG. 5 is a schematic diagram of the circuit configuration of FIG. 4 with the addition of input and output signalsInputting an asynchronous setting enable signal SR to an asynchronous setting enable signal input end M, inputting a clock signal clk to a clock signal input end C, and inputting JK flip-flop data K to a first data input end I1Inputting the JK flip-flop data J to the second data input terminal I2Inputting the preset number N to the preset number input terminal P to make the first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3A fourth logic low level input terminal L4Are all connected with logic '0', and the signal output by the current signal output end Q of the trigger is recorded as QCJK。
When the asynchronous set enable signal SR equals to logic '0', i.e. logic low level, f2、f3、f5、f6The input values of the respective first inputs are equal to the clock signals clk, f4Has an input value of logic '0', t5Has an output value of
Figure BDA0002900556150000091
I.e. f7Has an input value of
Figure BDA0002900556150000092
f7The input value of the second input terminal is JK trigger data J, t4Terminates the second input of logic "0" such that t4Is equal to t4Input value Q of the first input terminalCJKI.e. f7The input value of the first input end is a trigger present state signal QCJKThus f is7Output value of the second output terminal of
Figure BDA0002900556150000093
When the clock signal clk is logic "1", i.e. logic high, the clock signal is driven by f3,f4,t2The latch circuit is in data latch state, and the latched data is passed through f6And t4Then output by the trigger present signal output end Q, and the change of the JK trigger data K and the JK trigger data J can not influence the triggerThe output of the state signal output terminal Q is found by the generator5,t3The latch circuit is in data receiving state, and the received data is Qn，
Figure BDA0002900556150000094
I.e. by f5,t3The latch circuit is configured to actually receive data of
Figure BDA0002900556150000095
When the clock signal clk changes from logic "1" to logic "0", i.e. from logic high to logic low, i.e. the falling edge of the clock signal clk is changed from f5,t3The latch circuit is changed from a data receiving state to a data latching state, and the latched data is equal to the corresponding Q when the clock signal clk is to be changed from logic '1' to logic '0', namely from a logic high level to a logic low levelnA value of (d); when the clock signal clk is logic "0", i.e. logic low, the clock signal is driven by f5,t3The data latched in the latch circuit is passed through f6And t4Then the current state signal of the trigger is output by a signal output end Q, and the change of JK trigger data K and JK trigger data J does not influence the output of the current state signal of the trigger Q, and f3,f4,t2The latch circuit is configured to change from a data latching state to a data receiving state, the received data being Qn，
Figure BDA0002900556150000101
I.e. by f3,f4,t2The latch circuit is configured to actually receive data of
Figure BDA0002900556150000102
When the clock signal clk changes from logic "0" to logic "1", i.e. from a logic low level to a logic high level, i.e. the rising edge of the clock signal clk is changed from f3,f4,t2The latch circuit is configured to change from a data receiving state to a data latching state, the latched data being equal to the clock signal clk going from a logic "0" to a logic "1" and going from logicQ corresponding to change from low level to logic high levelnValue of (f), latched data via6And t4Then the current signal is output by a trigger current signal output end Q; when the clock signal clk is at logic high level, i.e. at logic "1" again, the clock signal is at the logic high level5,t3The latch circuit is changed from the data latch state to the data receiving state again, and receives QnA change in (c); wherein the content of the first and second substances,
Figure BDA0002900556150000103
meaning that a non-logical operation is performed on K,
Figure BDA0002900556150000104
represents a pair QCJKPerforming a non-logical operation; from the above analysis, when the asynchronous set enable signal SR is equal to logic "0", i.e. logic low level, the proposed flip-flop has a double-edge triggering function, and when the clock signal clk changes from logic "1" to logic "0", i.e. from logic high level to logic low level, or from logic "0" to logic "1", i.e. from logic low level to logic high level, Q is assertedCJKIs equal to QnAnd is and
Figure BDA0002900556150000105
and thus has a double-edge JK flip-flop function.
When the asynchronous set enable signal SR is equal to logic '1', i.e. logic high, no matter how the clock signal clk transitions, f2The input value of the first input terminal of (1) is kept constant at logic "0", f3,f4,f5,f6The input value of the respective first input terminal remains constant at logic "1", the preset number N being passed through f4Enter from f3,f4,t2The output value of the trigger present state signal output end Q is set to be N; t is t4Is terminated by a logical "0", t4Is equal to t4Is the input value of N, f2Has an input value of logic '0', t4Second output of (2)The output value N of the terminal is f7,f2Enter from f5,t3In the latch circuit constructed so as to be composed of3,f4,t2Latch circuit formed of5,t3The data stored in the latch circuit is N; due to f is formed by3,f4,t2Latch circuit formed of5,t3All data stored in the latch circuit are N, so when the asynchronous reset enable signal SR changes from "1" to "0", the output value of the flip-flop present signal output end Q is N no matter the clock signal clk is high level or low level, until the clock signal clk makes a transition. From the above analysis, the proposed flip-flop has an asynchronous set-up function.
The reversible double-edge JK trigger capable of asynchronously setting numbers is subjected to a function simulation experiment.
After modeling the circuit behavior of the NOT reversible logic gate, Feynman reversible logic gate, and Fredkin reversible logic gate in verilog hdl language, the circuit shown in fig. 5 was subjected to functional simulation, the functional simulation result is shown in fig. 6, and as can be seen from fig. 6, Q isCJKThe logic functions of the asynchronous set number enable signal SR, the preset number N, the clock signal clk and the JK trigger data J, JK are consistent with the logic functions of the asynchronous set number reversible double-edge JK trigger. Since the simulation software does not support subscripted signal names, signal QCJK in FIG. 6 corresponds to Q in FIG. 5CJK。

Claims (2)

1. A reversible double-edge JK trigger capable of asynchronously setting numbers is characterized by being composed of 1 NOT reversible logic gate, 4 Feynman reversible logic gates and 7 Fredkin reversible logic gates, wherein the 4 Feynman reversible logic gates are respectively marked as t1、t2、t3And t4Will t1、t2、t3And t4Respective control input terminal as first input terminal, let t1、t2、t3And t4Respective target input terminal as second input terminal, let t1、t2、t3And t4Respective control output terminal as the first output terminal, and t1、t2、t3And t4Respective target output terminal as second output terminal at t1、t2、t3And t4The output value of the first output end is equal to the input value of the first input end, the output value of the second output end is equal to the logical exclusive OR of the input value of the first input end and the input value of the second input end, and the NOT reversible logic gate is marked as t57 Fredkin reversible logic gates are respectively recorded as f1、f2、f3、f4、f5、f6And f7A 1 is to f1、f2、f3、f4、f5、f6And f7Respective control input terminal as first input terminal, f1、f2、f3、f4、f5、f6And f7Respective first target input terminal as second input terminal, and f1、f2、f3、f4、f5、f6And f7Respective second target input terminal as third input terminal, and f1、f2、f3、f4、f5、f6And f7Respective control output terminal as the first output terminal, and f1、f2、f3、f4、f5、f6And f7Respective first target output terminal as second output terminal, and f1、f2、f3、f4、f5、f6And f7Respective second target output terminal as third output terminal at f1、f2、f3、f4、f5、f6And f7In each case, the output value of the first output terminal is equal to the input value of the first input terminal, the output value of the second output terminal is equal to the input value of the second input terminal and the output value of the third output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "0", and the output value of the second output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "1The input value of the input end and the output value of the third output end are equal to the input value of the second input end;
the reversible double-edge JK flip-flop comprises an asynchronous digital enable signal input end M, a clock signal input end C and a first data input end I1A second data input terminal I2A preset number input terminal P, a first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3A fourth logic low level input terminal L4And an asynchronous setting enable signal output end M', a trigger present signal output end Q and a first garbage position output end g1And a second garbage position output end g2And a third garbage position output end g3And a fourth garbage position output end g4The fifth garbage position output end g5And a sixth garbage position output end g6And a seventh garbage position output end g7(ii) a In the reversible double-edge JK flip-flop, a logic low level is represented by "0", a logic high level is represented by "1", and Q is setnIndicating a flip-flop substate;
in the reversible double-edge JK flip-flop, f1Is connected to an asynchronous set-number enable signal input M, f1And a first logic low level input terminal L1Connection of f1Is connected to the clock signal input C, f1First output terminal and t1Is connected to the first input terminal of f1Second output terminal and first garbage level output terminal g1Connection of f1Third output terminal of (d) and f2Is connected to the first input terminal of f2Second input terminal of and f7Is connected with the second output end of the trigger, and the trigger is in a secondary state QnAt f2And f is a second input terminal7On the second output terminal of (f)2Third input terminal of (d) and f7Is connected to the first output terminal of f2First output terminal and t1Is connected to the second input terminal of f2Second output terminal of and f3Is connected to the second input terminal of f2Third output terminal of (d) and f5Is connected to the second input terminal of f3First input terminal and t1Is connected to the second output terminal of f3Third input terminal of (d) and f4Is connected to the second output terminal of f3First output terminal and f5Is connected to the first input terminal of f3Second output terminal and t2Is connected to the first input terminal of f3Third output terminal and third garbage level output terminal g3Connection of f4First input terminal and t1Is connected to the first output terminal of f4Second input terminal and t2Is connected to the second output terminal of f4Is connected to the preset number input P, f4Is connected with an asynchronous setting enable signal output M', f4Third output terminal and fourth garbage level output terminal g4Connection of f5Third input terminal of and t3Is connected to the second output terminal of f5First output terminal and f6Is connected to the first input terminal of f5Second output terminal and sixth garbage level output terminal g6Connection of f5Third output terminal and t3Is connected to the first input terminal of f6Second input terminal and t2Is connected to the first output terminal of f6Third input terminal of and t3Is connected to the first output terminal of f6First output end and second garbage position output end g2Connection of f6Second output terminal and fifth garbage level output terminal g5Connection of f6Third output terminal and t4Is connected to the first input terminal of f7First input terminal and t4Is connected to the second output terminal of f7Second input terminal and second data input terminal I2Connection of f7Third input terminal of and t5Is connected to the output terminal of f7Third output end and seventh garbage position output end g7Connection, t2And a second logic low level input terminal L2Connection, t3And a third logic low level input terminal L3Connection, t4And a fourth logic low level input terminal L4Connection, t4Is connected with the flip-flop present signal output Q, t5Input terminal and the secondA data input terminal I1And (4) connecting.
2. The reversible double-edge JK flip-flop with asynchronous setting function as claimed in claim 1, wherein the asynchronous setting enable signal SR is inputted to the asynchronous setting enable signal input terminal M, the clock signal clk is inputted to the clock signal input terminal C, and the JK flip-flop data K is inputted to the first data input terminal I1Inputting the JK flip-flop data J to the second data input terminal I2Inputting the preset number N to the preset number input terminal P to make the first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3A fourth logic low level input terminal L4Are all connected with logic '0', and the signal output by the current signal output end Q of the trigger is recorded as QCJK；
When the asynchronous set enable signal SR equals to logic '0', i.e. logic low level, f2、f3、f5、f6The input values of the respective first inputs are equal to the clock signals clk, f4Has an input value of logic '0', t5Has an output value of
Figure FDA0002900556140000031
I.e. f7Has an input value of
Figure FDA0002900556140000032
f7The input value of the second input terminal is JK trigger data J, t4Terminates the second input of logic "0" such that t4Is equal to t4Input value Q of the first input terminalCJKI.e. f7The input value of the first input end is a trigger present state signal QCJKThus f is7Output value of the second output terminal of
Figure FDA0002900556140000033
When the clock signal clk is logic "1", it is logic highWhen is driven by f3,f4,t2The latch circuit is in data latch state, and the latched data is passed through f6And t4Then the current state signal of the trigger is output by a signal output end Q, and the change of JK trigger data K and JK trigger data J does not influence the output of the current state signal of the trigger Q, and f5,t3The latch circuit is in data receiving state, and the received data is Qn，
Figure FDA0002900556140000034
I.e. by f5,t3The latch circuit is configured to actually receive data of
Figure FDA0002900556140000035
When the clock signal clk changes from logic "1" to logic "0", i.e. from logic high to logic low, i.e. the falling edge of the clock signal clk is changed from f5,t3The latch circuit is changed from a data receiving state to a data latching state, and the latched data is equal to the corresponding Q when the clock signal clk is to be changed from logic '1' to logic '0', namely from a logic high level to a logic low levelnA value of (d); when the clock signal clk is logic "0", i.e. logic low, the clock signal is driven by f5,t3The data latched in the latch circuit is passed through f6And t4Then the current state signal of the trigger is output by a signal output end Q, and the change of JK trigger data K and JK trigger data J does not influence the output of the current state signal of the trigger Q, and f3,f4,t2The latch circuit is configured to change from a data latching state to a data receiving state, the received data being Qn，
Figure FDA0002900556140000036
I.e. by f3,f4,t2The latch circuit is configured to actually receive data of
Figure FDA0002900556140000041
When the clock signal clk is slaveWhen the "0" changes to the logic "1", i.e. from the logic low level to the logic high level, i.e. the rising edge of the clock signal clk, the signal goes from f3,f4,t2The latch circuit is changed from a data receiving state to a data latching state, and the latched data is equal to the corresponding Q when the clock signal clk is to be changed from logic '0' to logic '1', namely from a logic low level to a logic high levelnValue of (f), latched data via6And t4Then the current signal is output by a trigger current signal output end Q; when the clock signal clk is at logic high level, i.e. at logic "1" again, the clock signal is at the logic high level5,t3The latch circuit is changed from the data latch state to the data receiving state again, and receives QnThe function of the double-edge JK trigger is realized; wherein the content of the first and second substances,
Figure FDA0002900556140000042
meaning that a non-logical operation is performed on K,
Figure FDA0002900556140000043
represents a pair QCJKPerforming a non-logical operation;
when the asynchronous set enable signal SR is equal to logic '1', i.e. logic high level, f2The input value of the first input terminal of (1) is kept constant at logic "0", f3,f4,f5,f6The input value of the respective first input terminal remains constant at logic "1", the preset number N being passed through f4Enter from f3,f4,t2The output value of the trigger present state signal output end Q is set to be N; t is t4Is terminated by a logical "0", t4Is equal to t4Is the input value of N, f2Has an input value of logic '0', t4The output value N of the second output terminal of (1) is via f7,f2Enter from f5,t3In the latch circuit constructed so as to be composed of3,f4,t2Latch circuit formed of5,t3The data stored in the formed latch circuit are all N, and the asynchronous number setting function is realized.
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