TWI223272B - Teacher-pupil flip-flop - Google Patents

Abstract

A teacher-pupil flip-flop with reduced register delay including a gate circuit, a stack circuit, a keeper circuit, a teacher output circuit, a latch circuit and a pupil output circuit. The gate circuit switches after a setup delay in response to transitions of a clock signal. The stack circuit, coupled to the gate circuit output and to an input, switches an intermediate node pair to a preliminary state when the clock signal is low, and to a data state indicative of the input after the setup delay when the clock signal goes high. The keeper circuit maintains the data state and the teacher output circuit drives the output based on the data state while the clock is high. The latch circuit stores the data state and the pupil output circuit drives the output with valid data from the latch circuit after the clock signal goes low.

Description

1223272 V. Description of the invention (1) The present invention claims the priority of US patent application 10/6 1 6, 4 7 3, which is July 9, 2003, and the entirety of the US patent application is incorporated herein. The invention is incorporated by reference. [Technical field to which the invention belongs] The present invention relates to a data flip-flop which can be used for a data register of a pipeline stage, and in particular, a master-student flip-flop, which is a master-student flip-flop Significantly reduces the register delay time, thereby increasing the work that can be performed during each cycle of the pipeline 1 ineddevice. [Prior Art] FIG. 1 is a block diagram showing a relationship between a register delay and a working interval in a pipelined component 100, which has a conventional D-type flip-flop 105, 106 and 107 separated consecutive stages. As shown in the figure, the first segment 10 (N segment) including the pipeline segment logic circuit 102 is coupled to the second segment 103 (N + 1 segment) including the pipeline segment logic circuit 104. Obviously, more sections may be included, for example, several previous sections before section 101 and several subsequent sections after section 103. When the clock signal Clk changes, the data is passed from the & section to the next section. The usual method is to transfer the output of one segment to the input of the next segment through a data register. Each register contains three or more D-type flip-flops. Each D-type flip-flop processes a data bit and includes a clock input terminal for receiving a CLK signal. & As shown in FIG. 1, the first D-type flip-flop 105 receives the data signal X at its D input terminal, and provides a temporarily registered version, (registered version), or data signal of the X signal at its Q output terminal. rx. ]) Type flip-flop 105

11823twf.ptd Page 6 1223272 V. Description of the Invention (2) It may include an inverting output terminal QB ′, which provides an inverted version of the RX signal at its QB output terminal, or RXB. Add the letter π B " to the name of the signal or input / output (I / 〇) to indicate a complementary signal with an inverted or opposite logic state. The RXA and RXB signals are supplied to the pipeline logic circuit 102, and an output signal Y is formed therefrom. The signal γ is supplied to the D input terminal of the second D-type flip-flop 106 between segment 101 and 103, and is generated by the D-type flip-flop 106 at its Q and QB outputs, respectively. Signal ry and signal RYB. The RY signal and the RYB signal are processed by the pipeline logic circuit 104, thereby generating an output signal Z to be supplied to the d input terminal of the third D-type flip-flop 107. The D-type flip-flop 107 generates a signal and a signal RZB at its Q and QB outputs, and so on. Once the CLK signal is converted, a signal on the D input of the D flip-flop before the clock conversion is latched at the Q and QB outputs of the D flip-flop. As the register transfers data from one segment to the next, it takes a finite amount of time called the REGISTER DELAY. As shown in the figure, each D-type flip-flop 105-107 has a register delay when transferring data between segments. The C L K signal determines the total amount of time available for each clock cycle. During each CLK signal cycle, each pipeline segment logic circuit including pipeline segment circuits 1 02 and 104 pipeline elements 1 and 0 4 performs a variety of functions. However, during the register delay period, the pipeline logic can perform any function. The time spent performing useful work during each clock cycle is called WORK INTERVAL, which is equal to the & period time of CLK minus the register delay. Therefore, pipelined components 100 are limited by the register delay required during the LK signal cycle.

1223272 V. Description of the invention (3) Figure 2 is a schematic diagram showing a master-slave D flip-flop 200 of the existing (traditional) technology, which can represent the D-type Any of the flip-flops 105-107. The master-slave D flip-flop 2000 is characterized by having two substantially identical stages, including a master stage 201 and a slave stage 203 thereafter. The main section 201 includes a complementary pass gate 205 and a pair of inverters 207 and 209. The slave section 203 also includes a complementary transmission gate 2 1 1 and a pair of inverters 2 1 3 and 2 1 5. The complementary transmission gate 205 is composed of a P-channel element pi and an N-channel element N1, where

The source of P1 is connected to the drain of N1, and the source of N1 is connected to the drain of P1. The D input terminal is formed at the connection point between the source of p 1 and the drain of N 1. The connection point between the drain of p 1 and the source of N 1 is connected to the input of inverter 207 and the output of inverter 209. The output terminal of the inverter 207 is connected to the input terminal of the inverter 209 and forms an input terminal from the segment 203]). The complementary transmission gate 2 丨 1 is composed of a p_channel element p2 and an N_channel element N2 which are connected to each other, and its engagement is the same as that of P1 * N1. The connection point of the source of p2 of the transmission gate with the and terminals of ... forms a DI input. The connection f of the source of N2 to the drain of P2 is connected to the input of inverter 2 1 3 and the output of inverter 2 1 5. The Q output terminal of the f inverter 200 is formed at the output terminal of the inverter 213, and the input terminal of the inverter 2 1 5 is connected. g η λ λ inverse / purpose (〇PP〇Si te) clock signals CLK and CLKB drive D-type positive% Ι Μ ^^^. In particular, the CLK signal is supplied to the gates of P1 and ″, and the input signal is supplied to the gates of P2 and N1. When CLK is low, the lean material on the D output is passed through the complementary pass gate 205. And master inverter

The eighteenth 1223272 V. Description of the invention (4) inverter) 207 transmission, and is set at the DI input of the complementary transmission gate 211 of the slave 203. The inverter 209 operates together with the inverter 207 as a holding circuit for latching data. When the CLK signal rises, the complementary transmission gate 205 is closed and the complementary transmission gate 2 1 1 is opened, so that data can flow to the Q output terminal via the complementary transmission gate 2 1 1 and from the inverter 2 1 3. Inverter 2 1 5 operates together with inverter 2 1 3 as a holding circuit that latches data at the Q output. The amount of time it takes for the D input to flow through the main segment 201 is called the set time, and the amount of time it takes for the output of the main segment 20i to flow from segment 230 to the output Q is called the clock to output End (CLOCK-TO-OUTUP) time. When the master-slave D-type flip-flop 200 is used as the pipeline-type element 1 0 0's D-type flip-flop 1 0 5-1 0 7, the setting and CLOCK-TO-OUTPUT time are the master-slave D-type flip-flop 2 0 0 register delay. FIG. 3 is a timing chart showing the setting of the CLK signal and the CLOCK-TO-OUTPUT of the master-slave D-type flip-flop 200 corresponding to FIG. 2. The states of the CLK signal, the D input node and the Q output node are displayed as being distributed along the vertical or γ axis, and the corresponding time is indicated along the horizontal or X axis. As shown, continuous data values DATAl and DATA2 are held in the D input section

Point. Before the rising edge of C L K at time T 1 3 0 1, the value of DATA1 applied to the D input node must flow through the master section 201 to the transmission gate 21 1 of the slave section 203. In this way, the minimum time required for the value of DATA1 to flow through the main section 20 1 is displayed as the set time between time T 0 and time T 1. The D A T A 1 value must be valid at the D input node before the set time at time τ 0 begins. The logic circuit of the pipeline section in the previous section must have completed its work and provided the value of DATA1 to the D output terminal before time τ 〇, so that the master-slave d-type flip-flop 200

11823twf.ptd Page 9 1223272 V. Description of the invention (5) The required setting time is satisfied. Similarly, during the CL 0 CK-T 0-0 UTPUT time from time T 1 to time T 2, after the clock rising edge 3 0 1, the value of DATA 1 flows from segment 2 0 to the Q output. The segment time is also called the output propagation time. The value of DATA1 on the Q output node is invalid before the end of the propagation time at the output. This time is the amount of time required for the value of DATA1 to flow through the complementary transmission gate 211 and inverter 21 3 of segment 203. The logic circuit of the pipeline section in the next section can only work after the end of the transmission day at the output end to ensure the processing of valid data. At present, in the prior art, the CLK cycle time is approximately 0. 5-1. 0 nanoseconds (ns). The delay time of a conventional traditional register such as a traditional register using a master-slave D flip-flop 2000 is approximately It is 100 picoseconds (p S), and the delay time is set between an average of eight and the CLOCK-TO-OUTPUT time. Knife-From the above discussion in conjunction with Figures 1-3, it can be seen that reducing the number of registers allows the logic circuits in the pipeline section to handle more work. χ-1 force and surface, IS $ 1 ?! Reducing the register delay between segments can improve the overall working speed of pipelined components including pipelined element H. Within

Banik U.S. Patent No. 1,185,656,962 " Bundler Circuitry "discloses a master-slave flip-flop circuit 400 whose tone is shown in the forward-backward view-Figure 4. The master-slave flip-flop circuit 4 〇〇 By providing a solid solution to the problem of register delay, thereby significantly shortening the segment 4 0 5

CLOCK-TO-OUTPUT time. The master-slave flip-flop circuit 400 is similar to the master-flip-flop 200, and also includes a same master segment 400 J and its type F403. Slave segment 4 0 3 is similar to slave segment 2 0 3, but it adds an insertion / slave segment before an inverter 40 7 and a complementary transmission gate 409Q input = 1 million points.

I223272, description of the invention (6) ----- Mutual 5 偟 includes an inverted 4U, which has an input terminal connected to the main section 401, an intermediate node between the transmission gate and the inverter, and an Connected to the output of one end of the end compensation transmission gate 413. The other% of the complementary transfer gate 413 is connected to the < 3 output node.丄 The bypass stage 405's main function is to bypass the slave segment 403 when the CLK signal rises two times, so that the CLOCK-TO-OUTPUT time and the delay time of the transmission gate 41 3 through the t segment 4 0 5 equal. When the CLK signal is high, the data value applied to the D input node is latched from segment 403. When the CLK signal is low, the Q output is driven from segment 403. The master-slave flip-flop circuit 400 has a set time equivalent to that of a conventional master-slave flip-flop circuit 2000, and has a shortened C L 0 C K-T 0-0 U T P U T time. For example, referring to Figure 3, after the rising edge of 300, the output data on the q output node will be validated relatively quickly, thereby reducing the total register delay. The master-slave flip-flop circuit 400 may be quite useful for certain operations where CLOCK-T0-0UTPUT time is a key factor.

Although the master-slave flip-flop circuit 400 has a shortened C L 0 C K _ T 0-0 U T P U T time, it is obtained at the cost of increasing the area and energy consumption of the component. Note that, for example, the master-slave flip-flop circuit 4 0 0 drives its output through complementary transmission gates 409 and 413. Fig. 5 is a schematic diagram of a typical output circuit 500 that can be used by the master-slave flip-flop circuit 400. An input signal is supplied to complementary elements P and N connected in series between the voltage source VDD and ground. The node between the elements p and N is connected to one end 'of the complementary transmission gate 5 0 1 and the other end thereof drives an output signal. Those of ordinary skill in the art should understand the driving strength and width of a component

11823twf.ptd Page 11 1223272 V. Description of the invention (7) It is linearly proportional and inversely proportional to the length of the component. Driving an output through a transmission gate undoubtedly doubles the length of the output element. Therefore, in order to drive the same load as a conventional D-type flip-flop such as the master-slave flip-flop circuit 4 0 0, the width of the inverters 4 0 7 and 4 1 1 of the master-slave flip-flop circuit 4 0 0 It must be doubled so that the size of each output inverter is four times larger. In addition, since the master-slave flip-flop 400 has two output inverters, this will significantly increase the overall size of each flip-flop of each register of each pipeline segment 100. In practical applications, the cost of the master-slave flip-flop circuit 400 is quite expensive due to size and power consumption issues. Therefore, it is necessary to provide a register component that can reduce the register delay time without significantly increasing its components and power consumption. [Summary of the Invention] The master and apprentice type flip-flop according to the embodiment of the present invention includes a teacher circuit and a auxiliary circuit. The main circuit includes a gate circuit, a stack circuit, a keeper circuit, and a teacher output circuit. The auxiliary circuit includes a latch circuit and a pump output circuit. The gate circuit has an output terminal and several input terminals connected to an intermediate node pair, and receives a clock signal. After a set delay (s e t u p d e 1 a y), the gate circuit switches to respond to the transition of the clock signal between the first state and the second state. The stack circuit connects the output of the gate circuit with an input data node. When the clock signal transitions to the first state after the set delay, the intermediate node pair is switched to the standby state (p r e 1 i m i n a r y

11823twf.ptd Page 12 1223272 V. Description of the invention (8) s t a t e); When the clock signal is switched to the second state after the delay is set, the intermediate node pair is switched to the data state representing the input data node. Keep the circuit connected to the intermediate node pair. The main output circuit drives an output node representing the data status of the intermediate node pair. The latch circuit stores the data status of the intermediate node pair. The auxiliary output circuit drives the output node representing the data state after the clock signal is switched to the first state. In one embodiment, the intermediate node pair includes a pull-up node and a pull-down node, and the stack circuit includes a first stack circuit connected to the pull-down node and a pull-up node. Second stack circuit. The first stack circuit drives the pull-down node to decrease during the standby state. If the input data node decreases when the set time delay expires, the first stack circuit drives the pull-down node to increase during the data state. The second stack circuit drives the pull-up node to rise during the standby state. If the input data node rises when the set time delay expires, the second stack circuit drives the pull-up node to decrease during the data state. In the embodiments, existing descriptions of existing elements may be used. For example, the gate circuit may include a NAND gate and a NOR gate. The rest can be implemented with standard-sized inverters and complementary periods such as N-channel and P-channel components. A register of an embodiment of the present invention includes: first and second gate circuits, first and second stack circuits, first and second holding circuits, first and second output circuits, and a storage circuit. ). The first gate circuit has a first input terminal for receiving a clock signal, a second input terminal connected to a pull-up node, and an output terminal. Second brake circuit

11823twf.ptd Page 13 1223272 V. Description of the invention (9) There are: a first input terminal for receiving an inverted clock signal, a second input terminal connected to a pull-down node, and an output terminal. The first stack circuit has a first input terminal connected to the output terminal of the first gate circuit, a second input terminal connected to the data input terminal, and an output terminal connected to the pull-down node. The second stack circuit has a first input terminal connected to the output terminal of the second gate circuit, a second input terminal connected to the data input terminal, and an output terminal connected to the pull-up node. The first holding circuit is connected to the pull-down node, and the second holding circuit is connected to the pull-up node. The first output circuit includes a complementary element having an input terminal connected to the pull-down node and the pull-up node and an output terminal connected to the output node. The memory circuit has a first input terminal connected to the pull-down node, a second input terminal connected to the pull-up node, and at least one storage node. The second output circuit receives a clock signal and an inverted clock signal, has an input terminal connected to a storage node of the storage circuit, and has a complementary output element connected to the output node. A register of another embodiment of the present invention includes a gate circuit, a stack circuit, a holding circuit, an output circuit, and an auxiliary circuit. The gate circuit has first and second outputs in response to a plurality of input switches after a delay. The stacked circuit has first and second input terminals connected to the output terminals of the gate circuit, a third input terminal connected to the data input terminal, and first and second output terminals connected to the first and second intermediate nodes. The gate circuit and the stack circuit are operated to toggle the intermediate node. When the clock signal is low after the delay, the intermediate node is switched to an initial state (initia 1 state), and after the delay, When the pulse signal goes high, make

11823twf.ptd Page 14 1223272 V. Description of the invention (ίο) The intermediate node switches to the data state representing the data input. The holding circuit latches the data state of the intermediate node. The output circuit uses valid data to drive an output node when the intermediate node is in the data state. The auxiliary circuit stores the data state of the intermediate node and uses a valid data to drive the output node when the clock signal is low. The register implemented by the master and apprentice flip-flops in the embodiments of the present invention can reduce the temporary register delay. The clock-to-output time, which is the collective delay through the input gate circuit, the stack circuit, and the main output circuit, is comparable to a traditional register. However, the set time is negative because the data value applied to the input may change during the set delay time through the gate circuit. The resulting register delay is simply the delay via the stack and output circuits during each clock cycle. Even if the negative set time causes the clock-to-output time to become longer, the register delay time will be greatly reduced. Standard size components can be used to avoid cost increase due to increased component area and energy consumption. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in cooperation The drawings are described in detail as follows: [Embodiment] The following description is made to enable those skilled in the art to make and use the present invention within the scope of a specific application and its requirements. However, it will be apparent to those skilled in the art that various modifications to the embodiments can be made, and the basic principle explained herein can also be applied to other embodiments. Therefore, the present invention is by no means limited to the embodiments presented here, but

11823twf.ptd Page 15 1223272 V. Description of the Invention (11) is the broadest scope applicable to the principles and novel features disclosed herein. The inventors of the present case realized that during each clock cycle of a pipelined element, it is necessary to significantly reduce the delay in order to maximize the effective working area. The inventors of the present case also realized that it is very necessary to increase the cycle time available for performing work without increasing the component area and power consumption. In view of this, as will be described in detail with reference to FIGS. 6 to 8 below, the inventor of this case has developed a master-student flip-flop circuit that can be used for pipelined components, which can be effective in each time period. The working area is maximized, and the circuit can be manufactured with traditional-sized components to avoid increasing manufacturing costs. FIG. 6 is a block diagram showing the relationship between the delay of the register and the working interval in the pipeline element 6 0 0. The continuous segment of the element is a master-student flip-flop 6 0 1, 6 0 of the preferred embodiment of the present invention. 2 and 6 0 3 separated. The pipeline type component 6 0 0 is similar to the pipeline component 1 0 0, so the number of similar components has not changed. The difference is that the traditional D-type flip-flops 1 0 5, 1 0 6, 1 0 7 Replaced by master and apprentice flip-flops 6 0 1, 6 0 2 and 6 0 3. As detailed below, the register delays of master and apprentice flip-flops 601, 602, and 603 are significant compared to the register delays of conventional D-type flip-flops 105, 106, and 107. The ground is shortened, so the working interval of each section is significantly lengthened. FIG. 7 is a schematic diagram of a master-apprentice type flip-flop 7 0 0 according to a preferred embodiment of the present invention. The shown flip-flop can be used as any of the master-apprentice type flip-flops 601, 602, and 603 shown in FIG. . The master and apprentice flip-flop 700 is a register. Its CLOCK-TO-OUTPUT time is about the same as or slightly longer than a conventional register such as the master-slave flip-flop 200, but its setting time is negative. (Ie less than zero

11823twf.ptd Page 16 1223272 5. Description of the invention (12)) ° A negative setting time means that after the CLK signal is converted, the input data value can still be changed, and at the same time, the edge of the CLK signal is still forwarded through the input terminal components. . Therefore, the signal value at the input does not need to be valid until a considerable amount of time after the CLK transition (that is, the CLK edge is raised): In this way, the 'register delay' 〇 and 400 are significantly shortened. In addition, the master and apprentice flip-flop 700 does not drive its Q output through a gate, but uses standard-sized output elements. In a variety of ways, the master and apprentice type flip-flop 700 can be implemented without increasing the size and power consumption, including a main part 701 and an auxiliary part 703. Receiving = 1 input 2 and reverse the gate U1 (NAND), one input terminal f and two output terminals, and the other input terminal is connected to the pull-up node PUP. The end of gate 1 receives the CLKB signal. The other pair of loops is U2 (N0R), which is connected at one input and output-node /: ^ to connect:: ^ festivals ⑽ 'gate of its input element N1 . The PC node is connected to the gate of the P-channel element P1 and an N-pass element N2. The D input node connects the gates of a% channel element P9 and an N-channel channel element P1. P9 = connected / one N-channel element ”and one P-through on the drain of N3. The full N3 of N3 is connected to VDD, its drain is connected to the source of PUP node and VDD, and it is connected to N2 The drain, the source of N2 is grounded. The drain of N1 at point P2 is connected to the source of p1. / F is connected to the source of P1. The drain of P1 is connected to PDN sections P9, N3, and N2 to form a flute -ϋNΐ to form a first stacked circuit 711 , PUP node connection-round ^ stack circuit 713. Connected to VDD, its drain is connected to the gate of the channel component P8, and its source is connected

Connect to the Q round-out node. PDN node connection-output N_ J

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^ = The gate of N4, its source is grounded, its drain is connected, and the vehicle I: 0 1 includes a first holding circuit connected to the PDN node 105 and a holding circuit 7 0 7 of one node. The holding circuit 7 0 5 includes: a number of P-channel elements P3. The input of the inverter R1 is connected to the ipDN node. The holding circuit m includes an inverting electrode J = two pieces N8. The input terminal of the inverter R3 is connected to the pup node, its input is connected to the gate of 8, the source of n 8 is connected to the ground, and the drain is connected to the p u p node. In the auxiliary section 703, the PUP node is connected to a p-channel transmission element.

PaSS device) P7, the PDN node is connected to an N-pass ==, the gate of element N9. The source of P7 is connected to VDD, and the drain is connected to the N9 drain located at the MST of the material storage node. The source of N9 is grounded. The MST node is connected: the input of the inverter R2 and the output of the other inverter ^, and the input of R4 is connected to the output of the inverter R2. The input shape of the output terminal R4 of R2 = the inverted data storage node MSTB, which is used to store the complementary number of the lean value stored on the MST node. Through the elements P7, p9 and the inverter ", R4 forms a storage circuit, that is, the latch circuit 709, which is used to latch and temporarily store the data status of the pup and PDN nodes, which will be described in detail below. The clk signal During the rising edge of, the state of the stored data represents the value of the data applied to the D input " 1

The C L K B signal is supplied to a p-channel element p 6 and an N-gate of the channel element n 7, and the C L K # number is supplied to p-channel element p & and n-the gate of the channel element n β. Is the source of P6 connected to VDD and the drain connected to a feedback pull-up node? The drain of \ 7 at 6? 11 卩. \ 7 和? 4 sources are connected at 8 nodes

11823twf.ptd Page 18 1223272 Description of the invention (14) ^. = The drain is connected to the ground of the drain gate of N6 located at the feedback pull-down section sFBPDN. The FBPUP node is connected to the p_channel output terminal element to VDD, and its terminal is connected to the Q output node. FBPDN ‘the gate of the second output element N5’ has its source grounded and its drain output Lang point. The elements P4—P6 and the elements N5—N7 together form an output circuit 710 ′. When the CLK signal goes low, the Q output node is driven according to a data value stored in the latch circuit ′ 0 9. The NC / PC nodes together form a switching by the input gate circuits U1 and U2 = a preliminary node pair. Through the delay of the input gate circuit U1 / U2, the effective resources provided to the d input node are established. The next day Mori. P D N / P U P Lang points together form an intermediate node pair. Based on the transition of C L K / C L K B to the complementary clock # and the state of the intermediate node pair, the input gate circuits U 1 and U 2 are switched. The intermediate node pair is switched by the stacked circuit 7 丨 713_. When CLK is lowered and CLKB is raised, the preliminary node pair is driven, so that the components P 9 and N 1 are turned on, and the components ρ 9 and N 1 will drive the intermediate point pair to the PUP high and PDN low standby states. When the CLK signal goes high (and the CLKB signal goes low), the intermediate node pair is switched to a 1-bucket-off, the data state represents the set delay of the gate circuits U1 and U2 and the stacked circuit 7 1 1 And the state of the data value applied to the d input node after any delay period of 7 1 3. In particular, when the set delay period expires, if]) input nodes go low, PDN / PUP nodes are driven high, and if]) input nodes go high, PDN / PUP nodes are driven low. During the remainder of the CLK half cycle ^, the output element N 4 or P 8 is turned on 'to drive the q-wheel out node with valid data. The holding circuit 7 0 5 main 7 0 7 maintains the data state of the intermediate node pair, and

1223272 V. Description of the invention (15) The transmission channel element N 9 or P 7 transmits the status of the data to the M S T / M S T B node. When the CLK signal is switched to the low level again, the MSTB node acts on the FBPUP and FBPDN nodes through P4 and N7, so that one of the auxiliary output elements N5 or P5 is delayed by P 4 / Ν 7 and Ν 5 / Ρ 5 , Use valid data to drive the Q output node. When the CLK signal goes low, after the collective delays of the input gate circuits υΐ and U2 and the stacking circuits 711 and 713 expire, the intermediate node pair returns to the standby state, and the output element "and P8 are in a tri-state Fig. 8 is a timing chart showing the setting of the master and apprentice flip-flop 700 shown in Fig. 7 and the CLOCK-TO-OUTPUT time corresponding to the CLK signal. The CLK signal, D, PUP, PDN, MST / MSTB The Q and Q nodes are distributed along the Y axis and their corresponding times are marked along the X axis. When the CLK signal goes low at time T0, the gate U 1 drives the NC node up, and the gate U 2 drives the PC node down. The pulled-up NC node turns on the element ν 1, and then pulls down the PDN node that tri-states the output element ν 4. Pulls down the PC node of element P9 to turn on (turn η) element p9, and then pulls south to make output element ρ 80% The three-state ρ υ P node. In this way, during the period that cl κ goes low, Ν1 keeps N4 to turn off (turn of f), and P9 keeps P8 to turn off. In addition, the CLK and CLKB signals respectively turn on the auxiliary output circuit 7 丨 〇 Components ρ 4 and N7, thus providing MSTB nodes via FBPUP and pBpM nodes The gate of the output element ΐΡ5. During the previous rising edge of the CLK signal, the state of the MST and MSTB nodes is latched to complement the data value applied to the D input node. The value of this data is called 〇ATA 1 value. In this way, if the value of D a T a 丨 decreases) = the input node decreases during the previous rising edge of the CLK signal, the JMST point is latched to a low level, and the MSTB node is stored to a high level

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5. Description of the invention (16) When conducting, make. Similarly, when the output level is determined by the node determined by the timing diagram (via the latch circuit 709), and when the output element "output element P5 is in tri-state. The Q output node is pulled low via N5 if the DATA 1 value is The “Rain level” is when the output element p $ conduction element N5 is in a tri-state, and the Q output node is pulled up via P5. It is shown that the Q output node is a version of the locked mst / mstb DATA1 value at time T0.

When CLK rises at time T1, the auxiliary components "and" are turned off (turn off), and the auxiliary components N6 and P6 are turned on, and the conduction of "and" makes the output components at time T2 (via P6 / N6 and P5 After the delay of / N5), it is cut off (three-state). From time T2, the Q output node is shown in the figure with a shadow. For this period, the output elements P8 / N4 * p5 / N5 are in Three sadnesses. The CLK and CLKB signals are transmitted at the time T 3 via the reverse gate u 1 and the reverse OR gate u 2 and the next data value displayed as the DATA 2 value at this time must be valid. At the time T 3 to the next Between time T 4, the NC and PC nodes turn on the main components p 2 and N 2 respectively, and cut off the components N 1 and P 9. As shown in the figure, the value of d ATA 2 is maintained at the D input node, It is valid at T 3. If the d ATA 2 value is low level, it will turn on P 1 and cut off N 3, and transmit a high level to PDN node at time T4 to turn on N4 and to the next time. At T5, the Q output node is pulled low. If the value of DATA2 is high, N3 is turned on and P1 is turned off. At time T4, a low level is transmitted to the pup node to turn on P8 and turn on The Q output node is pulled high at time T 5. Thus, at time τ 5, the Q output node is driven to the same state as the value of DATA2 held at the D input node at time T3. When the CLK signal goes up, if DATA2 value is low level, then PDN section

11823twf.ptd Page 21 1223272 V. Description of the invention (17) The high level at point (17) will be reverse-locked to the input terminal of the anti-OR gate U 2 to pull down the p c node and cause P9 to turn on and N2 to turn off. P9 keeps the PUP node high, thus keeping P8 disconnected. The high level on the PUP node is fed back to the inverse gate U 1 ′ to keep the N C node low, thereby locking (10 c k) P 2 to the conducting bear and locking N1 to the off state. In a similar manner, if the value of DATA2 is ~ high, the low level of the PUP node is fed back to the input of the inverse gate U1, thereby pulling up the NC node, causing N1 to be turned on and P2 to be turned off. N 1 keeps the PDN node low, thus keeping N 4 disconnected. The low level on the P D Ν node is fed back to the OR gate U2, thereby keeping the PC node high, thereby locking N2 in the on state and locking P9 in the off state. In either case, during the remainder of the high half cycle of the C L K signal in the case of a change in the DATA signal, the holding circuits 705 and 707 will latch the states of the PDN and PUP signals, respectively. If the DATA2 value is at a high level at time T3, both the PUP and PDN nodes are latched in a low state, and if the DATA2 value is at a low level at time T3, both the pup and P D N nodes are locked in a high state. From time τ 4 to time τ 5, the data state of this intermediate node pair is transmitted to the MST lang point via one of the elements p7 or N9, and the state is transmitted to the q output node during approximately the same time period. If the PDN / PUP node is at a high level, the element ㈣ is turned on, and the MST node is pulled down from &. Similarly, if the PDN / PUP node is low, the element P 7 is turned on ' to pull the South MS T node. During the remainder of the high half cycle of the C L K signal, the latch circuit 709 holds the states of the MST and MSTB nodes. At time, the T 6 C L K signal goes low, turning on the elements ρ 4 and N 7. As mentioned earlier, the M s τ β node is transferred to the FNPUP and FBPDN nodes, and after the delays via the elements ρ4 / N7 and Ρ5 / Ν5, the locked state of the DATA2 value via the MSTB node is now in place

11823twf.ptd Page 22 1223272 V. Description of the invention (18) Hai J T 7 is added to the q output node.卩 The state of the output node does not change, but is driven by one of the output elements P5 or N5 according to the locked state of MST / MSTB. At time T8, which is delayed by the gate circuits U1 / U2 and the elements N1 / N9, the PUP and P D N nodes are pulled back to the standby state, thereby tri-stating the output elements p 8 and N 4. Please note 'After the CLK signal changes the set time passed through the input gate circuits u 1 and u 2, the data value held on the D input node will soon be transmitted to Q through the components P 1 / N 3 and N 4 / P 8 Output node. The CLOCK-TO-OUTPUT time from time τ 1 to time T 5 is equal to the delay through the gate circuits u 1 and U2 plus the delay through the first stack circuit 7 11 or the second stack circuit 7 13, plus the delay through the main Delay of output element N 4 or P 8. The total delay time is longer than that of a conventional register (for example, a conventional register using a master-slave D-type flip-flop 2000). However, its set time is negative. A negative settling time thinker allows the data value of the input node at noon D to change after the rising c LK edge, and the period of the set time when the rising edge is passed through the gate circuits U 1 and U 2, that is, Changes from time T1 to time T3. In one embodiment of the invention, the delay from T1 to T3 is about 1000 picoseconds (ps). In this way, the input data value (for example: DATA2) need not be valid before the time τ 3 when the clock of the CLK signal rises. After the elements N 1 / P 2 and N 2 / P 9 are slightly delayed, the state of the input data value is latched by the holding circuits 7 05 and 7 0 7 and then passed to the Q output node via the output element N 4 / P 8. Because the set time is negative, the delay caused by the register is equal to CL 0 C Κ-Τ 0 _ 〇UTPU Τ time minus the set time (or add a negative set time), which is between time Τ 3 to time τ 5 Time with traditional staging

11823twf.ptd Page 23 1223272 V. Description of the invention (19) Compared with the register delay time of the register, this time is very short. Because the register delay time is very short, the effective working time during the mother-clock cycle of the pipeline element using the master-supplier 700 flip-flop is significantly increased, thereby maximizing the total workload performed. The speed of the pipeline-type component or any component using the embodiment of the present invention can be greatly increased. In addition, the conventional element size of the wheel driver can be used to manufacture the master-student flip-flop of each embodiment of the present invention. Another advantage of the master-student flip-flop 700 is that the Q output node is maintained in three states, which can provide a better speed improvement than the traditional circuit that uses ratiometric conversion at its output. As shown in the figure, the delay through the input gate circuits U 1 and U 2 is greater than the delay through the components N7 / P5 or P4 / N5 (for example, time T3 occurs after time T2). _ But the delay through these gate circuits can be shortened, so that time T 3 can be close to time T2, even before time T2. As long as the data value at the D-round Lang point is still valid at time T3, the analysis results are basically the same. The resulting register delay does not change because CLOCK-TO-OUTPUT and the set time change by the same amount. Although the present invention has been described in detail in connection with several embodiments, other changes and other solutions can be made according to the present invention. For example, the polarity of different components can be reversed, and some specific time values can also be changed according to the needs of the technology. Also, although the present invention discloses the application of 'complementary MOS devices including NMOS and PMOS #transistors, etc.' on metal-oxide-semiconductor (MOS) -type devices, the invention can also be applied to analog technology in a similar manner. And topological circuits, such as bipolar elements. Finally, those skilled in the art should understand that they can benefit

1223272 V. Description of the invention (20) Use the principles disclosed in the present invention and the listed embodiments to design a new structure or carry out structural transformation to achieve the purpose of the present invention without departing from the substance and scope of the scope of the patent application of the present invention. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

11823twf.ptd Page 25 1223272 Brief description of the drawing Figure 1 is a block diagram showing the relationship between the delay time of the register in the pipeline element and the working interval. The continuous segment of the pipeline element consists of traditional multiple D-types. Flip-flop separation. Fig. 2 is a schematic diagram showing a conventional master-slave D-type flip-flop in the prior art, which represents any D-type flip-flop in Fig. 1. Fig. 3 is a timing chart showing the setting time and clock-to-output time of the master-slave D-type flip-flop in Fig. 2 corresponding to the CLK signal. Figure 4 is a schematic diagram of a master-slave flip-flop circuit. The shown master-slave flip-flop circuit reduces the register delay time at the cost of increased component cost and power consumption. Figure 5 is a schematic diagram of a typical output circuit used by the master-slave trigger circuit shown in Figure 4. Fig. 6 is a block diagram showing the relationship between the register delay and the working interval in a pipelined component. The continuous segments of the pipelined component shown are separated by a master and apprentice type flip-flop implemented in the preferred embodiment of the present invention. Fig. 7 is a schematic diagram of a master-apprentice type flip-flop according to a preferred embodiment of the present invention. Fig. 8 is a timing chart of the setting time and the clock-to-output time of the master-student flip-flop shown in Fig. 7 corresponding to the CLK signal. [Illustration of Graphical Symbols] 1 0 0, 6 0 0: pipeline type components, 1 0 1: first stage, 1 0 2, 1 0 4 pipeline stage logic circuit, 1 0 3: second stage, 1 0 5, 1 0 6, 1 0 7, 2 0 0: flip-flop,

11823twf.ptd Page 26 1223272 Brief description of the diagram 201 -401: master stage, 2 0 3, 403: slave stage, 2 0 5, 2 1 1, 4 0 9, 4 1 3 , 5 0 1: complementary pass gate, 2 7, 209, 213, 215, 407, 411: inverter, 3 0 1: rising edge, 4 0 0: master-slave flip-flop circuit, 4 0 5: Bypass section '500: Output circuit, 601, 602, 603, 700: Master and apprentice type flip-flop, 7 0 1: Main part, 7 0 3: Auxiliary part, 7 0 5, 7 0 7 : Holding circuit, 709: latch circuit, 71 °: auxiliary output circuit, 711: first stacking circuit, 713: second stacking circuit, CLK: clock signal, D: input node, D 丨: input terminal, FBPUP " Feedback pull-up node, FbpM: Feedback pull-down node, MST: Data storage node, MSTB: Inverted data storage node, N-channel components: N1, n2, ν3, Ν4, Ν5, Ν6, Ν7 Λϊρ 'N 9, N 8 , NC, PC: nodes, Bu channel elements: Pi, P2, P3, P4, P5, P6, p7 po P9, ',, PUP: pull-up node, p D n: pull-down node, R1' R2 'R3, R4 : Inverter Q: output terminal, qb: inverted output , TO, ΤΙ, Τ2, Τ3, T4, T5, T7, T8: time, U1: NAND, U2: NOR gate, VDD: a voltage source,

11823twf.ptd

1223272 The diagram briefly explains X, RX, Z, RZ, RZB, RY, RYB: signals. 11823twf.ptd Page 28

Claims (1)

1223272 6. Application scope 1. A master-apprentice flip-flop, comprising: a main circuit including: a gate circuit having an output terminal and a plurality of input terminals, the input terminals are connected to an intermediate node pair, and After receiving a clock signal, the gate circuit switches after a set delay to respond to the transition of the clock signal between a first state and a second state; a stack circuit connected to the gate circuit output terminal and an input data Node, after the set delay and when the clock signal transitions to the first state, the stack circuit switches the intermediate node pair to a standby state, and after the set delay and when the clock signal transitions to the In the second state, the intermediate node pair is switched to a data state representing the input data node; a holding circuit is connected to the intermediate node pair; and a main output circuit is connected to the intermediate node pair, and the main output A circuit driving an output node representing the data state; and an auxiliary circuit including: a latch circuit connected to the pair of intermediate nodes, the latch circuit storing the intermediate node Point to the data state; and an auxiliary output circuit connected to the latch circuit and receiving the clock signal, the auxiliary output circuit driving the output representing the data state after the clock signal transitions to the first state node. 2. The master-student flip-flop as described in item 1 of the scope of patent application, wherein: the intermediate node pair includes a pull-up node and a pull-down node; and the stacked circuit includes: 11823twf.ptd Page 29 1223272 VI. Patent application scope-a first stack circuit, driving the pull-down node to a low level during the standby state, and during the data state, if the set time delay expires, the input data If the node is at a low level, the pull-down node is driven to a high level; and a second stack circuit drives the pull-up node to a high level during the standby state. During the data state, if the set time delay expires, the The input data node is at a high level, which drives the pull-up node to a low level. 3. The master-student flip-flop as described in item 2 of the patent application scope, wherein the main output circuit further includes: an output P-channel element having a source connected to a voltage source and connected to the pull-up node A gate and a drain connected to the output node; and an output N-channel element with a source connected to ground, a gate connected to the pull-down node and a drain connected to the output node. 4. The master-student flip-flop as described in item 3 of the scope of patent application, wherein the output P-channel element is tri-stated when the pull-up node is high, and wherein the output N-channel element is at This pull-down node is tri-stated when it is low. 5. The master and apprentice type flip-flop according to item 2 of the scope of patent application, wherein the gate circuit includes: a reverse sum gate having a first input terminal for receiving the clock signal, and a gate connected to the pull-up node. A second input terminal and an output terminal connected to the stacked circuit; and an inverting OR gate having a first input for receiving an inverted clock signal 11823twf.ptd Page 30 1223272 6. Scope of patent application Terminal connected to a second input terminal of the pull-down node and an output terminal connected to the stacked circuit. 6. The master-student flip-flop according to item 5 of the scope of patent application, wherein: the first stacked circuit includes: a first stacked P-channel element having a source connected to a voltage source and connected to the inverter And the gate and the drain of the output terminal of the gate; a second stacked P-channel element having a source connected to the drain of the first stacked P-channel element and a source connected to the data input node A gate and a drain connected to the pull-down node; and a first stacked N-channel element having a drain connected to the pull-down node, a gate connected to the output terminal of the anti-gate circuit, and a source grounded And the second stack circuit includes: a third stack P-channel element having a source connected to the voltage source, a gate connected to the output terminal of the NOR gate, and a drain connected to the pull-up node; A second stacked N-channel element having a drain connected to the pull-up node, a gate and a source connected to the data input node; and a third stacked N-channel element having the second stack connected N-channel element of this source Drain, connected to the NOR gate circuit the output terminal of a gate and a source is grounded. 7. The master-student flip-flop as described in item 2 of the patent application scope, wherein the holding circuit includes: 11823twf.ptd Page 31 I223272 / 、, Patent application scope A pull-up and hold circuit 'includes: a first inverter having a / input terminal and an output terminal connected to the intermediate node pull-up node; and The / pull-up N-channel element has a gate connected to the pull-up terminal, a gate connected to the output terminal of the first inverter and a ground p-point, and a source pull-down holding circuit, including: / A second inverter having an input end and a round output end connected to the intermediate pull-down node; and the ι-g pull-down P-channel element in " having a connection to the voltage inverter A = A free terminal of the output terminal and a drain terminal of a source point of Xiyuan. The receiving side section 8. As described in item 2 of the patent application scope, the latch circuit includes: 1 positive and negative, one of the transmission P-channel elements, has a closed pole connected to a thunder and 2 connected to the pull-up node And a source-pole connected to a point where a data is stored, and a first inverter, which is ancient, ground, and ground-source; a terminal and a link-inverted data store, and an input connected to the data storage node -The second inverter, the second is the output terminal of f; and the input terminal and the one connected to the data storage ~ connected to the inverse lean storage node 9. such as applying for a patent if: 第 即 二 = terminal. The master-student flip-flop as described in item 8, 11823twf.ptd Page 32 1223272 6. Scope of patent application The auxiliary output circuit includes: a first P-channel element with a source connected to the voltage source, A gate receiving an inverted clock signal and a drain connected to a feedback pull-up node; a first N-channel element having a drain connected to the feedback pull-up node and receiving the inverted clock signal A gate and a source connected to the inversion data storage node; a second P-channel element having a source connected to the inversion storage node, a gate to receive the clock signal and a feedback connection A pole of the pull-down node; a second N-channel element having a pole connected to the feedback pull-down node, a gate receiving the clock signal and a source of ground; an output P-channel element having A source connected to the voltage source, a gate connected to the feedback pull-up node and a drain connected to the output node; and an output N-channel element having a source connected to ground and connected to a feedback pull-down node Gate and connection A drain of the output node. 10. The master-student flip-flop as described in item 9 of the scope of patent application, wherein the output P-channel element is tri-stated when the feedback pull-up node is high, and the output N-channel element is at The feedback pull-down node is tri-stated when it is low. 1 1. A register comprising: a first gate circuit having a first input terminal for receiving a clock signal, a second input terminal and an output terminal connected to a pull-up node; 11823twf.ptd Page 33 1223272 6. Application scope of patent __ A first input terminal and a second output terminal of a pull stack; a first input terminal, which is connected to an input terminal and a circuit; A round-out of the pull-down node of the round-out node; a coin entry and connection-^-an output of the pull-up node; a loop-in connection and a first holding circuit connected to the drop-down node; a second Keep electricity & connect to the pull-up node; the element is connected to a first output circuit of the endpoint and includes a plurality of complements, with a plurality of outputs connecting the pull-down node and the pull-up node to the output node Terminal; a plurality of round-in terminals and a storage circuit, having a first input and a second input of a first-output connected to the pull-down node and the pull-up node, and at least one storage node number Connection% ί Ding 丨 we give the child and have the right 梏 su, a w1, 1 w /, 1 2 · If the patent application for chromium III Sheng · M words i complementary output element circuit is: 2 The register, wherein the slightly contradictory The gate, the second gate circuit 1 3 · If applied to Zhizhao, Idle outside = Ping is a reverse OR gate. Xi Xi declared that the patent consumes the temporary storage described in item 1 1 of the patent, and Lizhong · violates the stack circuit Including: J feeds and saves, B.T. —It input Λ circuit, receives the clock signal and the inverse clock signal, and one input of a storage node is connected to the P-channel element—a voltage source of 1223272 6 A patent application range pole connected to a gate and a drain of the first gate circuit output terminal; a second P-channel element having a source connected to the drain of the P-channel element and connected to the data input A gate and a drain connected to the pull-down node; and a first N-channel element having a drain connected to the pull-down node, a gate connected to the output of the first gate circuit, and a source grounded Wherein the second stacked circuit includes: a third P-channel element having a source connected to the voltage source, a gate connected to an output terminal of the second gate circuit, and a drain connected to the pull-up node _ A second N-channel element having the pull-up node A drain connected to a gate and a source of the data input terminal; and a third N-channel element having a drain connected to the source of the second N-channel element and connected to the second gate The gate and a source of the ground at the output end of the circuit. 1 4. The register according to item 11 of the scope of patent application, wherein the first output circuit includes: a P-channel element having a voltage source connected A source, a gate connected to the pull-up node and a pole connected to the output node; and an N-channel element having a source connected to ground, a gate and connection to the pull-down node _ point A drain of the output node. 15. The temporary register according to item 11 of the scope of patent application, wherein the storage circuit includes: 11823twf.ptd Page 35 1223272 A third p-channel element, which has a source connected to the voltage source, a two-pole element, a pole connected to the output electrode, and the output section 1223272 6. Application for a patent scope A third N-channel element, which has a grounded one A source, a gate connected to the drain of the second P-channel element and a drain connected to the output node. 1 7. A register including: a gate circuit having a plurality of input terminals Receiving a clock signal and connecting to a first intermediate node and a second intermediate node, and having a first output terminal and a second output terminal, which are switched to respond to the input terminals after a delay; a stack circuit, A first input terminal and a second input terminal are respectively connected to the first output terminal and the second output terminal of the gate circuit, and a third input terminal is connected to a data input terminal and has a first output Terminal and a second output terminal, which are respectively connected to the first intermediate node and the second intermediate node; wherein the gate circuit and the stacking circuit are operated to toggle the first intermediate node and the second intermediate node in a two-state, When in this extension When the clock signal reaches a low level, the first intermediate node and the second intermediate node are switched to an initial state, and when the clock signal reaches a high level after the delay, the first intermediate node is enabled. And the second intermediate node switches to a data state representing the data input terminal, a holding circuit, latches the data state of the first intermediate node and the second intermediate node, and an output circuit, when the first intermediate node When the node and the second intermediate node are in the data state, an output node is driven with valid data; and an auxiliary circuit stores the first intermediate node and the second intermediate node 11823twf.ptd Page 37 1223272 6. The state of the data in the scope of patent application, and when the clock signal is low, the output node is driven with valid data. 1 8. The register according to item 17 of the scope of patent application, wherein the gate circuit includes a reverse AND gate and a reverse OR gate. 19. The register according to item 17 of the scope of patent application, wherein the stack circuit includes a plurality of N-channel and P-channel elements connected in series between a voltage source and ground. 20. The register according to item 17 of the scope of patent application, wherein the auxiliary circuit comprises: a storage circuit storing the data state of the first intermediate node and the second intermediate node; and a second output Circuit, connecting the memory circuit and the output node, and receiving the clock signal. 11823twf.ptd Page 38