TWI478497B - Clockless return to state domino logic gate and integrated circuit and logic function evaluation method corresponding thereto - Google Patents
Clockless return to state domino logic gate and integrated circuit and logic function evaluation method corresponding thereto Download PDFInfo
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本發明係有關於邏輯電路,且特別有關於自我重置狀態回歸骨牌式邏輯閘(self-resetting return to state(RTS) domino logic gate),其操作無須依靠時脈信號,且用於回應狀態回歸(RTS)信號。The present invention relates to logic circuits, and particularly relates to a self-resetting return to state (RTS) domino logic gate, the operation of which does not depend on a clock signal, and is used to respond to state regression. (RTS) signal.
邏輯電路在積體電路(IC)上的設置,通常以快速執行邏輯運算為目的,因此,有多種可能佈局。在許多例子中,將時脈信號導引至提供邏輯運算的電路是困難且不易實現的。包括靜態以及動態邏輯閘以及電路,大多數的邏輯電路都需要根據一輸入時脈操作。靜態互補式金氧半邏輯閘是以相當低的能量操作,但具有可觀的輸入電容,且其中信號是互補的P型裝置與N型裝置彼此角力而得,因此,靜態互補式金氧半邏輯閘的操作相當慢。骨牌式電路(Domino)較相對的靜態裝置快速,但幾乎總是要由一輸入時脈信號控制。The setting of logic circuits on integrated circuits (ICs) is usually done for fast execution of logic operations, so there are many possible layouts. In many instances, directing a clock signal to a circuit that provides logic operations is difficult and difficult to implement. Including static as well as dynamic logic gates and circuits, most logic circuits need to operate according to an input clock. The static complementary MOS logic gate operates at a relatively low energy, but has a considerable input capacitance, and the signal is complementary. The P-type device and the N-type device are in a mutual force. Therefore, the static complementary MOS logic is half-logic. The operation of the gate is quite slow. Dominos are faster than the opposite static devices, but are almost always controlled by an input clock signal.
此技術領域需要一種邏輯電路或邏輯閘,可以在無需時脈信號的狀態下以較快速且有效的方式進行邏輯運算。This field of technology requires a logic circuit or logic gate that can perform logic operations in a faster and more efficient manner without the need for a clock signal.
根據本發明一種實施方式所形成的一種無時脈狀態回歸骨牌邏輯閘,具有複數個節點、一骨牌電路、一估算電路、一致能電路以及一重置電路。上述節點各自設計在一第一狀態以及一第二狀態切換。上述輸入節點各自在設定為上述第一狀態後,根據狀態回歸操作回歸上述第二狀態。骨牌電路具有一預置狀態以及一閂鎖狀態。該骨牌電路為該預置狀態時,該骨牌電路設定一預置節點以及一致能節點至上述第一狀態、且設定該輸出節點以及一第一重置節點為上述第二狀態。當該預置節點轉態至上述第二狀態,該骨牌電路切換至該閂鎖狀態,以轉態該輸出節點至上述第一狀態且轉態該致能節點至上述第二狀態。當該第一重置節點轉態為上述第一狀態時,該骨牌電路重置回該預置狀態。當上述輸入節點為至少一個估算狀態中任一者時,該估算電路轉態該預置節點至該第二狀態,反之,則該估算電路不影響該預設節點之準位。當該致能節點為上述第二狀態時,該致能電路轉態該第二重置節點至上述第一狀態,反之,則該致能電路不影響該第二重置節點之準位。當上述輸入節點不為上述至少一個估算狀態中任一者時,該重置電路將上述第一與第二重置節點耦接在一起。當上述輸入節點為上述至少一個估算狀態中任一者時,該重置電路將上述第一與第二重置節點彼此隔離。該估算電路與該重置電路彼此可為雙配置設計。所述狀態回歸技術可由回歸邏輯’0’設計實現,用於回應回歸邏輯’0’輸入信號,或者,可由回歸邏輯’1’設計實現,用於回應回歸邏輯’1’輸入信號。A clockless state return domino logic gate formed according to an embodiment of the present invention has a plurality of nodes, a domino circuit, an estimating circuit, a matching circuit, and a reset circuit. Each of the above nodes is designed to switch between a first state and a second state. Each of the input nodes is set to the first state, and then returns to the second state according to the state regression operation. The domino circuit has a preset state and a latched state. When the domino circuit is in the preset state, the domino circuit sets a preset node and a consistent energy node to the first state, and sets the output node and a first reset node to the second state. When the preset node transitions to the second state, the domino circuit switches to the latched state to transition the output node to the first state and to transition the enable node to the second state. When the first reset node transitions to the first state, the domino circuit resets to the preset state. When the input node is in any one of the at least one estimated state, the estimating circuit shifts the preset node to the second state, and vice versa, the estimating circuit does not affect the level of the preset node. When the enabling node is in the second state, the enabling circuit switches the second reset node to the first state, and vice versa, the enabling circuit does not affect the level of the second reset node. The reset circuit couples the first and second reset nodes together when the input node is not any of the at least one estimated state. The reset circuit isolates the first and second reset nodes from each other when the input node is any of the at least one estimated state. The estimation circuit and the reset circuit can be designed in a dual configuration with each other. The state regression technique may be implemented by a regression logic '0' design for responding to the return logic '0' input signal, or may be implemented by a regression logic '1' design for responding to the return logic '1' input signal.
根據本發明一種實施方式所實現的積體電路,其中包括一第一邏輯以及一無時脈狀態回歸骨牌邏輯閘。該第一邏輯供應複數個狀態回歸信號。該等狀態回歸信號各自切換於一第一狀態以及一第二狀態。關於各個狀態回歸信號,於設定為第一狀態後,該第一邏輯會根據狀態回歸操作設定各個狀態回歸信號為第二狀態。無時脈狀態回歸骨牌邏輯閘包括一預設節點、一致能節點、一輸出節點以及一第一與一第二重置節點,各自切換於第一與第二狀態。無時脈狀態回歸骨牌邏輯閘更包括一骨牌電路、一估算電路、一致能電路以及一重置電路。An integrated circuit implemented in accordance with an embodiment of the present invention includes a first logic and a clockless state return domino logic gate. The first logic supplies a plurality of state regression signals. The state regression signals are each switched to a first state and a second state. Regarding each state regression signal, after being set to the first state, the first logic sets each state regression signal to the second state according to the state regression operation. The clockless state return domino logic gate includes a preset node, a consistent energy node, an output node, and a first and a second reset node, each of which switches to the first and second states. The clockless state return domino logic gate further includes a domino circuit, an estimation circuit, a uniformity circuit, and a reset circuit.
根據本發明一種實施方式所實現的邏輯運算估算方法。所述方法包括接收複數個狀態回歸信號。關於各個狀態回歸信號,會於設定至一第一狀態後根據狀態回歸操作回歸一第二狀態。該方法更包括供應具有一預置狀態以及一閂鎖狀態的一骨牌電路。該骨牌電路於該預置狀態時,會設定一預置節點以及一致能節點為一第一狀態,且設定一輸出節點以及一重置節點為一第二狀態。當該預置節點被轉態至該第二狀態時,該骨牌電路切換至該閂鎖狀態。當該重置節點轉態至該第一狀態,該骨牌電路轉態回該預置狀態,以轉態該輸出節點至該第一狀態、且轉態該致能節點至該第二狀態。該方法更包括估算上述狀態回歸輸入信號,其中,於該等狀態回歸輸入信號處於至少一個估算狀態的任一者時,轉態該預置節點至該第二狀態,使該骨牌電路切換為其閂鎖狀態。該方法尚包括於該致能節點於該第二狀態且該等狀態回歸信號不再為上述至少一個估算狀態的任一者時轉態該重置節點為該第一狀態以重置該骨牌電路為該預置狀態。A logic operation estimation method implemented in accordance with an embodiment of the present invention. The method includes receiving a plurality of state regression signals. Regarding each state regression signal, a second state is returned according to the state regression operation after being set to a first state. The method further includes supplying a domino circuit having a preset state and a latched state. When the domino circuit is in the preset state, a preset node and a consistent energy node are set to a first state, and an output node and a reset node are set to a second state. When the preset node is transitioned to the second state, the domino circuit switches to the latched state. When the reset node transitions to the first state, the domino circuit transitions back to the preset state to transition the output node to the first state and transitions the enable node to the second state. The method further includes estimating the state regression input signal, wherein when the state regression input signal is in any of the at least one estimated state, transitioning the preset node to the second state causes the domino circuit to switch to Latched state. The method is further included when the enabling node is in the second state and the state regression signal is no longer any of the at least one estimated state, and the reset node is in the first state to reset the domino circuit For this preset state.
根據本發明一種實施方式所形成的一無時脈狀態回歸骨牌邏輯閘,具有複數個節點,一骨牌電路、一估算電路、一致能電路以及一重置電路。各節點切換於一第一狀態以及一第二狀態。至少一個輸入節點是一狀態回歸節點,會在設定為該第一狀態後,根據狀態回歸操作回歸該第二狀態。該骨牌電路具有一預置狀態以及一閂鎖狀態。當該骨牌電路為該預置狀態時,該骨牌電路設定一預置節點以及一致能節點至該第一狀態、且設定一輸出節點以及一第一重置節點至該第二狀態。當該預置節點被拉至該第二狀態,該骨牌電路切換至該閂鎖狀態,以將該輸出節點拉至該第一狀態、且將該致能節點拉至該第二狀態。當該第一重置節點拉至該第一狀態時,該骨牌電路重置回該預置狀態。當上述輸入節點處於至少一個估算狀態的任一者時,該估算電路將該預置節點拉至該第二狀態;反之,該估算電路不干涉該預置節點之準位。當該致能節點處於該第二狀態時,該致能電路拉升該第二重置節點至該第一狀態。當上述輸入節點不處於上述至少一估算狀態的任何一種時,該重置電路將上述第一與第二重置節點耦接在一起;反之,該重置電路會將上述第一與第二重置節點相互隔離。A clockless state return domino logic gate formed according to an embodiment of the present invention has a plurality of nodes, a domino circuit, an estimation circuit, a uniformity circuit, and a reset circuit. Each node switches to a first state and a second state. At least one input node is a state regression node, and after being set to the first state, the second state is returned according to the state regression operation. The domino circuit has a preset state and a latched state. When the domino circuit is in the preset state, the domino circuit sets a preset node and a consistent energy node to the first state, and sets an output node and a first reset node to the second state. When the preset node is pulled to the second state, the domino circuit switches to the latched state to pull the output node to the first state and pull the enabling node to the second state. When the first reset node is pulled to the first state, the domino circuit is reset back to the preset state. When the input node is in any of the at least one estimated state, the estimating circuit pulls the preset node to the second state; otherwise, the estimating circuit does not interfere with the level of the preset node. The enabling circuit pulls the second reset node to the first state when the enabling node is in the second state. When the input node is not in any of the at least one estimated state, the reset circuit couples the first and second reset nodes together; otherwise, the reset circuit converts the first and second weights The nodes are isolated from each other.
上述狀態回歸技術可實現成回歸邏輯’0’的架構,用以回應回歸邏輯’0’輸入信號。或者,上述狀態回歸技術可實現成回歸回歸邏輯’1’的架構,用以回應回歸邏輯’1’輸入信號。估算電路以及重置電路可用於共同執行任何需求的邏輯運算或功能,且無需限定為彼此的雙配置設計。在一種實施方式中,估算電路乃對應上述輸入節點的集合狀態,而該重置電路則耦接少於上述輸入節點總數的輸入節點。關於提供給該重置電路的輸入節點,各個皆是狀態回歸節點。The state regression technique described above can be implemented as a regression logic '0' architecture for responding to the return logic '0' input signal. Alternatively, the state regression technique described above can be implemented as an architecture of regression regression logic '1' for responding to the return logic '1' input signal. The estimation circuit and the reset circuit can be used to jointly perform any required logic operation or function, and need not be limited to each other's dual configuration design. In one embodiment, the estimation circuit corresponds to the aggregate state of the input node, and the reset circuit is coupled to the input node that is less than the total number of input nodes. Regarding the input nodes provided to the reset circuit, each is a state regression node.
至於依照本發明一種實施方式所製作的積體電路,其中包括第一邏輯以及一無時脈狀態回歸骨牌邏輯閘。該第一邏輯提供至少一個狀態回歸信號,切換於一第一狀態以及一第二狀態。關於各個狀態回歸信號,該第一邏輯會在所述狀態回歸信號設定為第一狀態後根據該狀態回歸操作將之設定回至第二狀態。所述無時脈狀態回歸骨牌邏輯閘具有一預置節點、一致能節點、一輸出節點、以及一第一與一第二重置節點;上述節點各自在上述第一與第二狀態切換。所述無時脈狀態回歸骨牌邏輯閘更包括一骨牌電路、一估算電路、一致能電路以及一重置電路。As for an integrated circuit fabricated in accordance with an embodiment of the present invention, the first logic and a clockless state are returned to the domino logic gate. The first logic provides at least one state regression signal, switching to a first state and a second state. Regarding each state regression signal, the first logic sets the state regression signal back to the second state according to the state regression operation after the state regression signal is set to the first state. The clockless state return domino logic gate has a preset node, a consistent energy node, an output node, and a first and a second reset node; each of the nodes switches in the first and second states. The clockless state return domino logic gate further includes a domino circuit, an estimation circuit, a uniformity circuit, and a reset circuit.
至於根據本發明一種實施方式所形成的一種估算一邏輯運算的方法,其中包括以下步驟。首先,接收複數個輸入信號,該等輸入信號各自在第一狀態與第二狀態切換。此外,提供一骨牌電路,操作在一預置狀態以及一閂鎖狀態。在該預置狀態下,該骨牌電路設定一預置節點以及一致能節點至一第一狀態、且設定一輸出節點以及一重置節點至一第二狀態。當該預置節點被拉到該第二狀態時,該骨牌電路切換至該閂鎖狀態,轉態該輸出節點至該第一狀態、且將該致能節點拉到該第二狀態。當該重置節點拉到該第一狀態時,該骨牌電路重置回該預置狀態。所述方法更包括:估算上述狀態回歸輸入信號,於上述狀態回歸輸入信號處於至少一個估算狀態的任何之一時,將該預置節點拉到第二狀態,以轉態該骨牌電路至該閂鎖狀態。所述方法更包括:於該致能節點處於該第二狀態且上述狀態回歸輸入信號不為上述至少一個估算狀態的任何之一時,將該重置節點拉到該第一狀態以重置該骨牌電路。上述輸入信號包括至少一個狀態回歸信號,於設定為第一狀態後根據狀態回歸操作回歸為該第二狀態。As for a method of estimating a logical operation formed according to an embodiment of the present invention, the following steps are included. First, a plurality of input signals are received, each of which switches between a first state and a second state. In addition, a domino circuit is provided that operates in a preset state and a latched state. In the preset state, the domino circuit sets a preset node and a consistent energy node to a first state, and sets an output node and a reset node to a second state. When the preset node is pulled to the second state, the domino circuit switches to the latched state, transitions the output node to the first state, and pulls the enabling node to the second state. When the reset node is pulled to the first state, the domino circuit is reset back to the preset state. The method further includes: estimating the state regression input signal, and when the state regression input signal is in any one of the at least one estimation state, pulling the preset node to the second state to transition the domino circuit to the latch status. The method further includes: when the enabled node is in the second state and the state regression input signal is not any one of the at least one estimated state, pulling the reset node to the first state to reset the domino Circuit. The input signal includes at least one state regression signal, and after being set to the first state, returns to the second state according to the state regression operation.
根據本發明一種實施方式所實現的一無時脈狀態回歸骨牌邏輯閘,包括一骨牌電路以及一輸入電路。該無時脈狀態回歸骨牌邏輯閘用於回應複數個輸入邏輯信號,其中各個輸入邏輯信號設計為在第一與第二邏輯狀態切換。骨牌電路包括三個反相器、具有一第一傳導形式的一第一以及一第二裝置、以及具有一第二傳導形式的一裝置。第一反相器耦接於上述輸入與輸出節點之間。第二反相器耦接於上述輸出節點以及一致能節點之間。第三反相器以輸入端耦接一第一重置節點。第一傳導形式的上述第一裝置具有一控制端耦接上述輸出節點、一第一電流端耦接關於上述第一邏輯狀態的一第一電源電位節點、以及一第二電流端耦接上述預置節點。第二傳導狀態的第一裝置具有一第一電流端耦接關於該第二邏輯狀態的一第二電源電位、一控制端耦接該致能節點、以及一第二電流端耦接該第一重置節點。第一傳導形式的該第二裝置具有一第一電流端耦接該第一電源電位節點、一控制端耦接該第三反相器的輸出端、以及一第二電流端耦接該預置節點。上述輸入邏輯信號為一估算狀態時,該輸入電路將該預置節點拉到該第二邏輯狀態。上述輸入信號轉態離開該估算狀態時,該輸入電路暫時地將該第一重置節點拉到該第一邏輯狀態。A clockless state return domino logic gate implemented in accordance with an embodiment of the present invention includes a domino circuit and an input circuit. The clockless state return domino logic gate is responsive to a plurality of input logic signals, wherein each input logic signal is designed to switch between the first and second logic states. The domino circuit includes three inverters, a first and a second device having a first conductive form, and a device having a second conductive form. The first inverter is coupled between the input and output nodes. The second inverter is coupled between the output node and the consistent energy node. The third inverter is coupled to the first reset node by the input end. The first device of the first conductive form has a control end coupled to the output node, a first current terminal coupled to the first power potential node with respect to the first logic state, and a second current terminal coupled to the pre-predator Set the node. The first device of the second conduction state has a first current end coupled to a second power supply potential of the second logic state, a control terminal coupled to the enable node, and a second current terminal coupled to the first Reset the node. The second device of the first conduction mode has a first current terminal coupled to the first power potential node, a control terminal coupled to the output terminal of the third inverter, and a second current terminal coupled to the preset node. When the input logic signal is in an estimated state, the input circuit pulls the preset node to the second logic state. When the input signal transitions away from the estimated state, the input circuit temporarily pulls the first reset node to the first logic state.
在一種實施方式中,該輸入電路包括一估算電路、一致能電路以及一重置電路。當上述輸入邏輯信號為一估算狀態時,該估算電路將該預置節點拉到該第二邏輯狀態。當該致能節點為該第二邏輯狀態時,該致能電路將一第二重置節點拉到該第一邏輯狀態。當該輸入邏輯信號不為該估算狀態時,該重置電路耦接該第一重置節點至該第二重置節點。在一種實施方式中,該第一電源電位節點具有一正值電源電位,該第二電源電位節點具有一參考電位,該第一傳導形式為半導體P型設計,且該第二傳導形式為半導體N型設計。在另一種實施方式中,該第一電源電位節點具有一參考電位,該第二電源電位節點具有一正值電源電位,該第一導通形式為半導體N型設計,且該第二導通形式為半導體P型設計。上述輸入信號可包括至少一個狀態回歸信號,根據不同設計,所述輸入信號會回歸邏輯’1’或回歸邏輯’0’。In one embodiment, the input circuit includes an estimation circuit, a uniformity circuit, and a reset circuit. When the input logic signal is in an estimated state, the estimating circuit pulls the preset node to the second logic state. When the enabling node is in the second logic state, the enabling circuit pulls a second reset node to the first logic state. The reset circuit is coupled to the first reset node to the second reset node when the input logic signal is not in the estimated state. In one embodiment, the first power supply potential node has a positive power supply potential, the second power supply potential node has a reference potential, the first conductive form is a semiconductor P-type design, and the second conductive form is a semiconductor N Type design. In another embodiment, the first power supply potential node has a reference potential, the second power supply potential node has a positive power supply potential, the first conductive form is a semiconductor N-type design, and the second conductive form is a semiconductor P-type design. The input signal may include at least one state regression signal that may be returned to logic '1' or regression logic '0' depending on the design.
根據本發明一種實施方式所實現的一積體電路包括至少一個無時脈狀態回歸骨牌邏輯閘以及一第一電路。該第一電路供應至少一個狀態回歸信號,且於上述狀態回歸信號設定為第一狀態後根據狀態回歸操作將之設定為第二狀態。無時脈狀態回歸骨牌邏輯閘可以上述類似方式設計。An integrated circuit implemented in accordance with an embodiment of the present invention includes at least one clockless state return domino logic gate and a first circuit. The first circuit supplies at least one state regression signal, and after the state regression signal is set to the first state, is set to the second state according to the state regression operation. The no-clock state return to the domino logic gate can be designed in a similar manner as described above.
一種估算多個輸入邏輯信號的方法。所述該等輸入邏輯信號包括至少一個狀態回歸輸入信號。該方法包括設定一預置節點為一第一邏輯狀態,該第一邏輯狀態為一第二邏輯狀態的反相。所述方法更包括反相該預置節點以決定一輸出節點的邏輯狀態,反相該輸出節點以決定一致能節點的邏輯狀態,於該致能節點為該第一邏輯狀態時轉態一重置節點至該第二邏輯狀態,反相該重置節點以決定一反相重置節點的一邏輯狀態,於該反相重置節點為該第二邏輯狀態時轉態該預置節點至該第一邏輯狀態,於上述輸入信號組成一估算狀態時強制該預置節點至該第二邏輯狀態,供應於轉態為第一邏輯狀態後轉態回第二邏輯狀態的至少一個狀態回歸信號,以及於該致能節點為該第二邏輯狀態且上述輸入信號根據狀態回歸操作跳脫該估算狀態時強制該重置節點為該第一邏輯狀態。此外,當重置節點被強制為該第一邏輯狀態,反相重置節點轉態回該第二邏輯狀態,接著,轉態該預置節點為該第一邏輯狀態,再來,轉態上述輸出節點回該第二邏輯狀態,接著,轉態該致能節點回到該第一邏輯狀態,接著,轉態該重置節點回該第二邏輯狀態,且接著,轉態該反相重置節點回該第一邏輯狀態。A method of estimating multiple input logic signals. The input logic signals include at least one state regression input signal. The method includes setting a preset node to a first logic state, the first logic state being an inversion of a second logic state. The method further includes inverting the preset node to determine a logic state of an output node, inverting the output node to determine a logic state of the consistent energy node, and shifting the state when the enable node is in the first logic state Setting a node to the second logic state, inverting the reset node to determine a logic state of an inverting reset node, and transitioning the preset node to the inverting reset node when the second logic state is a first logic state, when the input signal forms an estimated state, forcing the preset node to the second logic state, and supplying at least one state regression signal that is transitioned to the second logic state after the transition state is the first logic state, And forcing the reset node to be the first logic state when the enable node is in the second logic state and the input signal trips the estimated state according to the state regression operation. In addition, when the reset node is forced to the first logic state, the inverting reset node returns to the second logic state, and then, the preset node is in the first logic state, and then, the transition state is Returning the node to the second logic state, and then transitioning the enable node back to the first logic state, then transitioning the reset node back to the second logic state, and then transitioning the inverted logic state The node returns to the first logical state.
以下說明將幫助本技術領域人士得以將本說明書所揭露的發明內容製作且運用於特定應用以及條件。本技術領域人士依照以下所揭露之實施方式可能發展出多種變形,且說明書所揭露的技巧也可能以其他實施方式實現。因此,本發明的範圍並非意圖限定在以下所示或所述之特定實施例,事實上,應以所揭露之技巧與特徵的最廣範圍解釋之。發明人已發現業界對高速、有效率且無須依靠時脈信號之邏輯運算的需求。因此,發明人發展出無須時脈信號的狀態回歸骨牌邏輯閘,以下提供第1~17圖討論之。The following description will assist those skilled in the art to make and use the invention disclosed herein. A person skilled in the art may develop various modifications in accordance with the embodiments disclosed below, and the techniques disclosed in the specification may be implemented in other embodiments. Therefore, the scope of the invention is not intended to be limited The inventors have discovered a need in the industry for high speed, efficient, and logical operations that do not rely on clock signals. Therefore, the inventors developed a state-return domino logic gate without the need for a clock signal, which is discussed below in Figures 1-17.
第1圖為一簡化的方塊圖,圖解一晶片(或一積體電路,IC)101,其中包括根據本發明一種實施方式所實現的一無時脈狀態回歸骨牌電路(clockless return to state domino circuit)105。積體電路101可為任何型式,且可包括本技術領域已發展之任何數量之電子電路。在一種實施方式中,晶片101為一處理器,例如一微控制器(microcontroller)或微處理器(microprocessor)等類似裝置,此外,任何類型的積體電路或晶片都可能為其應用。一時脈信號CLK佈置在該積體電路101上,由一狀態回歸邏輯103接收。該狀態回歸邏輯103輸出一或多個狀態回歸輸入信號IN(RTS)給耦接該無時脈狀態回歸骨牌電路105對應輸入端的複數個輸入節點。該時脈信號CLK也被牽線至非狀態回歸邏輯(NON-RTS logic)104。該非狀態回歸邏輯104輸出一或多個非狀態回歸信號IN(NON-RTS)給耦接該無時脈狀態回歸骨牌電路105對應輸入端的複數個輸入端。以下更詳細敘述之。隨著無時脈狀態回歸骨牌電路105的設計不同,輸入信號IN之內容(IN(RTS)與IN(NON-RTS)之組合)會有所不同。在某些應用中(例如,雙配置設計/dual configurations),各個輸入信號IN都是狀態回歸信號RTS(以邏輯或閘設計為例)。此外,在其他應用中(例如,非雙配置設計/non-dual configuration),輸入信號IN中至少有一個為狀態回歸信號RTS,至於輸入信號IN內剩餘的各個信號則為狀態回歸信號RTS或非狀態回歸NON-RTS信號。通常,是在以下狀況下需要發展與提供上述狀態回歸信號。上述無時脈狀態回歸骨牌電路105輸出一個或多個狀態回歸輸出信號OUT(RTS)至另一邏輯電路107的相關輸入端,且時脈信號CLK亦被連接至邏輯電路107的時脈輸入端。狀態回歸邏輯103包括任何靜態或動態電路的組合,且更包括任何閂鎖(latch)或暫存器電路的組合,以根據狀態回歸操作提供輸入信號IN(RTS)。邏輯107包括任何靜態或骨牌電路(有腳位footed或無腳位footless)的組合且/或任何閂鎖或暫存器的組合,以接收、或閂鎖、或暫存所述輸出信號OUT(RTS)。1 is a simplified block diagram illustrating a wafer (or integrated circuit, IC) 101 including a clockless return to state domino circuit implemented in accordance with an embodiment of the present invention. ) 105. The integrated circuit 101 can be of any type and can include any number of electronic circuits that have been developed in the art. In one embodiment, the wafer 101 is a processor, such as a microcontroller or microprocessor, and the like, and any type of integrated circuit or wafer may be used for it. A clock signal CLK is disposed on the integrated circuit 101 and is received by a state regression logic 103. The state regression logic 103 outputs one or more state regression input signals IN (RTS) to a plurality of input nodes coupled to the corresponding inputs of the clockless state regression domino circuit 105. The clock signal CLK is also routed to the NON-RTS logic 104. The non-state regression logic 104 outputs one or more non-state regression signals IN (NON-RTS) to a plurality of inputs coupled to the corresponding inputs of the clockless state regression domino circuit 105. This is described in more detail below. The content of the input signal IN (the combination of IN (RTS) and IN (NON-RTS)) will vary depending on the design of the clockless state return domino circuit 105. In some applications (eg, dual configurations), each input signal IN is a state regression signal RTS (exemplified by a logic or gate design). In addition, in other applications (for example, non-dual configuration), at least one of the input signals IN is a state regression signal RTS, and the remaining signals in the input signal IN are state regression signals RTS or non- The state returns to the NON-RTS signal. Generally, it is necessary to develop and provide the above state regression signal under the following conditions. The clockless state return domino circuit 105 outputs one or more state regression output signals OUT (RTS) to the associated input of another logic circuit 107, and the clock signal CLK is also coupled to the clock input of the logic circuit 107. . State regression logic 103 includes any combination of static or dynamic circuitry, and further includes any combination of latch or scratchpad circuitry to provide an input signal IN (RTS) in accordance with a state regression operation. Logic 107 includes any combination of static or domino circuits (footed or footless) and/or any combination of latches or registers to receive, or latch, or temporarily store the output signal OUT ( RTS).
所述之狀態回歸輸入與輸出信號IN與OUT代表的是信號會在切換到一第二狀態後回到一預定狀態或一第一狀態。在二進位制邏輯中,狀態回歸不是回到邏輯’0’(RT0,其預設邏輯狀態為邏輯’0’),就是回到邏輯’1’(RT1,其預設邏輯狀態為邏輯’1’)。無時脈狀態回歸骨牌電路105包括一或多個無時脈狀態回歸骨牌邏輯閘。該等無時脈狀態回歸骨牌邏輯閘彼此串疊(cascade),或根據任何串聯或並聯方式耦接在一起。多種數量的無時脈狀態回歸骨牌邏輯閘都有機會被串疊或串聯在一起,僅受限於時間條件,所述時間條件定義於相應之輸出信號有效與否。每一個無時脈狀態回歸骨牌邏輯閘可接收任何數量的狀態回歸輸入信號且輸出至少一個狀態回歸輸出信號至其他電路─包括其他無時脈狀態回歸骨牌邏輯閘、或邏輯電路107、或其他類似電路。The state regression input and output signals IN and OUT represent that the signal will return to a predetermined state or a first state after switching to a second state. In binary logic, state regression does not return to logic '0' (RT0, whose default logic state is logic '0'), or returns to logic '1' (RT1, whose default logic state is logic '1' '). The no-vehicle state return domino circuit 105 includes one or more clockless state return domino logic gates. The clockless state return domino logic gates are cascaded to each other or coupled together according to any series or parallel connection. A variety of non-synchronous state return domino logic gates have the opportunity to be cascaded or concatenated together, limited only by time conditions, which are defined by whether the corresponding output signal is valid or not. Each clockless state return domino logic gate can receive any number of state regression input signals and output at least one state regression output signal to other circuits - including other no clock state return domino logic gates, or logic circuit 107, or the like Circuit.
第2圖為一方塊圖,圖解根據本案一種實施方式所實現的一無時脈狀態回歸骨牌邏輯閘200,用以實現該無時脈狀態回歸骨牌電路105內的一個或多個無時脈狀態回歸骨牌邏輯閘。輸入信號IN內的一個或多個信號供應給對應的輸入節點上,以輸入至一狀態回歸估算電路201的對應輸入端,且至少一個上述輸入信號IN會提供給一狀態回歸重置電路203。雖然圖中標示將同樣的輸入信號IN供應給電路201與203兩者,但在某些實施方式中─以下將詳細討論之─供應給該狀態回歸重置電路203的可僅為上述輸入信號IN的一子集合。此外,輸入信號IN可為狀態回歸信號(RTS)或可包括一或多個非狀態回歸信號(non-RTS)。無時脈狀態回歸骨牌邏輯閘200更包括一狀態回歸骨牌電路205;該狀態回歸骨牌電路205耦接一對電源電位VSRC1以及VSRC2。電源電位VSRC1以及VSRC2各由一電源電路(無顯示在圖中)提供,且以適當的電位統一供應電源電位給積體電路101上的複數個電子電路,所採用技術可為本技術領域常見技術。每一個電源電位所供應的電位以及對應在電源電位VSRC1與VSRC2之間的電位區間乃與電路型式和特定技術或製程相關,例如,可為5伏特、3.3伏特或2.1伏特等。通常,電源電位VSRC1與VSRC2之一為一參考電位(例如,VSS),且另一為一供電電位VDD,可以本技術領域常見技術實現之。狀態回歸估算電路201、狀態回歸重置電路203與狀態回歸致能電路207可共同組成一輸入電路,對應輸入信號IN動作。FIG. 2 is a block diagram illustrating a clockless state return domino logic gate 200 implemented in accordance with an embodiment of the present invention for effecting one or more clockless states in the clockless state return domino circuit 105. Return to the domino logic gate. One or more signals in the input signal IN are supplied to the corresponding input node for input to a corresponding input of a state regression estimation circuit 201, and at least one of the above-described input signals IN is supplied to a state regression reset circuit 203. Although the same input signal IN is supplied to both circuits 201 and 203, in some embodiments - as will be discussed in detail below - only the input signal IN may be supplied to the state return reset circuit 203. A collection of ones. Additionally, the input signal IN can be a state regression signal (RTS) or can include one or more non-state regression signals (non-RTS). The clockless state return domino logic gate 200 further includes a state return domino circuit 205; the state return domino circuit 205 is coupled to a pair of power supply potentials VSRC1 and VSRC2. The power supply potentials VSRC1 and VSRC2 are each provided by a power supply circuit (not shown in the figure), and the power supply potential is uniformly supplied to a plurality of electronic circuits on the integrated circuit 101 at an appropriate potential, and the adopted technology can be a common technology in the technical field. . The potential supplied by each of the power supply potentials and the potential interval corresponding to the power supply potentials VSRC1 and VSRC2 are related to the circuit type and the particular technique or process, for example, 5 volts, 3.3 volts, or 2.1 volts. Typically, one of the power supply potentials VSRC1 and VSRC2 is a reference potential (e.g., VSS) and the other is a supply potential VDD, which can be implemented by techniques common in the art. The state regression estimation circuit 201, the state regression reset circuit 203, and the state regression enable circuit 207 can collectively constitute an input circuit that operates in response to the input signal IN.
狀態回歸估算電路201耦接電源電位VSRC2,且更耦接一預置節點202以耦接該狀態回歸骨牌電路205的一預置輸入/輸出端PSET。該狀態回歸骨牌電路205具有一輸出端供應一狀態回歸輸出信號OUT(RTS)於一輸出節點208,且具有一重置輸入輸出端RST產生一重置信號(同樣標為RST)於一重置節點206,且還具有一狀態回歸致能信號輸出端RTSE供應一狀態回歸致能信號(同樣標為RTSE)於對應的一狀態回歸致能節點204。無時脈狀態回歸骨牌邏輯閘200包括一狀態回歸致能電路207耦接電源電位VSRC1。該狀態回歸致能電路207具有一輸入端耦接節點204以接收該狀態回歸致能信號RTSE,且具有另一端點耦接一第二重置節點210。該狀態回歸重置電路203耦接於上述重置節點210與206之間。The state regression estimation circuit 201 is coupled to the power supply potential VSRC2, and is further coupled to a preset node 202 for coupling to a preset input/output terminal PSET of the state return domino circuit 205. The state return domino circuit 205 has an output that supplies a state regression output signal OUT (RTS) to an output node 208, and has a reset input and output terminal RST that generates a reset signal (also labeled as RST) for a reset. Node 206, and also having a state regression enable signal output terminal RTSE supplies a state regression enable signal (also labeled RTSE) to the corresponding one state regression enable node 204. The clockless state return domino logic gate 200 includes a state return enable circuit 207 coupled to the power supply potential VSRC1. The state transition enabling circuit 207 has an input coupled to the node 204 to receive the state regression enable signal RTSE and another endpoint coupled to a second reset node 210. The state regression reset circuit 203 is coupled between the reset nodes 210 and 206.
各個信號節點(例如,IN、OUT、PSET、RST、RTSE等)具有一第一邏輯狀態以及一第二邏輯狀態;該第一邏輯狀態相關於電源電位VSRC2,且該第二邏輯狀態相關於電源電位VSRC1。狀態回歸估算電路201具有一初始預設狀態,此時各個輸入信號IN為上述第一邏輯狀態,與其回歸狀態(return state)相同。當上述輸入信號IN一同轉態,形成一個或多個估算狀態中任一者時,該狀態回歸估算電路201進入一估算狀態,產生一估算事件。該等輸入信號IN的一種或多種估算狀態─產生所述估算事件─乃由該狀態回歸估算電路201各自的邏輯設計有關。例如,若該狀態回歸估算電路201設計為一邏輯或閘,則一估算事件於該等輸入信號IN中任一或多個發生第一狀態至第二狀態之轉態時發生。另一種實施方式中,若該狀態回歸估算電路201是實現成一邏輯及閘,則一估算事件只會在每一個輸入信號IN都由該第一邏輯狀態轉態到該第二邏輯狀態時發生。該狀態回歸骨牌電路205通常具有兩種狀態,包括一預置狀態(“preset” state)以及一閂鎖狀態(“latch” state)。該預置狀態通常為該狀態回歸骨牌電路205的初始、或預設值。在該預置狀態下,該狀態回歸骨牌電路205會預置其預置輸入/輸出端PSET,因此節點202為該第二邏輯狀態。此外,在該預置狀態下,狀態回歸骨牌電路205初始設定該重置信號RST為該第一邏輯狀態且設定該狀態回歸致能信號RTSE為該第二邏輯狀態。該狀態回歸重置電路203具有一隔離狀態(isolation state)以及一重置狀態(reset state),由施加於其上的該等輸入信號IN之狀態決定。當施加於該狀態回歸重置電路203的該等輸入信號IN各自處於或回歸該第一邏輯狀態,該狀態回歸重置電路203為其重置狀態。否則,該狀態回歸重置電路203處於其隔離狀態。必須特別說明的是,每當該等輸入信號IN的集體狀態符合一個或多個估算狀態的任一者時,狀態回歸重置電路203是位於其隔離狀態。當該狀態回歸致能信號RTSE處於該第二邏輯狀態時,該狀態回歸致能電路207處於其初始預設狀態;當該狀態回歸致能信號RSTE處於該第一邏輯狀態時,該狀態回歸致能電路207轉態至一致能狀態。Each signal node (eg, IN, OUT, PSET, RST, RTSE, etc.) has a first logic state and a second logic state; the first logic state is related to a power supply potential VSRC2, and the second logic state is related to a power source Potential VSRC1. The state regression estimation circuit 201 has an initial preset state, in which case each input signal IN is in the first logic state described above, and is the same as its return state. When the input signal IN is rotated together to form any one of one or more estimated states, the state regression estimating circuit 201 enters an estimated state to generate an estimated event. One or more estimated states of the input signals IN - generating the estimated events - are related to the respective logic design of the state regression estimation circuit 201. For example, if the state regression estimation circuit 201 is designed as a logic or gate, an estimation event occurs when any one or more of the input signals IN transitions from the first state to the second state. In another embodiment, if the state regression estimation circuit 201 is implemented as a logic gate, an estimation event occurs only when each input signal IN transitions from the first logic state to the second logic state. The state return domino circuit 205 typically has two states, including a preset state ("preset" state) and a latch state ("latch" state). The preset state is typically the initial, or preset, value of the state return to the domino circuit 205. In the preset state, the state return domino circuit 205 presets its preset input/output terminal PSET, so the node 202 is in the second logic state. In addition, in the preset state, the state return domino circuit 205 initially sets the reset signal RST to the first logic state and sets the state regression enable signal RTSE to the second logic state. The state regression reset circuit 203 has an isolation state and a reset state determined by the state of the input signals IN applied thereto. When the input signals IN applied to the state regression reset circuit 203 are each in or returning to the first logic state, the state regression reset circuit 203 is in its reset state. Otherwise, the state regression reset circuit 203 is in its isolated state. It must be particularly noted that the state regression reset circuit 203 is in its isolated state whenever the collective state of the input signals IN conforms to any one of the one or more estimated states. When the state regression enable signal RTSE is in the second logic state, the state regression enabling circuit 207 is in its initial preset state; when the state regression enabling signal RSTE is in the first logic state, the state returns to The power circuit 207 is transitioned to a consistent state.
以下討論無時脈狀態回歸骨牌邏輯閘200的操作。一估算事件發生在該等輸入信號IN轉態為一個或多個估算狀態中任一者時;此時,該狀態回歸估算電路201進入其估算狀態、且該狀態回歸重置電路203進入其隔離狀態。在上述估算狀態中,該狀態回歸估算電路201改變節點202的信號,因此,狀態回歸骨牌電路205的預置輸入輸出端PSET轉態至該第一邏輯狀態,導致該狀態回歸骨牌電路205自其預置狀態切換到閂鎖狀態。該狀態回歸骨牌電路205於切換到其閂鎖狀態時切換輸出信號OUT至該第二邏輯狀態,且切換狀態回歸致能信號RTSE至第一邏輯狀態,且不再影響該重置信號RST。狀態回歸致能電路207進入其致能狀態,耦接節點210至電源電位VSRC1,以回應第一邏輯狀態的狀態回歸致能信號RTSE。由於狀態回歸重置電路203乃回應輸入信號IN處於其隔離狀態,因此,即使狀態回歸致能電路207被致能,仍不影響該重置信號RST。基於上述原因,該重置信號RST仍然維持在第一邏輯狀態。The operation of the clockless state return to the domino logic gate 200 is discussed below. An estimated event occurs when the input signal IN transitions to any one of the one or more estimated states; at this time, the state regression estimation circuit 201 enters its estimated state, and the state regression reset circuit 203 enters its isolation. status. In the above estimated state, the state regression estimating circuit 201 changes the signal of the node 202, and therefore, the preset input/output terminal PSET of the state return domino circuit 205 transitions to the first logic state, causing the state to return to the domino circuit 205 from The preset state is switched to the latched state. The state return domino circuit 205 switches the output signal OUT to the second logic state when switching to its latched state, and switches the state regression enable signal RTSE to the first logic state and no longer affects the reset signal RST. The state regression enabling circuit 207 enters its enabled state, coupling the node 210 to the power supply potential VSRC1 in response to the state return enable signal RTSE of the first logic state. Since the state regression reset circuit 203 is in response to the input signal IN being in its isolated state, even if the state regression enabling circuit 207 is enabled, the reset signal RST is not affected. For the above reasons, the reset signal RST remains in the first logic state.
當供應給狀態回歸重置電路203的狀態回歸輸入信號IN根據狀態回歸操作回到其預設狀態,狀態回歸重置電路203進入其重置狀態,將重置節點210與206耦接在一起,藉由電路203與207將重置信號RST拉至該第二邏輯狀態。重置信號RST至第二邏輯狀態的轉態會引發一重置事件,使狀態回歸骨牌電路205回歸其預置狀態。說明如下,狀態回歸骨牌電路205會改變其預置輸入輸出端PSET之電位,使節點202回到第二邏輯狀態。此外,狀態回歸骨牌電路205會將輸出信號OUT切換回第一邏輯狀態,且切換狀態回歸致能信號RTSE回該第二邏輯狀態。該狀態回歸致能電路207會對應狀態回歸致能信號RTSE至第二邏輯狀態的轉態而有效地關閉,且狀態回歸骨牌電路205會將重置信號RST拉回第一邏輯狀態。When the state regression input signal IN supplied to the state regression reset circuit 203 returns to its preset state according to the state regression operation, the state regression reset circuit 203 enters its reset state, coupling the reset nodes 210 and 206 together. The reset signal RST is pulled to the second logic state by circuits 203 and 207. The transition of the reset signal RST to the second logic state causes a reset event to cause the state return domino circuit 205 to return to its preset state. As explained below, the state return domino circuit 205 changes the potential of its preset input and output terminal PSET, causing the node 202 to return to the second logic state. In addition, the state regression domino circuit 205 switches the output signal OUT back to the first logic state, and the switching state regression enable signal RTSE returns to the second logic state. The state regression enabling circuit 207 is effectively turned off corresponding to the state transition enable signal RTSE to the transition state of the second logic state, and the state return domino circuit 205 pulls the reset signal RST back to the first logic state.
總結之,當輸入信號IN一同轉態到一個或多個估算狀態中任一者時,狀態回歸估算電路201轉態到一估算狀態,產生一估算事件,且該狀態回歸重置電路203進入一隔離狀態。回應上述估算事件,狀態回歸骨牌電路205自其預置狀態轉態到閂鎖狀態,切換輸出信號OUT、且切換該狀態回歸致能信號RTSE以致能該狀態回歸致能電路207。當各個狀態回歸輸入信號IN、或至少供應給該狀態回歸重置電路203的該些狀態回歸輸入信號IN根據狀態回歸操作回到第一邏輯狀態時,狀態回歸估算電路201回到其預設狀態、且該狀態回歸重置電路203進入其重置狀態將該重置信號RST拉到該第二邏輯狀態以產生一重置事件。回應該重置事件,該狀態回歸骨牌電路205回到其預置狀態,令該狀態回歸致能信號RSTE回歸該第二邏輯狀態以除能該狀態回歸致能電路207。一旦該狀態回歸致能電路207除能,狀態回歸重置電路203的狀態就不再影響操作,直至另一個估算事件發生後。該狀態回歸骨牌電路205隨後將重置信號RST拉回第一邏輯狀態,使該無時脈狀態回歸骨牌邏輯閘200預備好迎接下一個估算事件。如此一來,無時脈狀態回歸骨牌邏輯閘200為一自我重置電路,無須時脈信號即實現一邏輯狀況估算。In summary, when the input signal IN is transitioned together to any one of the one or more estimated states, the state regression estimation circuit 201 transitions to an estimated state, generating an estimated event, and the state regression reset circuit 203 enters a Isolated state. In response to the estimated event, the state return domino circuit 205 transitions from its preset state to the latched state, switches the output signal OUT, and switches the state regression enable signal RTSE to enable the state regression enable circuit 207. When the respective state regression input signals IN, or at least the state regression input signals IN supplied to the state regression reset circuit 203 return to the first logic state according to the state regression operation, the state regression estimation circuit 201 returns to its preset state. And the state regression reset circuit 203 enters its reset state to pull the reset signal RST to the second logic state to generate a reset event. The reset event should be returned. The state returns to the domino circuit 205 to return to its preset state, causing the state regression enable signal RSTE to return to the second logic state to disable the state regression enable circuit 207. Once the state regression enable circuit 207 is disabled, the state of the state regression reset circuit 203 no longer affects operation until another estimated event occurs. The state return domino circuit 205 then pulls the reset signal RST back to the first logic state, causing the no-clock state to return to the domino logic gate 200 ready for the next estimated event. In this way, the clockless state is returned to the domino logic gate 200 as a self-resetting circuit, and a logic condition estimation is implemented without the clock signal.
以下更討論無時脈狀態回歸骨牌邏輯閘200的一回歸邏輯’0’(RT0)邏輯閘設計以及一回歸邏輯’1’(RT1)邏輯閘設計。所述回歸邏輯’0’邏輯閘設計是用於回應回歸邏輯’0’輸入信號。所述回歸邏輯’1’邏輯閘設計是用於回應回歸邏輯’1’輸入信號。在一些實施方式中,狀態回歸估算電路201以及狀態回歸重置電路203為雙配置(dual configurations)設計,用以回應同樣的狀態回歸輸入信號IN。在這樣的實施方式中(例如,第10與17圖所示實施方式),狀態回歸重置電路203被簡化,其中,供應給該狀態回歸估算電路201的該些狀態回歸輸入信號IN也會供應給狀態回歸重置電路203,同時,與狀態回歸估算電路201同樣的邏輯運算會由狀態回歸重置電路203施行在選定的該狀態回歸輸入信號IN子集合上。在其他實施方式中,電路201與203並非雙配置設計,且供應給電路201的該等輸入信號IN中僅一子集合是供應給該狀態回歸重置電路203。供應給該狀態回歸重置電路203的該等輸入信號IN乃狀態回歸信號,無論剩餘的輸入信號IN為狀態回歸(RTS)或非狀態回歸(non-RTS)信號。在所述任一實施方式中,估算狀態為真時,重置狀態就不成立。狀態回歸估算電路顯示估算狀態不符合時,估算狀態是不成立的。在估算狀態不成立、但狀態回歸重置電路之重置條件成立時,所述重置狀態成立。A regression logic '0' (RT0) logic gate design and a regression logic '1' (RT1) logic gate design for the clockless state return domino logic gate 200 are discussed further below. The regression logic '0' logic gate design is used to respond to the return logic '0' input signal. The regression logic '1' logic gate design is used to respond to the return logic '1' input signal. In some embodiments, state regression estimation circuit 201 and state regression reset circuit 203 are dual configurations designed to respond to the same state regression input signal IN. In such an embodiment (e.g., the embodiments shown in Figures 10 and 17), the state regression reset circuit 203 is simplified, wherein the state regression input signals IN supplied to the state regression estimation circuit 201 are also supplied. The state regression reset circuit 203 is simultaneously subjected to the same logic operation as the state regression estimation circuit 201 by the state regression reset circuit 203 on the selected subset of the state regression input signals IN. In other embodiments, circuits 201 and 203 are not of a dual configuration design, and only a subset of the input signals IN supplied to circuit 201 are supplied to the state regression reset circuit 203. The input signals IN supplied to the state regression reset circuit 203 are state regression signals, regardless of whether the remaining input signal IN is a state regression (RTS) or a non-state return (non-RTS) signal. In any of the embodiments described above, when the estimated state is true, the reset state is not established. The state regression estimation circuit shows that the estimated state is not true when the estimated state is not met. The reset state is established when the estimation state is not established but the reset condition of the state regression reset circuit is established.
第3圖為一方塊圖,圖解一無時脈回歸邏輯’0’骨牌邏輯閘300,為無時脈狀態回歸骨牌邏輯閘200的一種回歸邏輯’0’實施方式。輸出信號OUT以及至少一輸入信號IN設計為回歸邏輯’0’信號,以邏輯’0’為預設邏輯狀態。基於本技術領域現有技術,將電源電位VSRC1作為一供電電位VDD,且將電源電位VSRC2作為一參考電位VSS。該狀態回歸估算電路201、狀態回歸骨牌電路205以及狀態回歸重置電路203分別被實現成一回歸邏輯’0’估算電路301、一回歸邏輯’0’骨牌電路305以及一回歸邏輯’0’重置電路303,用以根據回歸邏輯’0’操作而設計。必須注意的是,雖然電路301與303中任一者可能隔離其他電路為一回歸邏輯’1’電路(以其輸出觀之),但仍然是以其輸入與回歸邏輯’0’骨牌邏輯閘300整體功能的觀點視之為回歸邏輯’0’ 技術。前述預置輸入輸出端PSET被實現為一預充輸入輸出端PCHG。該預充輸入輸出端PCHG耦接一預充節點302;該預充節點302實現前述預置節點202。無時脈回歸邏輯’0’骨牌邏輯閘300設定一回歸邏輯’0’輸出信號OUT於一輸出節點308,而重置信號RST則產生在重置節點306。前述狀態回歸致能節點204被實現為一回歸邏輯’0’致能節點304,耦接P通道裝置P1之閘極。所述P通道裝置P1實現前述狀態回歸致能電路207。P通道裝置P1的源極耦接供電電為VDD且其汲極經由一第二重置節點310耦接回歸邏輯’0’重置電路303。回歸邏輯’0’重置電路303更耦接重置節點306。Figure 3 is a block diagram illustrating a clockless regression logic '0' domino logic gate 300, a regression logic '0' implementation for returning to the domino logic gate 200 without the clock state. The output signal OUT and the at least one input signal IN are designed to be a return logic '0' signal with a logic '0' as a predetermined logic state. Based on the prior art in the art, the power supply potential VSRC1 is taken as a supply potential VDD, and the power supply potential VSRC2 is taken as a reference potential VSS. The state regression estimation circuit 201, the state regression domino circuit 205, and the state regression reset circuit 203 are implemented as a regression logic '0' estimation circuit 301, a regression logic '0' domino circuit 305, and a regression logic '0' reset, respectively. Circuit 303 is designed to operate according to a return logic '0'. It must be noted that although any of circuits 301 and 303 may isolate other circuits from a return logic '1' circuit (as viewed from its output), it is still with its input and return logic '0' domino logic gate 300. The overall function view is regarded as the return logic '0' technology. The aforementioned preset input and output terminal PSET is implemented as a precharge input/output terminal PCHG. The pre-charge input and output terminal PCHG is coupled to a pre-charge node 302; the pre-charge node 302 implements the preset node 202. The clockless return logic '0' domino logic gate 300 sets a return logic '0' output signal OUT to an output node 308, and the reset signal RST is generated at the reset node 306. The state transition enable node 204 is implemented as a return logic '0' enable node 304 coupled to the gate of the P channel device P1. The P-channel device P1 implements the aforementioned state regression enabling circuit 207. The source of the P-channel device P1 is coupled to the power supply VDD and its drain is coupled to the return logic '0' reset circuit 303 via a second reset node 310. The return logic '0' reset circuit 303 is further coupled to the reset node 306.
第4圖圖解一回歸邏輯’0’骨牌電路400,為回歸邏輯’0’骨牌電路305的一種實施方式。預充節點302耦接一反相器401的輸入端,並耦接P通道裝置P2與P3的汲極。反相器401的輸出耦接輸出節點308提供所述回歸邏輯’0’輸出信號OUT(RT0),並將之供應給P通道裝置P3的閘極、以及另一個反相器403的輸入端。反相器403的輸出耦接節點304以供應狀回歸邏輯’0’致能信號RT0E至N通道裝置N1的閘極。N通道裝置N1的源極耦接參考電位VSS,且其汲極耦接重置節點306以供應重置信號RST。重置信號RST供應給一反相器405的輸入端。反相器405之輸出端供應一反相重置信號RSTB。反相重置信號RSTB供應給P通道裝置P2的閘極,其源極耦接供電電位VDD。反相器401與P通道裝置P3一同組成一半維持(half-keeper)電路402,以維持預充輸入輸出端PCHG之準位直至回歸邏輯’0’估算電路301將之拉低。預充輸入輸出端PCHG初始預充為高準位,因此,反相器401令輸出信號OUT為低準位,以導通P通道裝置P3。P通道裝置P3將預充輸入輸出端PCHG拉至供電電位VDD,以維持預充輸入輸出端PCHG的高準位邏輯狀態。因為輸出信號OUT是初始為低準位,反相器403令回歸邏輯’0’致能信號RT0E導通N通道裝置N1,以拉低重置信號RST的準位。反相器405因而會提供高準位的反相重置信號RSTB,使P通道裝置P2不導通。Figure 4 illustrates a regression logic '0' domino circuit 400 as an embodiment of a return logic '0' domino circuit 305. The pre-charging node 302 is coupled to the input of an inverter 401 and coupled to the drains of the P-channel devices P2 and P3. The output coupled to the output node 308 of the inverter 401 provides the return logic '0' output signal OUT (RT0) and supplies it to the gate of the P-channel device P3 and the input of the other inverter 403. The output of inverter 403 is coupled to node 304 to supply a return logic '0' enable signal RT0E to the gate of N-channel device N1. The source of the N-channel device N1 is coupled to the reference potential VSS, and its drain is coupled to the reset node 306 to supply the reset signal RST. The reset signal RST is supplied to the input of an inverter 405. An output of the inverter 405 is supplied with an inverted reset signal RSTB. The inverted reset signal RSTB is supplied to the gate of the P channel device P2, and its source is coupled to the power supply potential VDD. The inverter 401, together with the P channel device P3, constitutes a half-keeper circuit 402 to maintain the level of the precharge input and output terminal PCHG until the return logic '0' estimation circuit 301 pulls it low. The precharge input/output terminal PCHG is initially precharged to a high level, and therefore, the inverter 401 causes the output signal OUT to be at a low level to turn on the P channel device P3. The P channel device P3 pulls the precharge input and output terminal PCHG to the power supply potential VDD to maintain the high level logic state of the precharge input and output terminal PCHG. Since the output signal OUT is initially at a low level, the inverter 403 causes the return logic '0' enable signal RT0E to turn on the N-channel device N1 to pull down the level of the reset signal RST. Inverter 405 thus provides a high level inverted reset signal RSTB that disables P channel device P2.
參考第3與4圖,回應輸入信號IN中單一或多者轉態為一或多種估算狀態的其中一種時所產生的一估算事件,回歸邏輯’0’估算電路301會將預充輸入輸出端PCHG準位拉低,致使回歸邏輯’0’骨牌電路400轉態至其閂鎖狀態。因此,反相器401拉高輸出信號OUT的準位,使P通道裝置P3不導通。反相器403會拉低回歸邏輯’0’致能信號RT0E的準位,使P通道裝置P1導通並使N通道裝置N1不導通。P通道裝置P1的導通會使節點310耦接到供電電位VDD。N通道裝置N1的不導通會使重置信號RST不再被限制為低準位。輸入信號IN的估算狀態會使回歸邏輯’0’重置電路303轉態至其隔離狀態,使節點306隔離節點310。如此一來,重置節點306會被暫時隔離,故重置信號RST不會被刻意驅動為任何狀態。由於沒有任何其他裝置作用,重置信號RST仍然維持在低準位。在另一種實施方式中,另有一個N通道裝置N2(以虛線標示)供應在圖4電路中,與反相器405組成另一半維持電路,以維持重置信號RST的低準位狀態。N通道裝置N2具有一閘極接收反相重置信號RSTB,一汲極耦接節點306,以及一源極耦接參考電位VSS。因為反相重置信號RSTB初始為高準位,N通道裝置N2使節點306在N通道裝置N1不導通的狀態下仍為低準位。N通道裝置N2是用於確保或保證重置信號RST在前述狀態下仍為低準位。當輸入信號IN處於估算狀態,回歸邏輯’0’重置電路303維持其隔離狀態。Referring to Figures 3 and 4, in response to an estimated event generated when one or more of the input signals IN transitions to one of one or more estimated states, the return logic '0' estimation circuit 301 will precharge the input and output. The PCHG level is pulled low, causing the return logic '0' domino circuit 400 to transition to its latched state. Therefore, the inverter 401 pulls up the level of the output signal OUT, so that the P-channel device P3 is not turned on. The inverter 403 pulls down the level of the return logic '0' enable signal RT0E to turn on the P-channel device P1 and disable the N-channel device N1. Turning on the P-channel device P1 causes the node 310 to be coupled to the supply potential VDD. The non-conduction of the N-channel device N1 causes the reset signal RST to no longer be limited to a low level. The estimated state of the input signal IN causes the return logic '0' reset circuit 303 to transition to its isolated state, causing node 306 to isolate node 310. As a result, the reset node 306 is temporarily isolated, so the reset signal RST is not intentionally driven to any state. Since there is no other device function, the reset signal RST is still maintained at a low level. In another embodiment, another N-channel device N2 (indicated by a dashed line) is provided in the circuit of FIG. 4, and an inverter 405 is formed in the other half to maintain the low-level state of the reset signal RST. The N-channel device N2 has a gate receiving inverted reset signal RSTB, a drain coupled to the node 306, and a source coupled to the reference potential VSS. Since the inverted reset signal RSTB is initially at a high level, the N-channel device N2 causes the node 306 to remain at a low level in a state where the N-channel device N1 is not conducting. The N-channel device N2 is used to ensure or ensure that the reset signal RST is still at a low level in the aforementioned state. When the input signal IN is in the estimated state, the return logic '0' reset circuit 303 maintains its isolated state.
當供應給該回歸邏輯’0’重置電路303的每一個回歸邏輯’0’輸入信號IN都回歸到其預設狀態,回歸邏輯’0’重置電路303轉態到其重置狀態,產生一重置事件,其中,P通道裝置P1以及回歸邏輯’0’重置電路303一同將重置信號RST拉升為高準位。請注意,若所述電路具有N通道裝置N2,回歸邏輯’0’重置電路303需設計來對抗N通道裝置N2以拉升重置信號RST的準位。反相器405因而會拉低反相重置信號RSTB的準位,使P通道裝置P2導通。導通的P通道裝置P2會將預充輸入輸出端PCHG的電位拉升至其預設狀態。請注意,當供應給該回歸邏輯’0’重置電路303的每一個回歸邏輯’0’輸入信號IN都回到預設狀態,輸入信號IN不再處於一估算狀態,故回歸邏輯’0’估算電路301不再拉低預設輸入輸出端PCHG的準位。如此一來,P通道裝置P2將預充輸入輸出端PCHG的準位拉升回其預充狀態。當預充輸入輸出端PCHG的準位為高準位,反相器401令輸出信號OUT再次為低準位,以導通P通道裝置P3,維持預充輸入輸出端PCHG為高準位。反相器403將回歸邏輯’0’致能信號RT0E拉升為高準位以導通N通道裝置N1且使P通道裝置P1不導通。由於P通道裝置P1不導通,回歸邏輯’0’重置電路與供電電位VDD隔離,且不再拉升重置信號RST。此外,導通的N通道裝置N1會將重置信號RST拉到低準位,且反相器405會拉升反相重置信號RSTB為高準位,以令P通道裝置P2不導通(且在有供應N通道裝置N2的例子中,更包括使N通道裝置N2導通)。雖然P通道裝置P2不導通,半維持電路402會維持預充輸入輸出端PCHG為高準位。如此一來,回歸邏輯’0’骨牌電路400重置回其預置狀態,準備好迎接下一個估算事件。When the return signal '0' input signal IN supplied to the return logic '0' reset circuit 303 returns to its preset state, the return logic '0' reset circuit 303 transitions to its reset state, resulting in A reset event in which the P channel device P1 and the return logic '0' reset circuit 303 together pull the reset signal RST to a high level. Note that if the circuit has an N-channel device N2, the return logic '0' reset circuit 303 is designed to oppose the N-channel device N2 to pull up the level of the reset signal RST. The inverter 405 thus pulls down the level of the inverted reset signal RSTB to turn on the P-channel device P2. The turned-on P-channel device P2 pulls the potential of the pre-charge input and output terminal PCHG to its preset state. Please note that when the return signal '0' input signal IN supplied to the return logic '0' reset circuit 303 returns to the preset state, the input signal IN is no longer in an estimated state, so the return logic '0' The estimation circuit 301 no longer pulls down the level of the preset input and output terminal PCHG. In this way, the P channel device P2 pulls the level of the precharge input/output terminal PCHG back to its precharge state. When the level of the precharge input and output terminal PCHG is a high level, the inverter 401 causes the output signal OUT to be at a low level again to turn on the P channel device P3, and maintain the precharge input and output terminal PCHG at a high level. The inverter 403 pulls the return logic '0' enable signal RT0E to a high level to turn on the N-channel device N1 and disable the P-channel device P1. Since the P-channel device P1 is not turned on, the return logic '0' reset circuit is isolated from the supply potential VDD, and the reset signal RST is no longer pulled up. In addition, the turned-on N-channel device N1 pulls the reset signal RST to a low level, and the inverter 405 pulls the inverted reset signal RSTB to a high level to make the P-channel device P2 non-conductive (and In the example in which the N-channel device N2 is supplied, the N-channel device N2 is further turned on. Although the P-channel device P2 is not turned on, the semi-sustain circuit 402 maintains the pre-charge input and output terminal PCHG at a high level. As a result, the regression logic '0' domino circuit 400 is reset back to its preset state, ready for the next estimated event.
第5圖以時序圖圖解無時脈回歸邏輯’0’骨牌邏輯閘300的操作,其中根據一種實施方式將回歸邏輯’0’骨牌電路400用於實現回歸邏輯’0’骨牌電路305。第一狀態信號EVAL顯示該回歸邏輯’0’估算電路301的一估算狀態,該估算狀態的成立代表一估算事件的產生。第一狀態信號EVAL在該估算狀態成立時為高準位、並在該估算狀態不成立時為低準位。輸入信號IN之估算狀態的數量決定於回歸邏輯’0’骨牌電路305的邏輯功能設計。例如,若回歸邏輯’0’骨牌電路305設計為一邏輯或功能,則該些輸入信號IN中任一者或多個為高準位的狀況會分別對應一估算狀態。若回歸邏輯’0’骨牌電路305是設計來實現一邏輯及功能,則輸入信號IN只具有一個估算狀態;該估算狀態下,每一個輸入信號IN都為高準位。第二狀態信號RESET顯示回歸邏輯’0’重置電路303的一重置狀態;該重置狀態成立時,該第二狀態信號RESET為高準位;該重置狀態不成立時,該第二狀態信號RESET為低準位。所述重置狀態決定於回歸邏輯’0’重置電路303的設計以及供應給回歸邏輯’0’重置電路303的該些輸入信號IN之狀態。每當輸入信號IN為一種、或多種估算狀態的任一者,重置狀態不成立且回歸邏輯’0’重置電路303處於其隔離狀態。每當供應給回歸邏輯’0’重置電路303的每一個回歸邏輯’0’輸入信號IN回到邏輯’0’時,回歸邏輯’0’重置電路303處於其重置狀態。所述重置事件僅發生於回歸邏輯’0’致能信號RTOE為使P通道裝置P1導通的低準位、且回歸邏輯’0’重置電路303於其重置狀態時。少數應用倚賴估算與重置電路彼此間的設計。不論是雙配置、或非雙配置設計,在所有輸入信號IN都回歸邏輯’0’時,重置狀態成立,且估算狀態不成立。在雙配置與非雙配置設計下,估算狀態成立時,重置狀態皆不成立。非雙配置設計下,僅輸入信號IN的一子集合是供應給該回歸邏輯’0’重置電路303,重置狀態可能在估算狀態不成立時也不成立,且可能在估算狀態轉變為不成立後仍維持不成立。Figure 5 illustrates the operation of the clockless regression logic '0' domino logic gate 300 in a timing diagram in which the regression logic '0' domino circuit 400 is used to implement the regression logic '0' domino circuit 305 in accordance with one embodiment. The first state signal EVAL displays an estimated state of the regression logic '0' estimation circuit 301, the establishment of which represents the generation of an estimated event. The first state signal EVAL is a high level when the estimated state is established, and is a low level when the estimated state is not established. The number of estimated states of the input signal IN is determined by the logic function design of the regression logic '0' domino circuit 305. For example, if the regression logic '0' domino circuit 305 is designed to be a logic or function, the condition that any one or more of the input signals IN are at a high level will correspond to an estimated state, respectively. If the regression logic '0' domino circuit 305 is designed to implement a logic and function, the input signal IN has only one estimated state; in this estimated state, each input signal IN is at a high level. The second state signal RESET displays a reset state of the reset logic '0' reset circuit 303; when the reset state is established, the second state signal RESET is a high level; when the reset state is not established, the second state The signal RESET is at a low level. The reset state is determined by the design of the return logic '0' reset circuit 303 and the state of the input signals IN supplied to the return logic '0' reset circuit 303. Each time the input signal IN is any one of one or more of the estimated states, the reset state is not established and the return logic '0' reset circuit 303 is in its isolated state. Whenever the return signal '0' input signal IN supplied to the return logic '0' reset circuit 303 returns to logic '0', the return logic '0' reset circuit 303 is in its reset state. The reset event occurs only when the return logic '0' enable signal RTOE is a low level that turns P channel device P1 on, and the return logic '0' reset circuit 303 is in its reset state. A few applications rely on the design of the evaluation and reset circuits. Regardless of the dual configuration or the non-dual configuration design, when all input signals IN return to logic '0', the reset state is established and the estimation state is not established. In the dual configuration and non-dual configuration design, when the estimation state is established, the reset state is not established. In the non-dual configuration design, only a subset of the input signal IN is supplied to the return logic '0' reset circuit 303, and the reset state may not be true when the estimated state is not established, and may still be after the estimated state transitions to not established. Maintenance is not established.
第5圖包括信號EVAL、RESET、PCHG、OUT、RT0E、RST以及RSTB的時序圖。所示信號的轉態延遲僅為示意作用,並非意圖針對特定設計限定延遲時間。在初始時間T0,第一狀態信號EVAL為低準位,表示輸入信號IN並不處於估算狀態。第二狀態信號RESET在時序T0則為無意義信號。請注意,根據回歸邏輯’0’操作,輸入信號IN(至少該些為回歸邏輯’0’之信號)於一估算區間後、且下一個估算區間作用前,回歸為邏輯’0’。然而,各個輸入信號可能具有不同的時間延遲。當輸入信號IN全部設定為預設狀態,第一狀態信號EVAL為低準位且第二狀態信號RESET為高準位。若輸入信號中某一個或多個轉換為高準位但仍不符合估算狀態的條件(在下一次估算區間前),則第二狀態信號RESET可能在雙態間變換一或多次且同時第一狀態信號EVAL維持低準位。因此,第二狀態信號RESET如圖所示,不為特定狀態,此外,由於狀態回歸致能電路207(於回歸邏輯’0’例子中由P通道裝置P1實現)不作用,所述早於估算事件的任何雙態變化並不重要。信號PCHG、OUT、RT0E、RST以及RSTB在時間T0分別初始設定為邏輯’1’、’0’、’1’、’0’、以及’1’。Figure 5 contains timing diagrams for the signals EVAL, RESET, PCHG, OUT, RT0E, RST, and RSTB. The transition delay of the signal shown is for illustrative purposes only and is not intended to limit the delay time for a particular design. At the initial time T0, the first state signal EVAL is at a low level, indicating that the input signal IN is not in an estimated state. The second state signal RESET is a meaningless signal at timing T0. Note that, according to the regression logic '0' operation, the input signal IN (at least the signals of the regression logic '0') is returned to logic '0' after an estimation interval and before the next estimation interval. However, each input signal may have a different time delay. When the input signal IN is all set to the preset state, the first state signal EVAL is at a low level and the second state signal RESET is at a high level. If one or more of the input signals are converted to a high level but still do not meet the conditions of the estimated state (before the next estimation interval), the second state signal RESET may be toggled one or more times between the two states and simultaneously The status signal EVAL maintains a low level. Therefore, the second state signal RESET is not in a specific state as shown, and further, since the state regression enabling circuit 207 (implemented by the P channel device P1 in the regression logic '0' example) does not function, the prediction is earlier than the estimation. Any bimorphic change in an event is not important. The signals PCHG, OUT, RT0E, RST, and RSTB are initially set to logic '1', '0', '1', '0', and '1', respectively, at time T0.
接續的時間點T1,輸入信號IN一同進入一估算狀態,因此第一狀態信號EVAL拉高且第二狀態信號RESET拉低。回應高準位的第一狀態信號EVAL,回歸邏輯’0’估算電路301藉由在短暫延遲後的接續時間點T2拉低預充輸入輸出端PCHG電位,以引發一估算事件。由於第二狀態信號RESET為低準位,回歸邏輯’0’重置電路303處於其隔離狀態。回應被拉到低準位的預充輸入輸出信號PCHG,反相器401在短暫延遲後的接續時間點T3拉升輸出信號OUT的準位。隨著輸出信號OUT的拉升,反相器403在短暫延遲後的接續時間點T4拉低該回歸邏輯’0’致能信號RT0E的準位,以導通P通道裝置P1且不導通N通道裝置N1。因為回歸邏輯’0’重置電路303為不導通,重置信號RST不受任何裝置影響,且維持在低準位(或由N通道裝置N2維持在低準位)。無時脈回歸邏輯’0’骨牌邏輯閘300的狀態維持不變且第一狀態信號EVAL為高準位。在接續的時間點T5,輸入信號IN中一或多個信號改變其狀態,致使估算狀態不成立,相應之,第一狀態信號EVAL轉態為低準位。若供應給回歸邏輯’0’重置電路303的輸入信號各個也回到邏輯’0’,第二狀態信號RESET在時間點T5拉升如虛線501。若是非雙配置設計的實施例,第一狀態信號EVAL轉態至低準位、與第二狀態信號RESET轉態至高準位之間存在一延遲。必須注意的是,因為第一狀態信號EVAL為低準位,估算狀態不成立、且回歸邏輯’0’估算電路301在時間點T5後不再拉低預充輸入輸出信號PCHG。預充輸入輸出信號PCHG維持低準位,直至後續被P通道裝置P2拉升至高準位。請注意,另一個半維持電路(未在圖式中)可被用來在上述狀況中維持預充輸入輸出信號PCHG為低準位。At the subsequent time point T1, the input signal IN enters an estimated state together, so the first state signal EVAL is pulled high and the second state signal RESET is pulled low. In response to the high level first state signal EVAL, the return logic '0' estimation circuit 301 pulls down the precharge input and output PCHG potential by a continuation time point T2 after a short delay to initiate an estimation event. Since the second state signal RESET is at a low level, the return logic '0' reset circuit 303 is in its isolated state. In response to the precharge input and output signal PCHG pulled to the low level, the inverter 401 pulls up the level of the output signal OUT at the continuation time point T3 after the short delay. As the output signal OUT rises, the inverter 403 pulls down the level of the return logic '0' enable signal RT0E at the subsequent time T4 after the short delay to turn on the P channel device P1 and not turn on the N channel device. N1. Since the return logic '0' reset circuit 303 is non-conducting, the reset signal RST is not affected by any device and is maintained at a low level (or maintained at a low level by the N-channel device N2). The state of the clockless return logic '0' domino logic gate 300 remains unchanged and the first state signal EVAL is at a high level. At the subsequent time point T5, one or more signals in the input signal IN change its state, causing the estimation state to be unsatisfactory, and accordingly, the first state signal EVAL transitions to a low level. If the input signals supplied to the return logic '0' reset circuit 303 are each returned to the logic '0', the second state signal RESET is pulled up as indicated by the broken line 501 at the time point T5. In the case of a non-dual configuration design, there is a delay between the transition of the first state signal EVAL to the low level and the transition of the second state signal RESET to the high level. It must be noted that since the first state signal EVAL is at a low level, the estimation state is not established, and the return logic '0' estimation circuit 301 does not pull down the precharge input/output signal PCHG after the time point T5. The precharge input and output signal PCHG maintains a low level until it is subsequently pulled up to a high level by the P channel device P2. Please note that another semi-sustaining circuit (not shown) can be used to maintain the precharge input and output signal PCHG at a low level in the above conditions.
在時間點T5或接續的時間點T6,供應給回歸邏輯’0’重置電路303的輸入信號IN轉態為零,以啟動該回歸邏輯’0’重置電路303的重置狀態,使第二狀態信號RESET為高準位。所述回歸邏輯’0’重置電位303聯合P通道裝置P1,在短暫延遲後的時間點T7拉高重置信號RST的電位,以開始一重置事件。反相器405在短暫延遲後的時間點T8將反相重置信號RSTB拉低以回應之。反相重置信號RSTB轉態為低準位,以導通P通道裝置P2,在一短暫延遲後的時間點T9將預充輸入輸出信號PCGH拉升回預設狀態。當預充輸入輸出信號PCHG為高準位,反相器401在短暫延遲後的時間點T10將輸出信號OUT再次設定為低準位。轉態為低準位的輸出信號OUT會導通P通道裝置P3,使半維持電路402維持該預充輸入輸出信號PCHG為高準位直至下一個估算區間將之下拉。反相器403於短暫延遲後的時間點T11將回歸邏輯’0’致能信號RT0E拉到高準位。回歸邏輯’0’致能信號RT0E的高準位狀態會使N通道裝置N1導通、且使P通道裝置P1不導通。因為P通道裝置P1不導通,回歸邏輯’0’重置電路303不再拉升重置信號RST。N通道裝置N1之導通會使重置信號RST在短暫延遲後的時間點T12拉回低準位。反相器405會在短暫延遲後的時間點T13拉升反相重置信號RSTB至高準位,因此,P通道裝置P2不再拉升預充輸入輸出信號PCHG。此時,由半維持電路402維持預充輸入輸出PCHG為高準位。在時間點T13稍後的時間點T14,信號回復其預設狀態,回歸邏輯’0’估算電路301以及P通道裝置P1皆於其預設狀態,回歸邏輯’0’骨牌電路305回到其預置狀態,此外,假設輸入信號IN內每一個信號都是低準位,回歸邏輯’0’重置電路303處於其重置狀態。總結之,輸入信號IN的一估算狀態引發一估算事件,導致輸出信號OUT為高準位,且致能接續的重置事件。輸入信號IN的重置狀態導致回歸邏輯’0’重置電路303引發一重置事件,且無時脈回歸邏輯’0’骨牌邏輯閘300回到其初始狀態,準備迎接下一個估算區間。At the time point T5 or the subsequent time point T6, the input signal IN supplied to the return logic '0' reset circuit 303 is turned to zero to start the reset state of the return logic '0' reset circuit 303, so that The two-state signal RESET is at a high level. The return logic '0' reset potential 303, in conjunction with the P-channel device P1, pulls the potential of the reset signal RST high at a time point T7 after a brief delay to initiate a reset event. The inverter 405 pulls the inverted reset signal RSTB low in response to the short delay T8. The inverted reset signal RSTB transitions to a low level to turn on the P channel device P2, and pulls the precharge input and output signal PCGH back to a preset state at a time point T9 after a short delay. When the precharge input and output signal PCHG is at the high level, the inverter 401 sets the output signal OUT to the low level again at the time point T10 after the short delay. The output signal OUT, which is transitioned to a low level, turns on the P-channel device P3, causing the semi-sustain circuit 402 to maintain the pre-charge input and output signal PCHG at a high level until the next estimation interval will be pulled down. The inverter 403 pulls the return logic '0' enable signal RT0E to a high level at a time point T11 after a short delay. The high-level state of the return logic '0' enable signal RT0E turns on the N-channel device N1 and disables the P-channel device P1. Since the P channel device P1 is not turned on, the return logic '0' reset circuit 303 no longer pulls up the reset signal RST. The conduction of the N-channel device N1 causes the reset signal RST to be pulled back to the low level at a time point T12 after a short delay. The inverter 405 pulls up the inverted reset signal RSTB to a high level at a time point T13 after a short delay, and therefore, the P channel device P2 no longer pulls up the precharge input/output signal PCHG. At this time, the precharge input/output PCHG is maintained at a high level by the half sustain circuit 402. At a later time point T14 at time point T13, the signal returns to its preset state, and the return logic '0' estimation circuit 301 and the P channel device P1 are in their preset states, and the return logic '0' domino circuit 305 returns to its pre-predetermined state. The state is set. Further, assuming that each signal in the input signal IN is at a low level, the return logic '0' reset circuit 303 is in its reset state. In summary, an estimated state of the input signal IN triggers an estimated event, causing the output signal OUT to be at a high level and enabling a subsequent reset event. The reset state of the input signal IN causes the return logic '0' reset circuit 303 to initiate a reset event, and the clockless return logic '0' domino logic gate 300 returns to its initial state, ready for the next estimated interval.
如圖所示,第二狀態信號RESET為高準位直至時間點T11。時間點T11時,回歸邏輯’0’致能信號RT0E轉態為高準位以確定該無時脈回歸邏輯’0’骨牌邏輯閘回到其初始狀態,且至此之後,第二狀態信號RESET為無意義。請注意,重置信號RST於時間點T7拉到高準位時,即使重置狀態不成立且拉低第二狀態信號RESET,重置信號RST仍維持在高準位,原因是N通道裝置N1仍為不導通,無法影響重置信號RST。因此,雖然重置狀態應當被維持成立直至回歸邏輯’0’致能信號RT0E轉態為高準位,輸入信號可於時間點T7後與時間點T11前拉低第二狀態信號RESET的準位而不產生影響,因此,可維持適當的電路操作。一旦回歸邏輯’0’致能信號RT0E為高準位,P通道裝置P1不導通,且任何的輸入信號IN的無意義轉態在時間點T11後都無作用。非上述無意義轉態的狀況則可能另外引發一估算狀態。請注意,狀態回歸信號RTS可能不存在無意義轉態。然而,某些輸入信號,可能為非狀態回歸信號、且可能具有無意義轉態。供應給回歸邏輯’0’估算電路301的輸入信號IN是被選擇來避免潛在的估算狀態發生。As shown, the second state signal RESET is at a high level until time T11. At time T11, the return logic '0' enable signal RT0E transitions to a high level to determine that the clockless return logic '0' domino logic gate returns to its initial state, and thereafter, the second state signal RESET is Meaningless. Please note that when the reset signal RST is pulled to the high level at the time point T7, even if the reset state is not established and the second state signal RESET is pulled low, the reset signal RST is maintained at the high level because the N-channel device N1 is still It is not conductive and cannot affect the reset signal RST. Therefore, although the reset state should be maintained until the return logic '0' enable signal RT0E transitions to the high level, the input signal can pull the level of the second state signal RESET after the time point T7 and before the time point T11. Without impact, therefore, proper circuit operation can be maintained. Once the return logic '0' enable signal RT0E is at a high level, the P channel device P1 is not conducting, and any meaningless transition of the input signal IN has no effect after the time point T11. A situation other than the above meaningless transition may additionally trigger an estimated state. Please note that the state regression signal RTS may not have a meaningless transition. However, some input signals may be non-state regression signals and may have meaningless transitions. The input signal IN supplied to the regression logic '0' estimation circuit 301 is selected to avoid the occurrence of a potential estimation state.
第6圖為一示意方塊圖,圖解一無時脈回歸邏輯’0’骨牌邏輯閘600,用以實現一邏輯或閘,對M個回歸邏輯’0’的輸入信號I1…IM作邏輯或運算,其中,M為大於1的正整數。在這樣的實施方式中,輸入信號I1…IM皆是回歸邏輯’0’信號。無時脈回歸邏輯’0’骨牌邏輯閘600包括回歸邏輯’0’骨牌電路305。該回歸邏輯’0’骨牌電路305耦接一回歸邏輯’0’估算電路601(用以實現回歸邏輯’0’估算電路301),且耦接一回歸邏輯’0’重置電路603(用以實現回歸邏輯’0’重置電路303)。回歸邏輯’0’估算電路601包括M個N通道裝置NA…NM,各自以汲極耦接節點302,且各自以源極耦接參考電位VSS。N通道裝置NA…NM各自具有一閘極,如圖所示對應接收輸入信號I1…IM。類似地,回歸邏輯’0重置電路603包括M個P通道裝置PA…PM,串接於第二重置節點310以及重置節點306之間。如圖所示,其中第一個P通道裝置PA與P通道裝置P1的汲極耦接在節點310,至於P通道裝置PA的汲極則耦接下一個P通道裝置的源極。依照此串接規則,其中最後一個P通道裝置PM以其汲極耦接節點306。P通道裝置PA…PM各自如圖所示以閘極接收輸入信號I1…IM其中之一。雖然圖示中僅繪製複數個N通道裝置NA…NM中的兩個裝置NA與NM、複數個P通道裝置PA…PM中的兩個裝置PA與PM、複數個輸入信號I1…IM中的兩個信號I1與IM,必須了解的是,任何數量的所述裝置以及信號都可能為其實施方式(例如,供應給N通道裝置NB與P通道裝置PB之閘極的輸入信號I2…等)。Figure 6 is a schematic block diagram illustrating a clockless regression logic '0' domino logic gate 600 for implementing a logic or gate, logically ORing the input signals I1...IM of the M regression logic '0' Where M is a positive integer greater than one. In such an embodiment, the input signals I1...IM are all regression logic '0' signals. The clockless return logic '0' domino logic gate 600 includes a return logic '0' domino circuit 305. The regression logic '0' domino circuit 305 is coupled to a regression logic '0' estimation circuit 601 (to implement the regression logic '0' estimation circuit 301), and coupled to a regression logic '0' reset circuit 603 (for A regression logic '0' reset circuit 303 is implemented. The regression logic '0' estimation circuit 601 includes M N-channel devices NA...NM, each of which is coupled to the node 302 with a drain, and each of which is coupled to the reference potential VSS with a source. The N-channel devices NA...NM each have a gate corresponding to the received input signals I1...IM as shown. Similarly, the return logic '0 reset circuit 603 includes M P channel devices PA...PM connected in series between the second reset node 310 and the reset node 306. As shown, the first P-channel device PA and the P-channel device P1 are coupled to the node 310, and the P-channel device PA is coupled to the source of the next P-channel device. In accordance with this concatenation rule, the last P-channel device PM is coupled to node 306 with its drain. The P channel devices PA...PM each receive one of the input signals I1...IM as a gate as shown. Although only two of the plurality of N-channel devices NA...NM, NA and NM, two of the plurality of P-channel devices PA...PM, PA, and two of the plurality of input signals I1...IM are drawn in the illustration. Signals I1 and IM, it must be understood that any number of such devices and signals may be their implementation (e.g., input signals I2 to the gates of N-channel devices NB and P-channel devices PB, etc.).
無時脈回歸邏輯’0’骨牌邏輯閘600為雙配置設計的一種實施方式,其中回歸邏輯’0’重置電路603為回歸邏輯’0估算電路601的雙配置設計。在雙配置設計下,供應給回歸邏輯’0’估算電路601與回歸邏輯’0’重置電路603的信號都是輸入信號I1…IM。無時脈回歸邏輯’0’骨牌邏輯閘600的操作通常符合第5圖所示的時序圖。在這樣的狀態下,當輸入信號I1…IM根據回歸邏輯’0’操作皆為邏輯’0’,第一狀態信號EVAL為低準位且第二狀態信號RESET為高準位。當輸入信號I1…IM中任一者為高準位,估算狀態成立,且重置狀態不成立;因此,第一狀態信號EVAL為高準位狀態、且第二狀態信號RESET為低準位狀態。因為電路601與603為雙配置設計,隨著輸入信號IN的轉態切換,第一狀態信號EVAL與第二狀態信號RESET會跟著切換且維持為彼此的反相。隨著輸入信號IN中任一者轉態為邏輯’1’,預充輸入輸出信號PCHG轉態為低準位,輸出信號OUT在短暫延遲後轉態為高準位,且回歸邏輯’0’致能信號RT0E在另一段短暫延遲後轉態為低準位以致能一重置事件。當輸入信號I1…IM各個根據回歸邏輯’0’操作回到邏輯’0’時,回歸邏輯’0’重置電路603引發該重置事件,令重置信號RST轉態為高準位,反相重置信號RSTB轉態為低準位,預充輸入輸出信號PCHG拉高為高準位、且輸出信號OUT如前所述回到低準位。The clockless regression logic '0' domino logic gate 600 is an embodiment of a dual configuration design in which the return logic '0' reset circuit 603 is a dual configuration design of the regression logic '0 estimation circuit 601. In the dual configuration design, the signals supplied to the return logic '0' estimation circuit 601 and the return logic '0' reset circuit 603 are both input signals I1...IM. The operation of the clockless return logic '0' domino logic gate 600 generally conforms to the timing diagram shown in FIG. In such a state, when the input signals I1...IM are all logical "0" according to the return logic '0', the first state signal EVAL is at a low level and the second state signal RESET is at a high level. When any of the input signals I1...IM is at a high level, the estimated state is established and the reset state is not established; therefore, the first state signal EVAL is in the high level state and the second state signal RESET is in the low level state. Because the circuits 601 and 603 are of a dual configuration design, as the input signal IN switches, the first state signal EVAL and the second state signal RESET are switched and maintained in phase with each other. As any of the input signals IN transitions to a logic '1', the precharge input and output signal PCHG transitions to a low level, and the output signal OUT transitions to a high level after a short delay, and the return logic is '0'. The enable signal RT0E transitions to a low level after another short delay to enable a reset event. When the input signals I1...IM are each returned to logic '0' according to the return logic '0', the return logic '0' reset circuit 603 triggers the reset event, causing the reset signal RST to transition to a high level, The phase reset signal RSTB transitions to a low level, the precharge input and output signal PCHG is pulled high to a high level, and the output signal OUT returns to a low level as previously described.
在某些設計中,回歸邏輯’0’重置電路603內所串接的P通道裝置之數量受限為特定數量,以確保適當操作。例如,在某一實施方式中,允許串接於供電電位VDD與重置節點306間的P通道裝置之最高數量為4,輸入信號的數量因而被限制為3(M為3)。為了對大量的輸入信號進行邏輯或運算,可將多個無時脈回歸邏輯’0’骨牌邏輯閘600結合或串疊在一起,藉由大量的邏輯閘對任何數量的輸入信號進行邏輯或運算,以下詳述之。In some designs, the number of P-channel devices cascaded within the return logic '0' reset circuit 603 is limited to a particular number to ensure proper operation. For example, in one embodiment, the maximum number of P-channel devices allowed to be connected in series between the supply potential VDD and the reset node 306 is 4, and the number of input signals is thus limited to 3 (M is 3). In order to perform a logical OR operation on a large number of input signals, a plurality of clockless regression logic '0' domino logic gates 600 may be combined or cascaded together, and a logical OR operation is performed on any number of input signals by a large number of logic gates. , detailed below.
第7圖一簡化方塊圖,圖解三個無時脈狀態回歸骨牌邏輯閘701、703與705所組成的一聯合邏輯閘設計700,用以實現一邏輯運算。聯合邏輯閘設計700如圖所示為狀態回歸型式,且可應用於任何回歸邏輯’0’或回歸邏輯’1’應用。在一種實施方式中,六個輸入信號I1…I6經邏輯運算後產生一狀態回歸輸出信號OUT。輸入信號I1…I3中至少一個或上至全數都是狀態回歸信號,且輸入信號I4…I6中至少一個或上至全數都是狀態回歸信號。聯合邏輯閘設計700包括兩個三輸入無時脈狀態回歸骨牌邏輯閘701以及703、以及另一個雙輸入狀態回歸骨牌邏輯閘705。狀態回歸骨牌邏輯閘701接收輸入信號I1…I3且供應一狀態回歸輸出信號O1(RTS),作為狀態回歸骨牌邏輯閘705的一輸入信號。同樣地,狀態回歸骨牌邏輯閘703接收輸入信號I4…I6且供應一狀態回歸輸出信號O2(RTS),作為狀態回歸骨牌邏輯閘705的另一個輸入信號。狀態回歸骨牌邏輯閘705在其輸出端供應狀態回歸輸信號OUT(RTS)。如此一來,多個無時脈狀態回歸骨牌邏輯閘可被結合或串疊在一起,以應付大量的輸入信號,完成一特定邏輯運算。此外,尚有其他設計可完成同樣運算。例如,以三個雙輸入邏輯閘實現第一級結構,各自接收六個輸入信號中的兩個信號,且各自產生一個輸出信號,以聯合作為一個三輸入邏輯閘的輸入信號。或者,所述技術也可應用來實現其他數量的輸入信號之邏輯運算,上述為數6個的輸入信號僅是說明使用。Figure 7 is a simplified block diagram illustrating a joint logic gate design 700 consisting of three clockless state regression domino logic gates 701, 703 and 705 for implementing a logic operation. The joint logic gate design 700 is shown as a state regression pattern and can be applied to any regression logic '0' or regression logic '1' application. In one embodiment, the six input signals I1...I6 are logically operated to produce a state regression output signal OUT. At least one or all of the input signals I1...I3 are state regression signals, and at least one or all of the input signals I4...I6 are state regression signals. The joint logic gate design 700 includes two three-input no-cycle state return domino logic gates 701 and 703, and another dual input state return domino logic gate 705. The state return domino logic gate 701 receives the input signals I1...I3 and supplies a state regression output signal O1 (RTS) as an input signal for the state return domino logic gate 705. Similarly, state return domino logic gate 703 receives input signals I4...I6 and supplies a state regression output signal O2 (RTS) as another input signal for state return domino logic gate 705. The state return domino logic gate 705 supplies a state return signal OUT (RTS) at its output. In this way, multiple clockless state return domino logic gates can be combined or stacked to cope with a large number of input signals to perform a specific logic operation. In addition, there are other designs that do the same. For example, the first stage structure is implemented with three dual input logic gates, each receiving two of the six input signals, and each generating an output signal to combine as an input signal to a three input logic gate. Alternatively, the techniques can be applied to implement logical operations of other numbers of input signals, and the six input signals described above are for illustrative purposes only.
所述聯合邏輯閘設計700內的邏輯閘701、703與705分別可根據不同的邏輯運算需求─例如,邏輯及(AND)、邏輯或(OR)、邏輯非及(NAND)、邏輯非或(NOR)、邏輯異或(XOR)…等或任何所述邏輯運算之集合─配合適當或可用的輸入信號實現。例如,關於信號A與信號B之邏輯異或運算─XOR(A,B)─的一邏輯異或閘,狀態回歸輸入信號A與B以及其反相信號A’與B’(標號「’」代表為反相信號)需被供應。聯合邏輯閘設計700中的邏輯閘701、703與705可執行不同的運算。雖然圖中僅顯示三個邏輯閘,必須聲明的是,任何數量的邏輯閘都可基於本技術領域者熟知之技術串聯、並聯、或以其他方式結合在一起。例如,邏輯閘701、703與705各自可依無時脈回歸邏輯’0’骨牌邏輯電路600實現為一邏輯或閘。在這樣的實施方式中,邏輯閘701設計為一邏輯或閘,對輸入信號I1…I3作邏輯或運算,以供應輸出信號O1;邏輯閘703設計為一邏輯或閘,對輸入信號I4…I6做邏輯或運算,以供應輸出信號O2;且邏輯閘705設計為一邏輯或閘,對信號O1與O2做邏輯或運算,以產生輸出信號OUT。如此一來,大量的無時脈回歸邏輯’0’骨牌邏輯閘可被結合或串疊在一起,應付大量的輸入信號之邏輯運算,例如,實現一邏輯或運算。The logic gates 701, 703, and 705 within the joint logic gate design 700 can each be based on different logic operation requirements - for example, logical AND, OR, NAND, logic, or ( NOR), logical exclusive OR (XOR), etc. or any collection of such logical operations - implemented with appropriate or available input signals. For example, a logical exclusive OR operation of the signal A and the signal B - XOR (A, B) - a state exclusive return input signal A and B and its inverted signals A' and B' (labeled "'" The representative is the inverted signal) needs to be supplied. The logic gates 701, 703, and 705 in the joint logic gate design 700 can perform different operations. Although only three logic gates are shown in the figures, it must be stated that any number of logic gates can be connected in series, in parallel, or otherwise combined based on techniques well known to those skilled in the art. For example, each of the logic gates 701, 703, and 705 can be implemented as a logic or gate in accordance with the clockless return logic '0' domino logic circuit 600. In such an embodiment, the logic gate 701 is designed as a logic or gate, logically ORing the input signals I1...I3 to supply the output signal O1; the logic gate 703 is designed as a logic or gate, and the input signals I4...I6 A logical OR operation is performed to supply the output signal O2; and the logic gate 705 is designed as a logic or gate, and a logical OR operation is performed on the signals O1 and O2 to generate an output signal OUT. As a result, a large number of clockless regression logic '0' domino logic gates can be combined or cascaded to handle a large number of logical operations of the input signal, for example, to implement a logical OR operation.
第8圖為一方塊圖,圖解一無時脈回歸邏輯’0’骨牌邏輯閘800,其中根據本發明另一種實施方式實現混雜的邏輯運算。無時脈回歸邏輯’0’骨牌邏輯閘800包括上述回歸邏輯’0’骨牌電路305。該回歸邏輯’0’骨牌電路305耦接一回歸邏輯’0’估算電路801(用以實現該回歸邏輯’0’估算電路301)以及一回歸邏輯’0’重置電路803(用以實現該回歸邏輯’0’重置電路303)。回歸邏輯’0’估算電路801包括三個N通道裝置NA、NB與NC,各自以汲極耦接節點302,且各自以源極耦接一中繼節點802。回歸邏輯’0’估算電路801更包括兩個N通道裝置ND與NE,各自以汲極耦接節點802,且各自以源極耦接參考電位VSS。N通道裝置NA…NE分別以閘極接收五個輸入信號I1…I5。在這個實施例中,回歸邏輯’0’估算電路801執行一邏輯運算,使OUT=(I1|I2|I3)&(I4|I5),其中,符號「|」代表的是邏輯或運算,且符號「&」代表的是邏輯及運算。一估算狀態發生於輸入信號I1…I3中任一者為高準位、且輸入信號I4與I5中至少有一個為高準位時。回歸邏輯’0’重置電路803包括兩個P通道裝置PA與PB,串接於P通道裝置P1之汲極與重置節點306之間,且與P通道裝置P1之汲極耦接於節點310。特別說明的是,P通道裝置PA以源極耦接P通道裝置P1之汲極,且以汲極耦接P通道裝置PB之源極,且P通道裝置PB以汲極耦接該重置節點306。輸入信號I4供應給P通道裝置PA之閘極使用,且輸入信號I5供應給P通道裝置PB之閘極使用。在這個實施例中,重置狀態僅在輸入信號I4與I5同為低準位時發生。輸入信號I4與I5為回歸邏輯’0’信號;至於輸入信號I1…I3則可為回歸邏輯’0’信號但無需一定為回歸邏輯’0’信號。雖然狀態回歸信號為預期設定,但在某些設計中,結合非狀態回歸信號與狀態回歸信號可能是相當有用的設計。所述非狀態回歸信號可能需要符合某些相對於該些狀態回歸信號的時間條件。例如,在一種實施方式中,非狀態回歸信號可能是對應狀態回歸信號而設定或維持。Figure 8 is a block diagram illustrating a clockless regression logic '0' domino logic gate 800 in which a hybrid logic operation is implemented in accordance with another embodiment of the present invention. The clockless regression logic '0' domino logic gate 800 includes the above-described regression logic '0' domino circuit 305. The regression logic '0' domino circuit 305 is coupled to a regression logic '0' estimation circuit 801 (to implement the regression logic '0' estimation circuit 301) and a regression logic '0' reset circuit 803 (to achieve the Regression logic '0' resets circuit 303). The regression logic '0' estimation circuit 801 includes three N-channel devices NA, NB and NC, each of which is coupled to the node 302 with a drain, and each of which is coupled to a relay node 802 by a source. The regression logic '0' estimation circuit 801 further includes two N-channel devices ND and NE, each of which is coupled to the node 802 with a drain, and each of which is coupled to the reference potential VSS with a source. The N channel devices NA...NE receive five input signals I1...I5 at the gates, respectively. In this embodiment, the regression logic '0' estimation circuit 801 performs a logic operation such that OUT = (I1 | I2 | I3) & (I4 | I5), wherein the symbol "|" represents a logical OR operation, and The symbol "&" represents a logical sum operation. An estimated state occurs when any of the input signals I1...I3 is at a high level and at least one of the input signals I4 and I5 is at a high level. The return logic '0' reset circuit 803 includes two P channel devices PA and PB connected in series between the drain of the P channel device P1 and the reset node 306, and is coupled to the node of the P channel device P1. 310. Specifically, the P-channel device PA is coupled to the drain of the P-channel device P1 by a source, and is coupled to the source of the P-channel device PB by a drain, and the P-channel device PB is coupled to the reset node by a drain. 306. The input signal I4 is supplied to the gate of the P channel device PA, and the input signal I5 is supplied to the gate of the P channel device PB. In this embodiment, the reset state occurs only when the input signals I4 and I5 are both at a low level. Input signals I4 and I5 are regression logic '0' signals; input signals I1...I3 may be regression logic '0' signals but need not necessarily be regression logic '0' signals. Although the state regression signal is the expected setting, in some designs, combining non-state regression signals with state regression signals can be a quite useful design. The non-state regression signal may need to meet certain time conditions relative to the state regression signals. For example, in one embodiment, the non-state regression signal may be set or maintained corresponding to a state regression signal.
無時脈回歸邏輯’0’骨牌邏輯閘800的操作一般符合第5圖所示之時序圖。在這樣的實施例中,估算狀態在輸入信號I1…I3終至少一者為高準位且輸入信號I4與I5至少一者為高準位時成立,所述估算狀態於時間點T1引發估算事件。參考先前敘述,回應所述估算事件,預充輸入輸出信號PCHG轉態為低準位,接著,輸出信號OUT轉態為高準位,再來,回歸邏輯’0’致能信號RT0E轉態為低準位;所述轉態分別間隔一短暫延遲。所述估算狀態成立的區間內,第一狀態信號EVAL維持高準位。重置狀態僅在輸入信號I4與I5皆設定為低準位時成立。由於輸入信號I4與I5中有任一為高準位時該第二狀態信號RESET就會維持在低準位,因此,第二狀態信號RESET在第一狀態信號EVAL為高準位時維持在低準位。當第一狀態信號EVAL在時間點T5轉態為低準位時,若輸入信號I4與I5同時為低準位,第二狀態信號RESET才會轉態為高準位。在時間點T5,若輸入信號I4與I5都轉態為低準位,則第二狀態信號RESET可轉態為高準位,但第二狀態信號RESET也有可能維持在低準位更久的時間。例如,若輸入信號I1…I3全都轉態為低準位、且輸入信號I4與I5任一維持為高準位,則第二狀態信號RESET在第一狀態信號EVAL轉態為低準位時仍不轉態至高準位。待輸入信號I4與I5根據回歸邏輯’0’操作皆為低準位(例如,參考第5圖時間點T6)則第二狀態信號RESET轉態為高準位且回歸邏輯’0’重置電路803進入其重置狀態,以引發重置事件。如先前所敘述內容,回應所述重置事件,重置信號RST轉態為高準位,反相重置信號RSTB轉態為低準位,預充輸入輸出信號PCHG轉態回高準位,且輸出信號OUT轉態回低準位,上述轉態各自間隔一短暫延遲。The operation of the clockless return logic '0' domino logic gate 800 generally conforms to the timing diagram shown in FIG. In such an embodiment, the estimated state is established when at least one of the input signals I1...I3 is at a high level and at least one of the input signals I4 and I5 is at a high level, the estimated state triggering an estimated event at time T1 . Referring to the foregoing description, in response to the estimated event, the precharge input and output signal PCHG transitions to a low level, and then, the output signal OUT transitions to a high level, and then, the return logic '0' enable signal RT0E transitions to Low level; the transitions are separated by a short delay. The first state signal EVAL maintains a high level in the interval in which the estimated state is established. The reset state is established only when the input signals I4 and I5 are both set to a low level. The second state signal RESET is maintained at a low level because any of the input signals I4 and I5 is at a high level. Therefore, the second state signal RESET is maintained low when the first state signal EVAL is at a high level. Level. When the first state signal EVAL transitions to the low level at the time point T5, if the input signals I4 and I5 are simultaneously at the low level, the second state signal RESET will transition to the high level. At the time point T5, if the input signals I4 and I5 are both turned to the low level, the second state signal RESET can be turned to the high level, but the second state signal RESET is also likely to remain at the low level for a longer time. . For example, if the input signals I1...I3 are all turned to the low level and any of the input signals I4 and I5 are maintained at the high level, the second state signal RESET remains when the first state signal EVAL transitions to the low level. Do not turn to high level. The input signals I4 and I5 are all low level according to the return logic '0' operation (for example, refer to the time point T6 of FIG. 5), then the second state signal RESET transitions to a high level and the return logic '0' resets the circuit. 803 enters its reset state to cause a reset event. As described above, in response to the reset event, the reset signal RST transitions to a high level, the inverted reset signal RSTB transitions to a low level, and the precharge input and output signal PCHG transitions back to a high level. And the output signal OUT is turned back to the low level, and the above transition states are each delayed by a short delay.
無時脈回歸邏輯’0’骨牌邏輯閘800為一非雙配置實施方式,其中回歸邏輯’0’重置電路803並非回歸邏輯’0’估算電路801的雙配置設計。在這個實施例中,輸入信號I1…I5中僅有一個子集合─輸入信號I4與I5─是供應給該回歸邏輯’0’重置電路803。然而,由於估算狀態僅成立在輸入信號I4與I5至少一者為高準位時,因此,回歸邏輯’0’估算電路801為其估算狀態時,回歸邏輯’0’重置電路803必然處於其隔離狀態,可確保適當的操作。特別是,在所述估算事件開始時,回歸邏輯’0’重置電路803處於其隔離狀態,且該回歸邏輯’0’骨牌電路305轉態為其閂鎖狀態導通P通道裝置P1。重置信號RST在所述估算條件下不受任何裝置決定電位。當輸入信號I4與I5根據回歸邏輯’0’操作皆轉態為低準位,回歸邏輯’0’估算電路801脫離其估算狀態、且回歸邏輯’0’電路803進入其重置狀態引發一重置事件。所述重置事件使該回歸邏輯’0’骨牌電路305轉態回其預置狀態,使P通道裝置P1不導通,且接著拉低重置信號RST的準位,以準備迎接下一個估算事件。The clockless regression logic '0' domino logic gate 800 is a non-dual configuration implementation in which the return logic '0' reset circuit 803 is not a dual configuration design of the return logic '0' estimation circuit 801. In this embodiment, only a subset of the input signals I1 ... I5 - input signals I4 and I5 - are supplied to the return logic '0' reset circuit 803. However, since the estimation state is only established when at least one of the input signals I4 and I5 is at a high level, therefore, when the regression logic '0' estimation circuit 801 is in its estimated state, the return logic '0' reset circuit 803 is necessarily in its Isolation status ensures proper operation. In particular, at the beginning of the estimation event, the return logic '0' reset circuit 803 is in its isolated state, and the return logic '0' domino circuit 305 transitions to its latched state to turn on the P channel device P1. The reset signal RST is not subject to any device determining potential under the estimated conditions. When the input signals I4 and I5 are all converted to a low level according to the return logic '0' operation, the regression logic '0' estimation circuit 801 is out of its estimated state, and the return logic '0' circuit 803 enters its reset state, causing a heavy Set the event. The reset event causes the regression logic '0' domino circuit 305 to transition back to its preset state, causing the P channel device P1 to be non-conducting, and then lowering the level of the reset signal RST to prepare for the next estimated event. .
無時脈回歸邏輯’0’骨牌邏輯閘800之邏輯運算可用於類似聯合邏輯閘設計700的聯合邏輯閘結構。例如,邏輯閘701可由一個三輸入邏輯或閘實現,接收輸入信號I1…I3,以供應一輸出信號O1。邏輯閘703可由一個雙輸入邏輯或閘實現,以接收兩個輸入信號I4與I5以供應一輸出信號O2。邏輯閘705可由一個雙輸入邏輯及閘實現,以對信號O1與O2作邏輯及運算。如此一來,聯合結構將實現邏輯運算(II|I2|I3)&(I4|I5)。在另一種架構中,可更提供第三個P通道裝置(未顯示在圖中)串接在節點310與306之間。串接的三個P通道裝置用於分別接收輸入信號I1、I2與I3。所得到的操作是等效的,縱使,相對於兩個輸入信號的狀態(I4與I5),三個輸入信號的狀態(I1、I2與I3)可能會使回歸邏輯’0’骨牌電路305由閂鎖狀態轉態回預置狀態所耗費的時間略久。The logic operation of the clockless regression logic '0' domino logic gate 800 can be used for a joint logic gate structure similar to the joint logic gate design 700. For example, logic gate 701 can be implemented by a three-input logic or gate that receives input signals I1...I3 to supply an output signal O1. Logic gate 703 can be implemented by a dual input logic or gate to receive two input signals I4 and I5 to supply an output signal O2. The logic gate 705 can be implemented by a dual input logic and gate to logically AND the signals O1 and O2. As a result, the joint structure will implement logical operations (II|I2|I3)&(I4|I5). In another architecture, a third P-channel device (not shown) may be provided in series between nodes 310 and 306. The three P-channel devices connected in series are used to receive the input signals I1, I2 and I3, respectively. The resulting operation is equivalent, even though the states of the three input signals (I1, I2, and I3) may cause the return logic '0' domino circuit 305 to be relative to the state of the two input signals (I4 and I5). It takes a little longer for the latch state to transition back to the preset state.
第9圖為一示意方塊圖,圖解一無時脈回歸邏輯’0’骨牌邏輯閘900,其中實現一邏輯及閘,對M個回歸邏輯’0’輸入信號I1…IM進行邏輯及運算。在這樣的邏輯及實施例中,輸入信號I1…IM各個都是回歸邏輯’0’信號。無時脈回歸邏輯’0’骨牌邏輯閘900包括所述回歸邏輯’0’骨牌電路305,耦接回歸邏輯’0’估算電路901(實現所述回歸邏輯’0’估算電路301)以及一回歸邏輯’0’重置電路903(實現所述回歸邏輯’0’估算電路303)。回歸邏輯’0’估算電路901包括M個N通道裝置NA…NM,串接於預充輸入輸出節點302以及參考電位VSS之間。如圖所示,N通道裝置NA的汲極耦接節點302,且其源極耦接串列中下一個N通道裝置的汲極,並遵循此規則直至最後一級N通道裝置NM,並將N通道裝置NM的源極耦接參考電位VSS。如圖所示,N通道裝置NA…NM各自提供閘極接收輸入信號I1…IM。對應地,回歸邏輯’0’重置電路903包括M個P通道裝置PA…PM並聯於節點310與重置節點306之間。特別是,P通道裝置PA…PM的源極乃耦接節點310,且汲極乃耦接重置節點306。Figure 9 is a schematic block diagram illustrating a clockless regression logic '0' domino logic gate 900 in which a logic AND gate is implemented to logically AND the M regression logic '0' input signals I1...IM. In such logic and embodiments, the input signals I1...IM are each a return logic '0' signal. The clockless regression logic '0' domino logic gate 900 includes the regression logic '0' domino circuit 305, coupled to the regression logic '0' estimation circuit 901 (implementing the regression logic '0' estimation circuit 301) and a regression A logic '0' reset circuit 903 (implementing the regression logic '0' estimation circuit 303). The regression logic '0' estimation circuit 901 includes M N channel devices NA...NM connected in series between the precharge input and output node 302 and the reference potential VSS. As shown, the drain of the N-channel device NA is coupled to node 302, and its source is coupled to the drain of the next N-channel device in the series, and follows this rule until the last stage N-channel device NM, and will N The source of the channel device NM is coupled to the reference potential VSS. As shown, the N-channel devices NA...NM each provide a gate receive input signal I1...IM. Correspondingly, the regression logic '0' reset circuit 903 includes M P channel devices PA...PM connected in parallel between the node 310 and the reset node 306. In particular, the source of the P-channel device PA...PM is coupled to the node 310, and the drain is coupled to the reset node 306.
無時脈回歸邏輯’0’骨牌邏輯閘900為另一種雙配置設計的實施例。無時脈回歸邏輯’0’骨牌邏輯閘900的操作一般是符合第5圖所揭露之時序圖。在這樣的實施例中,估算狀態是在所有的輸入信號I1…IM都為高準位時成立,此時,N通道裝置NA…NM全數導通,一同將預充輸入輸出端PCHG拉到參考電位VSS。當輸入信號I1…IM中任一者為低準位時,重置狀態成立。這個實施方式中,回歸邏輯’0’估算與重置電路901與903彼此為雙配置設計。根據各種應用,所述邏輯閘可設計為接收多種數量的輸入信號。然而,如先前關於無時脈回歸邏輯’0’骨牌邏輯閘600的討論,為了確保操作正確度,串接在回歸邏輯’0’估算電路901內的N通道裝置之數量會限定在特定數量內。The clockless regression logic '0' domino logic gate 900 is an embodiment of another dual configuration design. The operation of the clockless regression logic '0' domino logic gate 900 is generally in accordance with the timing diagram disclosed in FIG. In such an embodiment, the estimated state is established when all of the input signals I1...IM are at a high level. At this time, the N-channel devices NA...NM are all turned on, and the pre-charge input/output terminal PCHG is pulled to the reference potential together. VSS. When any of the input signals I1...IM is at a low level, the reset state is established. In this embodiment, the regression logic '0' estimation and reset circuits 901 and 903 are of a dual configuration design with each other. Depending on the application, the logic gate can be designed to receive a variety of input signals. However, as previously discussed with respect to the clockless regression logic '0' domino logic gate 600, to ensure operational accuracy, the number of N-channel devices cascaded within the regression logic '0' estimation circuit 901 is limited to a certain number. .
如先前所討論的聯合邏輯閘設計700,無時脈回歸邏輯’0’骨牌邏輯閘900可採用串疊技術,以多重邏輯及閘實現任何數量之輸入信號的邏輯及運算。邏輯閘701、703與705各個可參照無時脈回歸邏輯’0’骨牌邏輯閘900實現為一邏輯及閘。在一種實施方式中,邏輯閘701設計為一邏輯及閘,用以對輸入信號I1…I3作邏輯及運算,以產生信號O1;邏輯閘703設計為一邏輯及閘,對輸入信號I4…I6做邏輯及運算,以產生信號O2;邏輯閘705設計為一邏輯及閘,對信號O1與O2作邏輯及運算,以產生輸出信號OUT。如此一來,多個無時脈回歸邏輯’0’骨牌邏輯閘可被結合或串疊在一起,以實現特定邏輯運算─例如,邏輯及運算─對大量輸入信號之處理。As with the joint logic gate design 700 discussed previously, the clockless regression logic '0' domino logic gate 900 can employ a cascade technique to implement the logical AND of any number of input signals with multiple logic and gates. Each of the logic gates 701, 703, and 705 can be implemented as a logic and gate with reference to the clockless return logic '0' domino logic gate 900. In one embodiment, the logic gate 701 is designed as a logic gate for logically ANDing the input signals I1...I3 to generate the signal O1; the logic gate 703 is designed as a logic and gate, and the input signals I4...I6 The logic AND operation is performed to generate the signal O2; the logic gate 705 is designed as a logic and gate, and the signals O1 and O2 are logically ANDed to generate the output signal OUT. As such, a plurality of clockless regression logic '0' domino logic gates can be combined or stacked to achieve a particular logical operation - for example, a logical AND operation - for processing a large number of input signals.
第10圖為一方塊圖,圖解另一個無時脈回歸邏輯’0’骨牌邏輯閘1000,用於實現一邏輯及閘,對M個回歸邏輯’0’輸入信號I1…IM作邏輯及運算,且包括一簡化的重置電路1003。無時脈回歸邏輯’0’骨牌邏輯閘1000大致上與無時脈回歸邏輯’0’骨牌邏輯閘900類似,其中同樣的元件採用同樣的編號。比較兩電路,回歸邏輯’0’重置電路903改由一回歸邏輯’0’重置電路1003實現。無時脈回歸邏輯’0’骨牌邏輯閘1000的操作一般來說也符合第5圖所揭露之時序圖。回歸邏輯’0’重置電路1003僅包括一P通道裝置PA,以源極耦接P通道裝置P1的汲極於節點310,且以汲極耦接重置節點306。輸入信號I1…IM中任一者,圖中標示為信號IX,會供應給P通道裝置PA的閘極。Figure 10 is a block diagram illustrating another clockless regression logic '0' domino logic gate 1000 for implementing a logic and gate, and logically ANDing the M regression logic '0' input signals I1...IM, A simplified reset circuit 1003 is included. The clockless regression logic '0' domino logic gate 1000 is substantially similar to the clockless regression logic '0' domino logic gate 900, in which the same components are numbered the same. Comparing the two circuits, the return logic '0' reset circuit 903 is implemented by a return logic '0' reset circuit 1003. The operation of the clockless regression logic '0' domino logic gate 1000 generally also conforms to the timing diagram disclosed in FIG. The return logic '0' reset circuit 1003 includes only a P-channel device PA, the source is coupled to the drain of the P-channel device P1 to the node 310, and the reset node 306 is coupled with the drain. Any of the input signals I1...IM, indicated as signal IX in the figure, is supplied to the gate of the P-channel device PA.
與無時脈回歸邏輯’0’骨牌邏輯閘900相較,無時脈回歸邏輯’0’骨牌邏輯閘1000所執行的運算是相同的,不過是設計為非雙配置結構。無時脈回歸邏輯’0’骨牌邏輯閘1000的操作基本上類似無時脈回歸邏輯’0’骨牌邏輯閘900,不同處在於其重置狀態僅於輸入信號IX為低準位時成立。輸入信號I1…IM─包括信號IX─都轉態為高準位時,重置狀態不成立,且估算事件發生。當信號IX轉態為邏輯’0’,所述估算狀態不成立且所述重置狀態成立,一重置事件被引發,使該無時脈回歸邏輯’0’骨牌電路305回到其預置狀態。無時脈回歸邏輯’0’骨牌邏輯閘1000的優點在於簡化的回歸邏輯’0’重置電路,其中只以一個P通道裝置實現;然而,若信號IX以較其他輸入信號慢的方式回歸零準位,則會有一定的速度損失發生。無時脈回歸邏輯’0’骨牌邏輯閘900的優點在可能增快反應速度,原因是,估算事件後,重置事件會在輸入信號中任一者轉態為零準位時立即的速度發生;然而,會需要較複雜的回歸邏輯’0’重置電路設計。若該等輸入信號IN之一必定為最快的回歸邏輯’0’信號,可將其選擇為信號IX,以解決無時脈回歸邏輯’0’骨牌邏輯閘1000的反應速度問題。Compared to the clockless regression logic '0' domino logic gate 900, the operations performed by the clockless regression logic '0' domino logic gate 1000 are the same, but are designed to be non-dual configuration. The operation of the clockless return logic '0' domino logic gate 1000 is substantially similar to the clockless return logic '0' domino logic gate 900, except that its reset state is established only when the input signal IX is low. When the input signals I1...IM, including the signal IX, are all transitioned to a high level, the reset state is not established and an estimated event occurs. When the signal IX transitions to a logic '0', the estimated state does not hold and the reset state is established, a reset event is triggered, causing the no-wheel-return logic '0' domino circuit 305 to return to its preset state. . The advantage of the clockless regression logic '0' domino logic gate 1000 is the simplified return logic '0' reset circuit, which is implemented with only one P channel device; however, if signal IX returns to zero in a slower manner than the other input signals At the level, there will be a certain speed loss. The advantage of no clock return logic '0' domino logic gate 900 is that it may increase the reaction speed because the reset event will occur immediately after the event is estimated to be zero when any of the input signals is zero. However, more complex regression logic '0' will be required to reset the circuit design. If one of the input signals IN must be the fastest regression logic '0' signal, it can be selected as signal IX to account for the reaction speed problem of the clockless regression logic '0' domino logic gate 1000.
參考第5圖之時序圖,回顧採用回歸邏輯’0’骨牌電路400之無時脈回歸邏輯’0’骨牌邏輯閘300,其中,所選擇的多個或所有輸入信號(視其特定設計而定)根據回歸邏輯’0’操作為(或轉態至)邏輯’0’時,無時脈回歸邏輯’0’骨牌邏輯閘300為其初始預設狀態。當輸入信號使估算狀態成立,重置狀態為不成立,且一估算事件發生。在估算狀態成立的狀態下,重置狀態維持為不成立。在供應給重置電路之回歸邏輯’0’輸入信號回復成其預設邏輯’0’狀態時,所述估算狀態轉態為不成立,且其後所述重置狀態成立。重置最終是根據回歸邏輯’0’操作發生。關於無時脈回歸邏輯’0’骨牌邏輯閘600,重置事件在輸入信號I1…IM各個都轉態為邏輯’0’時發生。關於無時脈回歸邏輯’0’骨牌邏輯閘800,重置事件在輸入信號I1…I5的一子集合─即輸入信號I4與I5─轉態為邏輯’0’時發生。關於無時脈回歸邏輯’0’骨牌邏輯閘900,重置事件在輸入信號I1…IM其中任一者轉態為邏輯’0’時發生。關於無時脈回歸邏輯’0’骨牌邏輯閘1000,重置事件於輸入信號中選定的一個─即信號IX─轉態為邏輯’0’時發生。Referring to the timing diagram of Figure 5, a regression-free logic '0' domino logic gate 300 using regression logic '0' domino circuit 400 is reviewed, wherein multiple or all of the selected input signals are selected (depending on their specific design) When the return logic '0' is operated (or transitioned to) logic '0', the clockless return logic '0' domino logic gate 300 is its initial preset state. When the input signal causes the estimated state to be true, the reset state is not established, and an estimated event occurs. In the state where the estimation state is established, the reset state is maintained as not established. When the return logic '0' input signal supplied to the reset circuit returns to its predetermined logic '0' state, the estimated state transition is not true, and thereafter the reset state is established. The reset ultimately occurs based on the regression logic '0' operation. Regarding the clockless regression logic '0' domino logic gate 600, the reset event occurs when the input signals I1...IM are each transitioned to logic '0'. Regarding the clockless regression logic '0' domino logic gate 800, the reset event occurs when a subset of the input signals I1...I5, i.e., input signals I4 and I5, transitions to logic '0'. Regarding the clockless regression logic '0' domino logic gate 900, the reset event occurs when either of the input signals I1...IM transitions to logic '0'. Regarding the clockless regression logic '0' domino logic gate 1000, the reset event occurs when the selected one of the input signals, i.e., signal IX, transitions to logic '0'.
第11圖為一示意方塊圖,圖解一無時脈回歸邏輯’1’骨牌邏輯閘1100,根據無時脈狀態回歸骨牌邏輯閘200的一種回歸邏輯’1’實施方式所實現。一或多個輸入信號與所產生的輸出信號被設計為回歸邏輯’1’信號,具有的預設邏輯狀態為邏輯’1’。電源電位VSRC1設計為參考電位VSS,且電源電位VSRC2設計為供電電位VDD,與無時脈回歸邏輯’0’骨牌邏輯閘300的設計相反。狀態回歸估算電路201、狀態回歸骨牌電路205以及狀態回歸重置電路203被分別以一回歸邏輯’1’估算電路1101、一回歸邏輯’1’骨牌電路1105以及一回歸邏輯’1’重置電路1103實現,乃根據一狀態回歸’1’操作所設計。請注意,雖然電路1101與1103各自可能因其輸出信號的操作被視為回歸邏輯’0’電路,仍是依照其輸入信號以及回歸邏輯’1’骨牌邏輯閘1100整體作用將之視為回歸邏輯’1’電路。前述之預置輸入出端PSET改由耦接一預清節點1102的一預清輸入輸出端PCLR取代。無時脈回歸邏輯’1’骨牌邏輯閘1100的輸出在一輸出節點1108設定一回歸邏輯’1’輸出信號OUT,且在一重置節點1106產生一重置信號RST。狀態回歸致能節點204由一回歸邏輯’1’致能節點1104實現,耦接N通道裝置N1的閘極,以實現狀態回歸致能電路207。N通道裝置N1以源極耦接參考電位VSS且以源極耦接第二重置節點1110,且回歸邏輯’1’重置電路1103耦接於重置節點1110與1106之間。Figure 11 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1100 implemented in accordance with a regression logic '1' implementation that returns to the domino logic gate 200 without the clock state. The one or more input signals and the resulting output signal are designed as a return logic '1' signal having a predetermined logic state of logic '1'. The power supply potential VSRC1 is designed to be the reference potential VSS, and the power supply potential VSRC2 is designed as the supply potential VDD, as opposed to the design of the clockless return logic '0' domino logic gate 300. The state regression estimation circuit 201, the state regression domino circuit 205, and the state regression reset circuit 203 are respectively a regression logic '1' estimation circuit 1101, a regression logic '1' domino circuit 1105, and a regression logic '1' reset circuit. The 1103 implementation is designed according to a state return '1' operation. Please note that although circuits 1101 and 1103 may each be considered as a return logic '0' circuit due to the operation of their output signals, they are still considered regression logic according to their input signals and the regression logic '1' domino logic gate 1100 as a whole. '1' circuit. The preset input and output terminal PSET is replaced by a pre-clear input and output terminal PCLR coupled to a pre-clear node 1102. The output of the clockless regression logic '1' domino logic gate 1100 sets a return logic '1' output signal OUT at an output node 1108 and a reset signal RST at a reset node 1106. The state regression enable node 204 is implemented by a regression logic '1' enable node 1104 coupled to the gate of the N-channel device N1 to implement the state regression enable circuit 207. The N-channel device N1 is coupled to the reference potential VSS by a source and coupled to the second reset node 1110 by a source, and the return logic '1' reset circuit 1103 is coupled between the reset nodes 1110 and 1106.
第12圖為一示意方塊圖,圖解一回歸邏輯’1’骨牌電路1200,為回歸邏輯’1’骨牌電路1105的一種實施方式。回歸邏輯’1’骨牌電路1200為回歸邏輯’0’骨牌電路300的反相設計,其中以參考電位VSS取代電路300中的供電電位VDD,以供電電位VDD取代電路300中的參考電位VSS,以P通道裝置取代電路300中的N通道裝置,以N通道裝置取代電路300中的P通道裝置,且令每一個節點的操作狀態都是電路300內對應節點的反相狀態(邏輯’0’狀態替換成邏輯’1’狀態,且邏輯’1’狀態替換為邏輯’0’狀態)。此外,各個反相器內的P通道與N通道裝置與電源電位設計都是電路300之反相設計;圖中因為所執行的同樣為反相運算,所以將之採用相同的符號表示。預清節點1102耦接反相器1201的輸入端,且耦接N通道裝置N2以及N3的汲極。反相器1201的輸出端耦接輸出節點1108以供應回歸邏輯’1’輸出信號,且更耦接N通道裝置N3的閘極與反相器1203的輸入端。反相器1203的輸出耦接至節點1104以供應回歸邏輯’1’致能信號RT1E,以施加於P通道裝置P1之閘極。P通道裝置P1以源極耦接供電電位VDD且以汲極耦接重置節點1106以供應重置信號RST。重置信號RST供應給反相器1205的輸入端,反相器1205的輸出端供應一反相重置信號RSTB。反相輸出信號RSTB供應給N通道裝置N2的閘極,該N通道裝置N2的源極耦接參考電位VSS。反相器1201與N通道裝置N3一同組成一半維持電路1202,維持預清輸入輸出端PCLR電位為低準位直至回歸邏輯’1’估算電路1101將該預清輸入輸出端PCLR的電位拉升。P通道裝置P2如圖虛線所示(對應回歸邏輯’0’骨牌電路300內的N通道裝置N2)以其閘極接收反相重置信號RSTB,且以汲極耦接節點1106,且以源極耦接供電電位VDD。預清輸入輸出端PCLR初始預清為低準位,故反相器1201設定輸出信號OUT為高準位,令N通道裝置N3導通。N通道裝置N3因此維持預清輸入輸出端PCLR為低準位。由於輸出信號OUT的初始狀態為高準位,反相器1205會設定回歸邏輯’1’致能信號RT1E為低準位,令P通道裝置P1導通,導通的P通道裝置P1將拉高重置信號RST。反相器1205因此拉低反相重置信號RSTB且N通道裝置N2的起始狀態為不導通。Figure 12 is a schematic block diagram illustrating a regression logic '1' domino circuit 1200 as an embodiment of a return logic '1' domino circuit 1105. The regression logic '1' domino circuit 1200 is an inverted design of the return logic '0' domino circuit 300, in which the reference potential VSS is substituted for the supply potential VDD in the circuit 300, and the supply potential VDD is substituted for the reference potential VSS in the circuit 300. The P-channel device replaces the N-channel device in circuit 300, replaces the P-channel device in circuit 300 with an N-channel device, and causes the operational state of each node to be the inverted state of the corresponding node in circuit 300 (logical '0' state Replaced with a logical '1' state and a logical '1' state replaced with a logical '0' state). In addition, the P-channel and N-channel devices and the power supply potential design in each inverter are both inverted designs of the circuit 300; since the same calculations are performed in the figure, they are denoted by the same symbols. The pre-clearing node 1102 is coupled to the input end of the inverter 1201 and coupled to the drains of the N-channel devices N2 and N3. The output of the inverter 1201 is coupled to the output node 1108 to supply the return logic '1' output signal, and is further coupled to the gate of the N-channel device N3 and the input of the inverter 1203. The output of inverter 1203 is coupled to node 1104 to supply a return logic '1' enable signal RT1E for application to the gate of P-channel device P1. The P-channel device P1 is coupled to the supply potential VDD with a source and coupled to the reset node 1106 with a drain to supply a reset signal RST. The reset signal RST is supplied to the input of the inverter 1205, and the output of the inverter 1205 is supplied with an inverted reset signal RSTB. The inverted output signal RSTB is supplied to the gate of the N-channel device N2, and the source of the N-channel device N2 is coupled to the reference potential VSS. The inverter 1201 and the N-channel device N3 constitute a half-maintenance circuit 1202, and maintain the pre-clear input/output terminal PCLR potential at a low level until the return logic '1' estimation circuit 1101 pulls up the potential of the pre-clear input/output terminal PCLR. The P-channel device P2 is shown as a broken line (corresponding to the N-channel device N2 in the dominating logic '0' domino circuit 300), receives the inverted reset signal RSTB with its gate, and is coupled to the node 1106 with the drain, and the source The pole is coupled to the power supply potential VDD. The pre-clear input/output terminal PCLR is initially pre-cleared to a low level, so the inverter 1201 sets the output signal OUT to a high level to turn on the N-channel device N3. The N-channel device N3 thus maintains the pre-clear input and output terminal PCLR at a low level. Since the initial state of the output signal OUT is a high level, the inverter 1205 sets the regression logic '1' to enable the signal RT1E to be low, and the P channel device P1 is turned on, and the turned-on P channel device P1 is pulled high. Signal RST. The inverter 1205 thus pulls the inverted reset signal RSTB low and the initial state of the N-channel device N2 is non-conductive.
參考第11與12圖,回應一或多個輸入信號IN轉態為一或多個估算狀態的任一者時所發生的一估算事件,回歸邏輯’1’估算電路1101拉升預清輸入輸出端PCLR的準位,致使回歸邏輯’1’骨牌電路1200轉態為其閂鎖狀態。特別是,反相器1201會拉低輸出信號OUT令N通道裝置N3不導通。反相器1203拉升回歸邏輯’1’致能信號RT1E的準位,使N通道裝置N1導通,且令P通道裝置P1不導通。導通的N通道裝置N1會耦接節點1110至參考電位VSS。不導通的P通道裝置P1將不再限制重置信號RST為高準位。輸入信號IN的估算狀態會導致回歸邏輯’1’重置電路1103轉態為其隔離狀態,使節點1106與1110彼此隔離。如此一來,重置節點1106暫時被隔離,重置信號RST不再被限制在特定狀態。然而,由於沒有其他裝置試圖變化重置信號RST的狀態,重置信號RST維持為高準位。當輸入信號IN處於一估算狀態,回歸邏輯’1’重置電路1103維持在其隔離狀態。Referring to Figures 11 and 12, in response to an estimated event occurring when one or more of the input signals IN transitions to any one or more of the estimated states, the regression logic '1' estimates the circuit 1101 to pull up the pre-clear input and output. The level of the PCLR is such that the return logic '1' domino circuit 1200 is in its latched state. In particular, the inverter 1201 pulls down the output signal OUT to disable the N-channel device N3. The inverter 1203 pulls up the level of the return logic '1' enable signal RT1E to turn on the N-channel device N1 and disable the P-channel device P1. The turned-on N-channel device N1 couples the node 1110 to the reference potential VSS. The non-conducting P-channel device P1 will no longer limit the reset signal RST to a high level. The estimated state of the input signal IN causes the return logic '1' reset circuit 1103 to transition to its isolated state, thereby isolating nodes 1106 and 1110 from each other. As a result, the reset node 1106 is temporarily isolated, and the reset signal RST is no longer limited to a specific state. However, since no other device attempts to change the state of the reset signal RST, the reset signal RST is maintained at a high level. When the input signal IN is in an estimated state, the return logic '1' reset circuit 1103 is maintained in its isolated state.
當供應給該回歸邏輯’1’重置電路1103之輸入信號IN各個回復為其預設狀態,回歸邏輯’1’重置電路1103轉態至其重置狀態,引發一重置事件,其中,N通道裝置N1以及回歸邏輯’1’重置電路1103聯合將重置信號RST拉到低準位。反相器1205會隨之將反相重置信號RSTB拉到高準位以導通N通道裝置N2。導通的N通道裝置N2會將預清輸入輸出端PCLR的電位拉低到預設值。請注意,當供應給該回歸邏輯’1’重置電路1103的每個輸入信號IN回歸到預設狀態,該些輸入信號IN將不再為估算狀態,因此,回歸邏輯’1’估算電路1101不再將預清輸入輸出端PCLR拉在高準位。如此一來,N通道裝置N2得以再次將預清輸入輸出端PCLR拉低成預清狀態。若預清輸入輸出端PCLR轉態為高準位,反相器1201會設定輸出信號OUT再次為高準位,使N通道裝置N3導通,維持預清輸入輸出端PCLR為低準位。反相器1103會將回歸邏輯’1’致能信號RT1E拉低,以導通P通道裝置P1、且使N通道裝置N1不導通。由於N通道裝置N1不導通,回歸邏輯’1’重置電路1103與參考電位VSS隔離,不再將重置信號RST之準位拉低。此外,P通道裝置P1的導通會將重置信號RST拉升到高準位,反相器1105會將反相重置信號RSTB拉到低準位,使N通道裝置N2不導通。雖然N通道裝置N2不導通,半維持電路1202會維持預清輸入輸出端PCLR電位為低準位。如此一來,回歸邏輯’1’骨牌電路1200重置回其預置狀態,以準備迎接下一次的估算事件。When the input signals IN supplied to the return logic '1' reset circuit 1103 are each returned to their preset states, the return logic '1' resets the circuit 1103 to its reset state, causing a reset event, wherein The N-channel device N1 and the return logic '1' reset circuit 1103 jointly pull the reset signal RST to a low level. The inverter 1205 will then pull the inverted reset signal RSTB to a high level to turn on the N-channel device N2. The turned-on N-channel device N2 pulls the potential of the pre-clear input and output terminal PCLR to a preset value. Please note that when each input signal IN supplied to the return logic '1' reset circuit 1103 returns to a preset state, the input signals IN will no longer be in an estimated state, therefore, the return logic '1' estimation circuit 1101 The pre-clear input and output terminal PCLR is no longer pulled to the high level. In this way, the N-channel device N2 can again pull the pre-clear input and output terminal PCLR to the pre-clear state. If the pre-clear input and output terminal PCLR is turned to the high level, the inverter 1201 sets the output signal OUT to the high level again, so that the N-channel device N3 is turned on, and the pre-clear input and output terminal PCLR is kept at the low level. The inverter 1103 pulls the return logic '1' enable signal RT1E low to turn on the P channel device P1 and disable the N channel device N1. Since the N-channel device N1 is not turned on, the return logic '1' reset circuit 1103 is isolated from the reference potential VSS, and the level of the reset signal RST is no longer pulled low. In addition, the conduction of the P-channel device P1 pulls the reset signal RST to a high level, and the inverter 1105 pulls the inverted reset signal RSTB to a low level, so that the N-channel device N2 is not turned on. Although the N-channel device N2 is not turned on, the semi-sustain circuit 1202 maintains the pre-clear input and output terminal PCLR potential at a low level. As such, the regression logic '1' domino circuit 1200 is reset back to its preset state to prepare for the next estimated event.
第13圖以一時序圖描述無時脈回歸邏輯’1’骨牌邏輯閘1100的操作,其中回歸邏輯’1’骨牌電路1105所採用的是回歸邏輯’1’骨牌電路1200的一種實施方式。第13圖之時序圖根本上與第5圖之時序圖類似,除了少數信號名稱的不同、以及電路信號的準位調整(將之反相)。特別說明之,相較於第5圖,第13圖以預清輸入輸出信號PCLR取代預充輸入輸出信號PCHG,以回歸邏輯’1’輸出信號OUT(RT1)取代回歸邏輯’0’輸出信號OUT(RT0),且以回歸邏輯’1’致能信號RT1E取代回歸邏輯’0’致能信號RT0E。第13圖的信號PCLR、OUT(RT1)、RT1E、RST以及RSTB分別為第5圖信號PCHR、OUT(RT0)、RT0E、RST以及RSTB的反相。此外,轉態時間基本上同樣具有短暫延遲。與第5圖相較,第13圖也包含第一狀態信號EVAL以及第二狀態信號RESET之波形,且反應類似。在這個實施例中,第一狀態信號EVAL用於標示回歸邏輯’1’估算電路1101的估算狀態,於估算狀態成立時為高準位,且於估算狀態不成立時為低準位。第二狀態信號RESET用於標示回歸邏輯’1’重置電路1103的重置狀態,於重置狀態成立時為高準位,且於重置狀態不成立時為低準位。所述重置狀態會引發一重置事件,僅發生在一估算事件後該回歸邏輯’1’致能信號RT1E為高準位時。Figure 13 depicts the operation of the clockless regression logic '1' domino logic gate 1100 in a timing diagram in which the regression logic '1' domino circuit 1105 employs an embodiment of a regression logic '1' domino circuit 1200. The timing diagram of Figure 13 is essentially similar to the timing diagram of Figure 5, except for a few signal names and the level adjustment of the circuit signal (inverting it). In particular, compared with Figure 5, Figure 13 replaces the precharge input and output signal PCHG with the pre-clear input and output signal PCLR, and replaces the return logic '0' output signal OUT with the return logic '1' output signal OUT (RT1). (RT0), and replace the return logic '0' enable signal RT0E with the return logic '1' enable signal RT1E. The signals PCLR, OUT(RT1), RT1E, RST, and RSTB in Fig. 13 are the inverse of the signals PCHR, OUT(RT0), RT0E, RST, and RSTB of the fifth figure, respectively. In addition, the transition time basically has the same short delay. Compared with Fig. 5, Fig. 13 also includes the waveforms of the first state signal EVAL and the second state signal RESET, and the reaction is similar. In this embodiment, the first status signal EVAL is used to indicate the estimated state of the regression logic '1' estimation circuit 1101, which is a high level when the estimated state is established, and a low level when the estimated state is not established. The second state signal RESET is used to indicate the reset state of the return logic '1' reset circuit 1103, which is a high level when the reset state is established, and a low level when the reset state is not established. The reset state causes a reset event to occur only when the return logic '1' enable signal RT1E is at a high level after an estimated event.
第13圖將所述信號EVAL、RESET、PCRL、OUT(RT1)、RT1E、RST以及RSTB以時序圖呈現。各個信號間存在的轉態延遲僅是示意用途,並非精確顯示實際狀況。參考初始時間點T0,第一狀態信號EVAL的初始狀態為低準位,顯示輸入信號IN並非在估算狀態。此外,基於第5圖所討論內容,第二狀態信號RESET於時間點T0為無意義。於時間點T0,信號PCLR、OUT(RT1)、RT1E、RST以及RSTB分別初始設定為邏輯’0’、’1’、’0’、’1’以及’0’。Figure 13 presents the signals EVAL, RESET, PCRL, OUT(RT1), RT1E, RST, and RSTB in a timing diagram. The transition delays that exist between the individual signals are for illustrative purposes only and do not accurately show the actual conditions. Referring to the initial time point T0, the initial state of the first state signal EVAL is a low level, and the display input signal IN is not in an estimated state. Further, based on the content discussed in FIG. 5, the second state signal RESET is meaningless at the time point T0. At time point T0, signals PCLR, OUT (RT1), RT1E, RST, and RSTB are initially set to logic '0', '1', '0', '1', and '0', respectively.
在接續的時間點T1,輸入信號IN一同進入估算狀態,致使第一狀態信號EVAL轉態為高準位,且第二狀態信號RESET轉態為低準位。回應第一狀態信號EVAL之高準位狀態,回歸邏輯’1’估算電路1101在一短暫延遲後的一時間點T2拉升預清輸入輸出端PCLR電位,引發一估算事件。由於第二狀態信號RESET為低準位,回歸邏輯’1’重置電路1103處於其隔離狀態。回應預清輸入輸出端PCLR之信號轉態到高準位的動作,反相器1201在一短暫延遲後的接續時間點T3將輸出信號OUT的準位拉低。回應拉低準位的輸出信號OUT,反相器1203在一短暫延遲後的接續時間點T4拉高回歸邏輯’1’致能信號RT1E的準位,以導通N通道裝置N1,且令P通道裝置P1不導通。由於回歸邏輯’1’重置電路1103不作用,重置信號RST不受任何裝置影響且維持在高準位(或者,在有設計P通道裝置P2的實施方式中,由P通道裝置P2維持在高準位)。無時脈回歸邏輯’1’骨牌電路1200的狀態於第一狀態信號EVAL為高準位時維持不變。在接續的時間點T5,一個或多個輸入信號IN改變狀態,致使所述估算狀態不成立,且第一狀態信號EVAL相應轉態為低準位。若供應給回歸邏輯’1’重置電路1103的輸入信號IN各個都回復為邏輯’1’,則第二狀態信號RESET如同虛線501所示於時間點T5轉態為高準位。然而,關於非雙配置設計,第一狀態信號EVAL轉態為低準位與第二狀態信號RESET轉態為高準位之間存在有一延遲。請注意,由於第一狀態信號EVAL為低準位,所述估算狀態不成立,故回歸邏輯’1’估算電路1101在時間點T5後不再拉升預清輸入輸出端PCLR的電位。預清輸入輸出端PCLR的電位會維持在高準位直至N通道裝置N2 作用,將其準位拉低。At the subsequent time point T1, the input signal IN enters the estimation state together, causing the first state signal EVAL to transition to the high level, and the second state signal RESET to the low level. In response to the high level state of the first state signal EVAL, the return logic '1' estimating circuit 1101 pulls up the preamplifier input and output terminal PCLR potential at a time point T2 after a short delay, causing an estimation event. Since the second state signal RESET is at a low level, the return logic '1' reset circuit 1103 is in its isolated state. In response to the action of pre-clearing the signal of the input/output terminal PCLR to the high level, the inverter 1201 pulls the level of the output signal OUT low at the continuation time point T3 after a short delay. In response to the output signal OUT of the low level, the inverter 1203 raises the level of the return logic '1' enable signal RT1E at a subsequent time T4 after a short delay to turn on the N channel device N1 and make the P channel Device P1 is not conducting. Since the return logic '1' reset circuit 1103 does not function, the reset signal RST is not affected by any device and is maintained at a high level (or, in the embodiment with the designed P channel device P2, maintained by the P channel device P2 High standard). The state of the clockless regression logic '1' domino circuit 1200 remains unchanged when the first state signal EVAL is at a high level. At the subsequent time point T5, one or more input signals IN change state, causing the estimated state to be unsuccessful, and the first state signal EVAL is correspondingly transitioned to a low level. If the input signals IN supplied to the return logic '1' reset circuit 1103 each return to logic '1', the second state signal RESET transitions to a high level at time T5 as indicated by the broken line 501. However, with regard to the non-dual configuration design, there is a delay between the transition of the first state signal EVAL to the low level and the transition of the second state signal RESET to the high level. Please note that since the first state signal EVAL is at a low level, the estimation state is not established, so the return logic '1' estimation circuit 1101 does not pull up the potential of the pre-clear input/output terminal PCLR after the time point T5. Pre-clear the input and output terminals PCLR potential will remain at the high level until the N channel device N2 Role, pull its level low.
在時間點T5或接續的時間點T6,供應給回歸邏輯’1’重置電路1103的輸入信號IN轉態為高準位,以開始回歸邏輯’1’重置電路1103的重置狀態,使第二狀態信號RESET轉態為高準位。回歸邏輯’1’重置電路1103聯合N通道裝置N1在一短暫延遲後的一時間點T7將重置信號RST的準位拉低,以起始一重置事件。反相器1205回應上述操作,在一短暫延遲後的一時間點T8拉升反相重置信號RSTB的準位。轉態為高準位的反相重置信號RSTB會導通N通道裝置N2,於一短暫延遲後的時間點T9將預清輸入輸出端PCLR的準位拉低。當預清輸入輸出端PCLR的準位降低,反相器1201在一短暫延遲後的時間點T10設定輸出信號OUT為高準位。轉態為高準位的輸出信號OUT會使N通道裝置N3導通,致使半維持電路1202得以維持預清輸入輸出端PCLR的電位為低準位直至稍後的估算區間將其準位拉高。反相器1203在一短暫延遲後的時間點T11將回歸邏輯’1’致能信號RT1E的準位拉低。低準位狀態的回歸邏輯’1’致能信號RT1E使P通道裝置P1導通,且使N通道裝置N1不導通。由於N通道裝置N1不導通,回歸邏輯’1’重置電路1103不再拉低重置信號RST的準位。導通的P通道裝置P1在一短暫延遲後的時間點T12將重置信號RST拉回高準位。反相器1205在短暫延遲後的時間點T13拉低反相重置信號RSTB的準位,使N通道裝置N2不再拉低預清輸入輸出端PCLR的準位。此時,半維持電路1202負責維持該預清輸入輸出端PCLR的準位為低準位。於跟隨在時間點T13之後的時間點T14,所述信號回到初始預設狀態。因此,回歸邏輯’1’估算電路1101以及N通道裝置N1皆處於其預設狀態,回歸邏輯’1’骨牌電路1105回歸其預置狀態,此外,假設入信號IN各個為高準位,回歸邏輯’1’重置電路1103處於其重置狀態。總結之,輸入信號IN的估算狀態會引發一估算事件,致使輸出信號OUT轉態為低準位,且致能接續的重置事件。輸入信號IN的重置狀態會致使回歸邏輯’1’重置電路1103引發一重置事件,並使無時脈回歸邏輯’1’骨牌邏輯閘1100回歸其初始狀態,以迎接下一個估算區間。At the time point T5 or the subsequent time point T6, the input signal IN supplied to the return logic '1' reset circuit 1103 is turned to the high level to start the reset logic '1' reset circuit 1103 reset state, so that The second state signal RESET transitions to a high level. The return logic '1' reset circuit 1103, in conjunction with the N-channel device N1, pulls the level of the reset signal RST low at a time point T7 after a short delay to initiate a reset event. The inverter 1205 responds to the above operation, and raises the level of the inverted reset signal RSTB at a time point T8 after a short delay. The inverted reset signal RSTB, which is transitioned to a high level, turns on the N-channel device N2, and pulls the level of the pre-clear input and output terminal PCLR low at a time point T9 after a short delay. When the level of the pre-clear input and output terminal PCLR is lowered, the inverter 1201 sets the output signal OUT to a high level at a time point T10 after a short delay. The output signal OUT, which is transitioned to a high level, causes the N-channel device N3 to conduct, causing the semi-sustain circuit 1202 to maintain the potential of the pre-clear input and output terminal PCLR at a low level until a later estimation interval pulls its level high. The inverter 1203 pulls the level of the return logic '1' enable signal RT1E low at a time point T11 after a brief delay. The return logic '1' enable signal RT1E of the low level state turns on the P channel device P1 and makes the N channel device N1 non-conductive. Since the N-channel device N1 is not turned on, the return logic '1' reset circuit 1103 no longer pulls down the level of the reset signal RST. The turned-on P-channel device P1 pulls the reset signal RST back to the high level at a time point T12 after a short delay. The inverter 1205 pulls down the level of the inverted reset signal RSTB at a time point T13 after a short delay, so that the N-channel device N2 no longer pulls down the level of the pre-clear input and output terminal PCLR. At this time, the semi-sustaining circuit 1202 is responsible for maintaining the level of the pre-clear input and output terminal PCLR to a low level. At a time point T14 following time point T13, the signal returns to the initial preset state. Therefore, the regression logic '1' estimation circuit 1101 and the N channel device N1 are in their preset states, and the regression logic '1' domino circuit 1105 returns to its preset state. In addition, it is assumed that the input signals IN are each high level, and the regression logic The '1' reset circuit 1103 is in its reset state. In summary, the estimated state of the input signal IN triggers an estimated event, causing the output signal OUT to transition to a low level and enabling a subsequent reset event. The reset state of the input signal IN causes the return logic '1' reset circuit 1103 to initiate a reset event and returns the clockless return logic '1' domino logic gate 1100 to its initial state to accommodate the next estimated interval.
如同第5圖的討論內容,第二狀態信號RESET為高準位直至時間點T11-回歸邏輯’1’致能信號RTE1轉態為低準位-以確保無時脈回歸邏輯’1’邏輯閘回歸其初始狀態,其後,第二狀態信號RESET如圖所示為無意義。請注意,重置信號RST在時間點T7拉至低準位時,倘若重置狀態不成立將第二狀態信號RESET拉低為低準位,重置信號RST仍維持在低準位,原因是P通道裝置P1仍為不導通,無力影響重置信號RST。因此,雖然重置狀態應當維持成立直至回歸邏輯’1’致能信號RT1E轉態為低準位,但若輸入信號如是動作於時間點T7之後且時間點T11之前拉低第二狀態信號RESET,仍不會影響正確的電路操作。一旦回歸邏輯’1’致能信號RT1E為低準位,P通道裝置P1導通,且輸入信號IN任何無意義的轉態在時間點T11後都不會影響整體電路狀態。As discussed in Figure 5, the second state signal RESET is at a high level until the time point T11 - the return logic '1' enables the signal RTE1 to transition to a low level - to ensure that there is no clock return logic '1' logic gate Returning to its initial state, after that, the second state signal RESET is meaningless as shown. Please note that when the reset signal RST is pulled to the low level at the time point T7, if the reset state is not established, the second state signal RESET is pulled low to the low level, and the reset signal RST is still maintained at the low level, because P The channel device P1 is still non-conducting and has no effect on the reset signal RST. Therefore, although the reset state should be maintained until the return logic '1' enable signal RT1E transitions to the low level, if the input signal is after the time point T7 and before the time point T11, the second state signal RESET is pulled down. Still does not affect the correct circuit operation. Once the return logic '1' enable signal RT1E is at a low level, the P-channel device P1 is turned on, and any meaningless transition of the input signal IN does not affect the overall circuit state after the time point T11.
第14圖為一示意方塊圖,圖解一無時脈回歸邏輯’1’骨牌邏輯閘1400,用於實現一邏輯或運算,對M個輸入信號I1…IM作邏輯或運算。無時脈回歸邏輯’1’骨牌邏輯閘1400包括回歸邏輯’1’骨牌電路1105。電路1105耦接一回歸邏輯’1’估算電路1401(用來實現前述回歸邏輯’1’估算電路1101)以及一回歸邏輯’1’重置電路1403(用來實現前述回歸邏輯’1’重置電路1103)。回歸邏輯’1’估算電路1401包括M個P通道裝置PA…PM,各自以汲極耦接節點1102,且各自以源極耦接供電電位VDD。P通道裝置PA…PM各自提供一閘極,以接收輸入信號I1…IM其中之一。在類似方式中,回歸邏輯’1’重置電路1403包括M個N通道裝置NA…NM,串接於節點1110以及重置節點1106之間。如圖所示,第一級的N通道裝置NA以源極耦接N通道裝置N1之汲極上的節點1110,並以汲極耦接下一級N通道裝置的源極;依循所述規則直至最後一級的N通道裝置NM。最後一級N通道裝置NM的汲極耦接節點1106。N通道裝置NA…NM各自提供一閘極,以如圖所示方式接收輸入信號I1…IM其中之一。儘管圖中只標示所述N通道裝置的其中兩個裝置(NA,NM)、P通道裝置的其中兩個裝置(PA,PM)、以及僅顯示輸入信號I1與IM,事實上,依照所揭露之規則,省略繪製之部分可包括任何數量的所述裝置以及相關信號(例如,供應給N通道與P通道裝置NB與PB之閘極的輸入信號I2)。Figure 14 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1400 for implementing a logical OR operation to logically OR the M input signals I1...IM. The clockless regression logic '1' domino logic gate 1400 includes a return logic '1' domino circuit 1105. The circuit 1105 is coupled to a regression logic '1' estimation circuit 1401 (for implementing the foregoing regression logic '1' estimation circuit 1101) and a regression logic '1' reset circuit 1403 (for implementing the aforementioned regression logic '1' reset Circuit 1103). The return logic '1' estimation circuit 1401 includes M P channel devices PA...PM, each of which is coupled to the node 1102 with a drain, and each of which is coupled to the supply potential VDD with a source. The P channel devices PA...PM each provide a gate to receive one of the input signals I1...IM. In a similar manner, the regression logic '1' reset circuit 1403 includes M N-channel devices NA...NM connected in series between the node 1110 and the reset node 1106. As shown, the N-channel device NA of the first stage is coupled to the node 1110 on the drain of the N-channel device N1 by a source and coupled to the source of the next-stage N-channel device with a drain; following the rules until the end One-stage N-channel device NM. The drain of the last stage N-channel device NM is coupled to node 1106. The N-channel devices NA...NM each provide a gate to receive one of the input signals I1...IM as shown. Although only two of the N-channel devices (NA, NM), two of the P-channel devices (PA, PM), and only the input signals I1 and IM are shown, in fact, according to the disclosed The rule that the omitted portion may include any number of the devices and associated signals (e.g., input signal I2 supplied to the gates of the N-channel and P-channel devices NB and PB).
無時脈回歸邏輯’1’骨牌邏輯閘1400為一種雙配置設計,其中,回歸邏輯’1’重置電路1403為回歸邏輯’1’估算電路1401的雙配置設計。此外,在雙配置設計中,供應給回歸邏輯’1’估算電路1401與回歸邏輯’1’重置電路1403的都是相同的輸入信號I1…IM。無時脈回歸邏輯’1’骨牌邏輯閘1400之操作通常符合第13圖所示之時序。在這個實施例中,當輸入信號I1…IM根據回歸邏輯’1’之操作皆處於邏輯’1’時,第一狀態信號EVAL為低準位,且第二狀態信號RESET為高準位。當輸入信號I1…IM中任一者轉態為低準位時,估算狀態成立,且重置狀態不成立,故第一狀態信號EVAL為高準位且第二狀態信號RESET為低準位。由於電路1401與1403為雙配置設計,隨著輸入信號IN之轉態切換,第一狀態信號EVAL與第二狀態信號RESET之狀態跟著切換,且維持為對方的反相。回應輸入信號IN中任一者的低準位轉態所引發的估算事件,預清輸入輸出端PCLR轉態為高準位,且輸出信號OUT在短暫延遲後轉態為低準位,且回歸邏輯’1’致能信號RT1E在另一段短暫延遲後轉態為高準位以致能一重置事件。當輸入信號I1…IM全數根據回歸邏輯’1’操作轉態回邏輯’1’,回歸邏輯’1’重置電路1403引發一重置事件,令重置信號RST轉態為低準位,反相重置信號RSTB轉態為高準位,預清輸入輸出端PCLR之準位拉回低準位,且輸出信號OUT如前述內容拉升回高準位。The clockless regression logic '1' domino logic gate 1400 is a dual configuration design in which the regression logic '1' reset circuit 1403 is a dual configuration design of the regression logic '1' estimation circuit 1401. Further, in the dual configuration design, the same input signals I1...IM are supplied to the regression logic '1' estimation circuit 1401 and the regression logic '1' reset circuit 1403. The operation of the clockless regression logic '1' domino logic gate 1400 generally conforms to the timing shown in Figure 13. In this embodiment, when the input signals I1...IM are in logic '1' according to the operation of the return logic '1', the first state signal EVAL is at a low level and the second state signal RESET is at a high level. When any of the input signals I1...IM transitions to a low level, the estimated state is established and the reset state is not established, so the first state signal EVAL is at a high level and the second state signal RESET is at a low level. Since the circuits 1401 and 1403 are of a dual configuration, as the switching state of the input signal IN switches, the states of the first state signal EVAL and the second state signal RESET are switched, and are maintained as the opposite phase of the other. In response to the estimated event caused by the low-level transition of any of the input signals IN, the PCLR transition state of the input and output terminals is pre-determined to a high level, and the output signal OUT transitions to a low level after a short delay, and the regression The logic '1' enable signal RT1E transitions to a high level after another short delay to enable a reset event. When the input signals I1...IM are all rotated back to logic '1' according to the return logic '1' operation, the return logic '1' reset circuit 1403 triggers a reset event, causing the reset signal RST to transition to a low level, The phase reset signal RSTB transitions to a high level, and the pre-clear input and output terminal PCLR is pulled back to the low level, and the output signal OUT is pulled back to the high level as described above.
在某些設計中,串接在回歸邏輯’1’重置電路1403內的N通道裝置之數量可能需限制在特定量以下,以確保電路正常運作。例如,在一種實施方式中,串接在參考電位VSS與重置節點1106間的N通道裝置之數量上限為4,因此,輸入信號的數量會被限制為3(即M為3)。參考第7圖,邏輯閘701、703與705分別可由一個回歸邏輯’1’邏輯或閘實現,各邏輯閘採用的是無時脈回歸邏輯’1’骨牌邏輯閘1400技術。這個實施例中,邏輯閘701設計為一邏輯或閘,對回歸邏輯’1’輸入信號I1…I3進行邏輯或運算,以供應回歸邏輯’1’信號O1。邏輯閘703設計為一回歸邏輯’1’邏輯或閘,對回歸邏輯’1’輸入信號I4…I6進行邏輯或運算,以供應一回歸邏輯’1’信號O2。邏輯閘705設計為一回歸邏輯’1’邏輯或閘,對信號O1與O2進行邏輯或運算,以供應為回歸邏輯’1’信號的輸出信號OUT。如此一來,多個無時脈回歸邏輯’1’骨牌邏輯閘可被結合或串疊在一起以對大量的回歸邏輯’1’輸入信號進行特定的邏輯運算,例如,邏輯或運算。In some designs, the number of N-channel devices cascaded in the return logic '1' reset circuit 1403 may need to be limited to a certain amount to ensure proper operation of the circuit. For example, in one embodiment, the upper limit of the number of N-channel devices connected in series between the reference potential VSS and the reset node 1106 is 4, and therefore, the number of input signals is limited to 3 (i.e., M is 3). Referring to Figure 7, logic gates 701, 703, and 705 can each be implemented by a return logic '1' logic or gate, and each logic gate uses a clockless regression logic '1' domino logic gate 1400 technique. In this embodiment, logic gate 701 is designed as a logic OR gate that logically ORs the return logic '1' input signals I1...I3 to supply a return logic '1' signal O1. Logic gate 703 is designed as a return logic '1' logic or gate, and logically ORs the return logic '1' input signals I4...I6 to supply a return logic '1' signal O2. Logic gate 705 is designed as a return logic '1' logic or gate that logically ORs signals O1 and O2 to supply an output signal OUT that is a return logic '1' signal. As such, a plurality of clockless regression logic '1' domino logic gates can be combined or cascaded to perform a particular logical operation, such as a logical OR operation, on a large number of regression logic '1' input signals.
第15圖為一示意方塊圖,圖解一無時脈回歸邏輯’1’骨牌邏輯閘1500,其中根據另外一種實施方式實現多樣化的邏輯運算。無時脈回歸邏輯’1’骨牌邏輯閘1500包括回歸邏輯’1’骨牌電路1105。電路1105耦接回歸邏輯’1’估算電路1501(用以實現回歸邏輯’1’估算電路1101)以及一回歸邏輯’1’重置電路1503(用以實現回歸邏輯’1’重置電路1103)。無時脈回歸邏輯’1’骨牌邏輯閘1500的設計基本上雷同無時脈回歸邏輯’0’骨牌邏輯閘800,不同之處在於專對回歸邏輯’1’操作所作的反相設計。說明之,相較於邏輯閘800,邏輯閘1500以供電電位VDD取代參考電位VSS,以參考電位VSS取代供電電位VDD,以N通道裝置取代P通道裝置,以P通道裝置取代N通道裝置,令輸入信號I4與I5採用回歸邏輯’1’操作方式而非回歸邏輯’0’操作方式,將信號狀態反相設計,且令輸入信號I1…I3為回歸邏輯’1’或非回歸邏輯’1’信號。前述節點302、304、306、308以及310分別以類似的節點1102、1104、1106、1108以及1110取代,以類似第11…14圖之方式實現類似的運算。無時脈回歸邏輯’1’骨牌邏輯閘1500的操作一般符合第13圖所揭露的時序圖。無時脈回歸邏輯’1’骨牌邏輯閘1500實行一邏輯運算OUT=~((~I1|~I2|~I3)&(~I4|~I5)),其中,符號「~」代表的是邏輯反相。Figure 15 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1500 in which diverse logic operations are implemented in accordance with another embodiment. The clockless regression logic '1' domino logic gate 1500 includes a regression logic '1' domino circuit 1105. The circuit 1105 is coupled to the regression logic '1' estimation circuit 1501 (to implement the regression logic '1' estimation circuit 1101) and a regression logic '1' reset circuit 1503 (to implement the regression logic '1' reset circuit 1103) . The design of the clockless regression logic '1' domino logic gate 1500 is basically identical to the clockless regression logic '0' domino logic gate 800, except for the inverse design of the return logic '1' operation. Illustrated, compared to the logic gate 800, the logic gate 1500 replaces the reference potential VSS with the power supply potential VDD, replaces the power supply potential VDD with the reference potential VSS, replaces the P channel device with the N channel device, and replaces the N channel device with the P channel device. The input signals I4 and I5 adopt the regression logic '1' operation mode instead of the return logic '0' operation mode, and the signal state is inverted, and the input signals I1...I3 are the return logic '1' or the non-regressive logic '1'. signal. The aforementioned nodes 302, 304, 306, 308, and 310 are replaced with similar nodes 1102, 1104, 1106, 1108, and 1110, respectively, to perform similar operations in a manner similar to the 11th-14th. The operation of the clockless regression logic '1' domino logic gate 1500 generally conforms to the timing diagram disclosed in FIG. The clockless regression logic '1' domino logic gate 1500 implements a logic operation OUT=~((~I1|~I2|~I3)&(~I4|~I5)), where the symbol "~" represents logic Inverted.
類似無時脈回歸邏輯’0’骨牌邏輯閘800,無時脈回歸邏輯’1’骨牌邏輯閘1500為非雙配置設計的另外一種實施方式,其中,回歸邏輯’1’重置電路1503並非回歸邏輯’1’估算電路1501的雙配置設計。輸入信號I1…I5中僅有一子集合-輸入信號I4與I5-有供應給回歸邏輯’1’重置電路1503。由於估算狀態成立時輸入信號I4與I5其中之一必定為低準位,故回歸邏輯’1’重置電路1503為其隔離狀態。只要回歸邏輯’1’估算電路1501為估算狀態,回歸邏輯’1’重置電路1503必定處於其隔離狀態以確保能以類似無時脈回歸邏輯’0’骨牌邏輯閘800的前述方式正常操作。此外,無時脈回歸邏輯’1’骨牌邏輯閘1500可採用類似於聯合邏輯閘設計700的技術實現一串疊邏輯閘。在一種實施方式中,第三N通道裝置(未顯示在圖中)添加於節點1110與1106之間的串疊裝置內,使三個串疊的N通道裝置接收輸入信號I1、I2與I3。上述修正所實現的是等效的邏輯運算,不過,關於該回歸邏輯’1’骨牌電路1105自閂鎖狀態轉態回歸預置狀態所耗費的時間,三個輸入信號(I1…I3)的狀況會較兩個輸入信號(I4與I5)的狀況耗時。Similar to the clockless regression logic '0' domino logic gate 800, the clockless regression logic '1' domino logic gate 1500 is another implementation of the non-dual configuration, wherein the regression logic '1' reset circuit 1503 is not a regression The logic '1' estimates the dual configuration design of circuit 1501. Only a subset of the input signals I1...I5 - input signals I4 and I5 - are supplied to the return logic '1' reset circuit 1503. Since one of the input signals I4 and I5 must be at a low level when the estimated state is established, the return logic '1' reset circuit 1503 is in an isolated state. As long as the regression logic '1' estimation circuit 1501 is in the estimated state, the regression logic '1' reset circuit 1503 must be in its isolated state to ensure normal operation in the manner previously described as a clockless regression logic '0' domino logic gate 800. In addition, the clockless regression logic '1' domino logic gate 1500 can implement a cascade of logic gates using techniques similar to the joint logic gate design 700. In one embodiment, a third N-channel device (not shown) is added to the tandem device between nodes 1110 and 1106 to cause three cascaded N-channel devices to receive input signals I1, I2, and I3. The above-mentioned correction achieves an equivalent logical operation, but the time taken by the regression logic '1' domino circuit 1105 to return to the preset state from the latched state transition state, the state of the three input signals (I1...I3) It takes less time than the two input signals (I4 and I5).
第16圖為一示意方塊圖,圖解一無時脈回歸邏輯’1’骨牌邏輯閘1600,為一邏輯及閘,對M個回歸邏輯’1’輸入信號I1…IM進行邏輯及運算。無時脈回歸邏輯’1’骨牌邏輯閘1600包括一回歸邏輯’1’骨牌電路1105。電路1105耦接一回歸邏輯’1’估算電路1601(用於實現前述回歸邏輯’1’估算電路1101)以及一回歸邏輯’1’重置電路1603(用於實現前述回歸邏輯’1’重置電路1103)。無時脈回歸邏輯’1’骨牌邏輯閘1600之設計基本上類似無時脈回歸邏輯’0’骨牌邏輯閘900,不同之處在於骨牌邏輯閘1600是根據回歸邏輯’1’操作所作出的變形。說明之,與骨牌邏輯閘900相較,骨牌邏輯閘1600以供電電位VDD取代參考電位VSS,且以參考電位VSS取代供電電位VDD,以N通道裝置取代P通道裝置,以P通道裝置取代N通道裝置,令輸入信號I1…15採回歸邏輯’1’設計而非回歸邏輯’0’設計,令輸出信號OUT為回歸邏輯’1’設計而非回歸邏輯’0’設計,且令信號狀態為反相設計。節點302、304、306、308以及310會分別由類似的節點1102、1104、1106、1108與1110取代,以實現於第11…14圖所討論的同等運算。Figure 16 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1600 as a logical AND gate that performs a logical AND operation on the M regression logic '1' input signals I1...IM. The clockless regression logic '1' domino logic gate 1600 includes a regression logic '1' domino circuit 1105. The circuit 1105 is coupled to a regression logic '1' estimation circuit 1601 (for implementing the foregoing regression logic '1' estimation circuit 1101) and a regression logic '1' reset circuit 1603 (for implementing the aforementioned regression logic '1' reset Circuit 1103). The design of the clockless regression logic '1' domino logic gate 1600 is basically similar to the clockless regression logic '0' domino logic gate 900, except that the domino logic gate 1600 is a deformation based on the regression logic '1' operation. . In addition, compared with the domino logic gate 900, the domino logic gate 1600 replaces the reference potential VSS with the power supply potential VDD, and replaces the power supply potential VDD with the reference potential VSS, replaces the P channel device with the N channel device, and replaces the N channel with the P channel device. The device makes the input signal I1...15 return to the logic '1' design instead of the return logic '0' design, so that the output signal OUT is the regression logic '1' design instead of the return logic '0' design, and the signal state is reversed. Phase design. Nodes 302, 304, 306, 308, and 310 are replaced by similar nodes 1102, 1104, 1106, 1108, and 1110, respectively, to implement the equivalent operations discussed in Figures 11...14.
無時脈回歸邏輯’1’骨牌邏輯閘1600為雙配置設計的另外一種實施方式。無時脈回歸邏輯’1’骨牌邏輯閘1600的操作一般符合第13圖所示時序圖。在這個實施例中,估算狀態僅在輸入信號I1…IM全數設定為低準位成立,使P通道裝置PA…PM全數導通,合力將預清輸入輸出端PCLR的準位拉到供電電位VDD。重置狀態會在輸入信號I1…IM中任一者為高準位時成立。在這樣的實施方式中,回歸邏輯’1’估算以及重置電路1601與1603彼此為雙配置設計。根據各種需求,所設計的電路可接受所需數量的輸入信號。參考無時脈回歸邏輯’1’骨牌邏輯閘1400先前的討論,類似地,串接在回歸邏輯’1’估算電路1601內的P通道裝置之數量可能需要限定在特定數量內,以確保電路正常操作。參閱第7圖,邏輯閘701、703與705各自可以採用無時脈回歸邏輯’1’骨牌邏輯閘1600技術的一回歸邏輯’1’邏輯及閘實現。如此一來,可將數個無時脈回歸邏輯’1’骨牌邏輯閘結合或串疊在一起,以對大量的輸入信號進行特定的邏輯運算─例如邏輯及運算。The clockless regression logic '1' domino logic gate 1600 is another implementation of a dual configuration design. The operation of the clockless regression logic '1' domino logic gate 1600 generally conforms to the timing diagram shown in FIG. In this embodiment, the estimation state is established only when the input signals I1...IM are all set to a low level, so that the P channel devices PA...PM are all turned on, and the resultant force pulls the level of the pre-clear input and output terminal PCLR to the power supply potential VDD. The reset state is established when either of the input signals I1...IM is at a high level. In such an embodiment, the regression logic '1' estimate and reset circuits 1601 and 1603 are in a dual configuration design with each other. The circuit is designed to accept the required number of input signals, depending on the requirements. Referring to the previous discussion of the clockless regression logic '1' domino logic gate 1400, similarly, the number of P channel devices cascaded within the regression logic '1' estimation circuit 1601 may need to be limited to a certain number to ensure proper circuit operation. operating. Referring to Figure 7, each of the logic gates 701, 703, and 705 can be implemented using a return logic '1' logic and gate without the clock-return logic '1' domino logic gate 1600 technique. In this way, several clockless regression logic '1' domino logic gates can be combined or cascaded to perform specific logic operations on a large number of input signals, such as logic and operations.
第17圖為一示意方塊圖,圖解一無時脈回歸邏輯’1’骨牌邏輯閘1700,為一邏輯及閘,對M個輸入信號I1…IM進行邏輯及運算,其中採用簡化的重置電路1703。無時脈回歸邏輯’1’骨牌邏輯閘1700基本上類似無時脈回歸邏輯’1’骨牌邏輯閘1600,其中,同樣的元件採用同樣的編號,而回歸邏輯’1’重置電路1603改由回歸邏輯’1’重置電路1703取代。無時脈回歸邏輯’1’骨牌邏輯閘1700一般符合第13圖所示時序圖。回歸邏輯’1’重置電路1703僅具有一個N通道裝置NA,以源極耦接N通道裝置N1的汲極於節點1110,且以汲極耦接重置節點1106。輸入信號I1…IM其中任一個─通常標示為IX─將供應給N通道裝置NA之閘極。Figure 17 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1700, which is a logic and gate, logically ANDing M input signals I1...IM, wherein a simplified reset circuit is employed 1703. The clockless regression logic '1' domino logic gate 1700 is basically similar to the clockless regression logic '1' domino logic gate 1600, in which the same components are numbered the same, and the return logic '1' reset circuit 1603 is changed by The return logic '1' reset circuit 1703 is replaced. Clock-free Regression Logic '1' Domino Logic Gate 1700 generally conforms to the timing diagram shown in Figure 13. The return logic '1' reset circuit 1703 has only one N-channel device NA, the source is coupled to the drain of the N-channel device N1 to the node 1110, and the reset node 1106 is coupled with the drain. Any of the input signals I1...IM, generally designated IX, will be supplied to the gate of the N-channel device NA.
無時脈回歸邏輯’1’骨牌邏輯閘1700之運算與無時脈回歸邏輯’0’骨牌邏輯閘1600等效,不同之處在於骨牌邏輯閘1700為一非雙配置設計實施方式。無時脈回歸邏輯’1’骨牌邏輯閘1700的操作基本上類似無時脈回歸邏輯’1’骨牌邏輯閘1600,不同處在於重置狀態僅在輸入信號IX為高準位才成立。當輸入信號I1…IM─包括輸入信號IX─各個都轉態為低準位,重置狀態不成立,且估算事件發生。當輸入信號IX轉態為邏輯’0’,估算狀態不成立,且重置狀態成立,引發一重置事件使無時脈回歸邏輯’1’骨牌電路1105回歸其預置狀態。無時脈回歸邏輯’1’骨牌邏輯閘1700的優勢在於其回歸邏輯’1’重置電路較簡化,僅有一個N通道裝置包含於其中,然而,若輸入信號IX轉態回邏輯’1’的速度較其他輸入信號慢,則會有反應速度問題。無時脈回歸邏輯’1’骨牌邏輯閘1600的優點在於可能有較快的反應速度,原因是估算事件後,一旦輸入信號中有任一者轉態為邏輯’1’,即會引發重置事件,代價是回歸邏輯’1’重置電路的設計會較複雜。骨牌邏輯閘1700的速度問題可由以下方式避免:令輸入信號IN中,可最快速轉態為邏輯’1’的輸入信號為所述輸入信號IX。The operation of the clockless regression logic '1' domino logic gate 1700 is equivalent to the clockless regression logic '0' domino logic gate 1600, except that the domino logic gate 1700 is a non-dual configuration design implementation. The operation of the clockless regression logic '1' domino logic gate 1700 is substantially similar to the clockless regression logic '1' domino logic gate 1600, except that the reset state is only true if the input signal IX is at a high level. When the input signals I1...IM, including the input signal IX, are each transitioned to a low level, the reset state is not established and an estimated event occurs. When the input signal IX transitions to logic '0', the estimated state is not true and the reset state is asserted, causing a reset event to cause the clockless regression logic '1' domino circuit 1105 to return to its preset state. The advantage of the clockless regression logic '1' domino logic gate 1700 is that its return logic '1' reset circuit is simplified, only one N channel device is included, however, if the input signal IX transitions back to logic '1' The speed is slower than other input signals, and there is a problem with the speed of response. The advantage of the clockless regression logic '1' domino logic gate 1600 is that there may be a faster response speed because after any event is estimated, once any of the input signals transitions to a logic '1', a reset is initiated. The cost of the event is that the design of the return logic '1' reset circuit is more complicated. The speed problem of the domino logic gate 1700 can be avoided by making the input signal IN, the input signal that can be most rapidly transitioned to logic '1', the input signal IX.
回顧無時脈回歸邏輯’1’骨牌邏輯閘1100,令其中採用依照第13圖時序圖操作的回歸邏輯’1’骨牌電路1200,無時脈回歸邏輯’1’骨牌邏輯閘1100在輸入信號根據回歸邏輯’1’操作處於(或轉態到)邏輯’1’時處於(或轉態到)初始預設狀態。當輸入信號使估算狀態成立,重置狀態不成立且一估算事件被引發。估算狀態成立時,重置狀態維持不成立。估算狀態成立後,若供應給重置電路的輸入信號轉態回其預設邏輯’1’狀態時,重置狀態成立。重置最終根據回歸邏輯’1’操作發生。以無時脈回歸邏輯’1’骨牌邏輯閘1400為例,重置事件發生於各個輸入信號I1…IM皆轉態回邏輯’1’時。以無時脈回歸邏輯’1’骨牌邏輯閘1500為例,重置事件發生於輸入信號I1…I5的一子集合-輸入信號I4與I5-轉態為邏輯’1’時。以無時脈回歸邏輯’1’骨牌邏輯閘1600為例,重置事件發生於輸入信號I1…IM中任一者轉態回邏輯’1’時。以無時脈回歸邏輯’1’骨牌邏輯閘1700為例,重置事件發生於輸入信號中選定的該個信號-稱之為輸入信號IX-轉態為邏輯’1’時。Recall that there is no clock return logic '1' domino logic gate 1100, which uses the regression logic '1' domino circuit 1200 operating according to the timing diagram of Figure 13, no clock return logic '1' domino logic gate 1100 in the input signal according to The return logic '1' operation is (or transitioned to) the initial preset state when it is (or transitioned to) logic '1'. When the input signal causes the estimated state to be true, the reset state is not established and an estimated event is raised. When the estimated state is established, the reset state remains unchanged. After the estimation state is established, the reset state is established if the input signal supplied to the reset circuit is returned to its preset logic '1' state. The reset eventually occurs according to the regression logic '1' operation. Taking the clockless regression logic '1' domino logic gate 1400 as an example, the reset event occurs when each of the input signals I1...IM is turned back to logic '1'. Taking the clockless regression logic '1' domino logic gate 1500 as an example, the reset event occurs when a subset of the input signals I1...I5 - the input signals I4 and I5 - transition to logic '1'. Taking the clockless regression logic '1' domino logic gate 1600 as an example, the reset event occurs when any of the input signals I1...IM transitions back to logic '1'. Taking the clockless regression logic '1' domino logic gate 1700 as an example, the reset event occurs when the selected signal in the input signal is referred to as the input signal IX-transition to logic '1'.
雖然以上盡力詳述本發明數種較佳實施方式,仍可能有其他實施方式或變形存在。例如,上述電路可以任何包括邏輯裝置或電路之類的其他合適方案實現。所介紹之邏輯電路的任何數量之運算可由軟體或韌體或積體裝置內類似技術實現。所述電路可包括反相裝置,以實行正相或反相邏輯或其他可將信號反轉的技術。所揭露的技術採用的電路運算可為數位、二進位位元組或字元,本技術領域所熟知,關於任何位元數量之數位或二進位電路應用。熟知本技術領域人士或許會以上述內容所揭露的概念與實施例為基礎,設計或調適其餘結構,在不違背本發明精神的前提下,根據以下請求項所定義的範圍,實現與本發明相同的作用。While the above-described several preferred embodiments of the invention have been described in detail, it is possible that other embodiments or variations may be present. For example, the above circuits can be implemented in any other suitable manner including logic devices or circuits. Any number of operations of the described logic circuits can be implemented by software or similar techniques within a firmware or integrated device. The circuitry can include an inverting device to perform normal phase or inverting logic or other techniques that can invert the signal. The circuit operations employed by the disclosed techniques can be digital, binary, or word, as is well known in the art, with respect to digital or binary circuit applications for any number of bits. Those skilled in the art will be able to design or adapt the remaining structures based on the concepts and embodiments disclosed above, and the same as defined in the following claims, without departing from the spirit of the present invention. The role.
101...積體電路101. . . Integrated circuit
103...狀態回歸邏輯103. . . State regression logic
104...非狀態回歸邏輯104. . . Non-state regression logic
105...無時脈狀態回歸骨牌電路105. . . No clock state return to the domino circuit
107...邏輯電路107. . . Logic circuit
200...無時脈狀態回歸骨牌邏輯閘200. . . No clock state return to domino logic gate
201...狀態回歸估算電路201. . . State regression estimation circuit
202...預置節點202. . . Preset node
203...狀態回歸重置電路203. . . State regression reset circuit
204...狀態回歸致能節點204. . . State regression enable node
205...狀態回歸骨牌電路205. . . State regression domino circuit
206...重置節點206. . . Reset node
207...狀態回歸致能電路207. . . State regression enabling circuit
208...輸出節點208. . . Output node
210...第二重置節點210. . . Second reset node
300...無時脈回歸邏輯’0’骨牌邏輯閘300. . . Clock-free regression logic '0' domino logic gate
301...回歸邏輯’0’估算電路301. . . Regression logic '0' estimation circuit
302...預充節點302. . . Precharge node
303...回歸邏輯’0’重置電路303. . . Regression logic '0' reset circuit
304...回歸邏輯’0’致能節點304. . . Regression logic '0' enable node
305...回歸邏輯’0’骨牌電路305. . . Regression logic '0' domino circuit
306...重置節點306. . . Reset node
308...輸出節點308. . . Output node
310...第二重置節點310. . . Second reset node
400...回歸邏輯’0’骨牌電路400. . . Regression logic '0' domino circuit
401...反相器401. . . inverter
402...半維持電路402. . . Semi-sustained circuit
403、405...反相器403, 405. . . inverter
501...標示雙配置設計之第二狀態信號RESET的反應501. . . The response of the second state signal RESET indicating the dual configuration design
600...無時脈回歸邏輯’0’骨牌邏輯閘600. . . Clock-free regression logic '0' domino logic gate
601...回歸邏輯’0’估算電路601. . . Regression logic '0' estimation circuit
603...回歸邏輯’0’重置電路603. . . Regression logic '0' reset circuit
700...聯合邏輯閘設計700. . . Joint logic gate design
701、703、705...無時脈狀態回歸骨牌邏輯閘701, 703, 705. . . No clock state return to domino logic gate
800...無時脈回歸邏輯’0’骨牌邏輯閘800. . . Clock-free regression logic '0' domino logic gate
801...回歸邏輯’0’估算電路801. . . Regression logic '0' estimation circuit
802...中繼節點802. . . Relay node
803...回歸邏輯’0’重置電路803. . . Regression logic '0' reset circuit
900...無時脈回歸邏輯’0’骨牌邏輯閘900. . . Clock-free regression logic '0' domino logic gate
901...回歸邏輯’0’估算電路901. . . Regression logic '0' estimation circuit
903...回歸邏輯’0’重置電路903. . . Regression logic '0' reset circuit
1000...無時脈回歸邏輯’0’骨牌邏輯閘1000. . . Clock-free regression logic '0' domino logic gate
1003...回歸邏輯’0’重置電路1003. . . Regression logic '0' reset circuit
1100...無時脈回歸邏輯’1’骨牌邏輯閘1100. . . Clock-free regression logic '1' domino logic gate
1101...回歸邏輯’1’估算電路1101. . . Regression logic '1' estimation circuit
1102...預清節點1102. . . Pre-clear node
1103...回歸邏輯’1’重置電路1103. . . Regression logic '1' reset circuit
1104...回歸邏輯’1’致能節點1104. . . Regression logic '1' enabling node
1105...回歸邏輯’1’骨牌電路1105. . . Regression logic '1' domino circuit
1106...重置節點1106. . . Reset node
1108...輸出節點1108. . . Output node
1110...第二重置節點1110. . . Second reset node
1200...回歸邏輯’1’骨牌電路1200. . . Regression logic '1' domino circuit
1201...反相器1201. . . inverter
1202...半維持電路1202. . . Semi-sustained circuit
1203、1205...反相器1203, 1205. . . inverter
1400...無時脈回歸邏輯’1’骨牌邏輯閘1400. . . Clock-free regression logic '1' domino logic gate
1401...回歸邏輯’1’估算電路1401. . . Regression logic '1' estimation circuit
1403...回歸邏輯’1’重置電路1403. . . Regression logic '1' reset circuit
1500...無時脈回歸邏輯’1’骨牌邏輯閘1500. . . Clock-free regression logic '1' domino logic gate
1501...回歸邏輯’1’估算電路1501. . . Regression logic '1' estimation circuit
1502...中繼節點1502. . . Relay node
1503...回歸邏輯’1’重置電路1503. . . Regression logic '1' reset circuit
1600...無時脈回歸邏輯’1’骨牌邏輯閘1600. . . Clock-free regression logic '1' domino logic gate
1601...回歸邏輯’1’估算電路1601. . . Regression logic '1' estimation circuit
1603...回歸邏輯’1’重置電路1603. . . Regression logic '1' reset circuit
1700...無時脈回歸邏輯’1’骨牌邏輯閘1700. . . Clock-free regression logic '1' domino logic gate
1703...回歸邏輯’1’重置電路1703. . . Regression logic '1' reset circuit
CLK...時脈信號CLK. . . Clock signal
EVAL...第一狀態信號EVAL. . . First state signal
I1…I6...輸入信號I1...I6. . . input signal
11(RT0)…IM(RT0)、IX(RT0)...回歸邏輯’0’輸入信號11(RT0)...IM(RT0), IX(RT0). . . Return logic '0' input signal
I1(RT1)…IM(RT1)、IX(RT1)...回歸邏輯’1’輸入信號I1(RT1)...IM(RT1), IX(RT1). . . Return logic '1' input signal
IN...輸入信號IN. . . input signal
IN(NON-RTS)...非狀態回歸輸入信號IN(NON-RTS). . . Non-state regression input signal
IN(RTS)...狀態回歸輸入信號IN(RTS). . . State regression input signal
N1、N2、NA…NM...N通道裝置N1, N2, NA...NM. . . N channel device
O1(RST)、O2(RST)...輸出信號O1 (RST), O2 (RST). . . output signal
OUT...輸出端OUT. . . Output
OUT(RT0)...回歸邏輯’0’輸出信號OUT(RT0). . . Return logic '0' output signal
OUT(RT1)...回歸邏輯’1’輸出信號OUT (RT1). . . Return logic '1' output signal
OUT(RTS)...狀態回歸輸出信號OUT (RTS). . . State regression output signal
P1、P2、P3、PA…PM...P通道裝置P1, P2, P3, PA...PM. . . P channel device
PCHG...預充輸入輸出端/信號PCHG. . . Precharge input/output/signal
PCLR...預清輸入輸出端/信號PCLR. . . Pre-clear input/output/signal
PSET...預置輸入輸出端PSET. . . Preset input and output
RESET...第二狀態信號RESET. . . Second state signal
RST...重置信號RST. . . Reset signal
RSTB...反相重置信號RSTB. . . Inverted reset signal
RT0E...回歸邏輯’0’致能信號RT0E. . . Regression logic '0' enable signal
RT1E...回歸邏輯’1’致能信號RT1E. . . Regression logic '1' enable signal
RTSE...狀態回歸致能信號RTSE. . . State regression enable signal
T0…T14...時間點T0...T14. . . Time point
VDD...供電電位VDD. . . Supply potential
VSRC1、VSRC2...電源電位VSRC1, VSRC2. . . Power supply potential
VSS...參考電位VSS. . . Reference potential
以下敘述將有助於了解本發明的優點、特徵以及改善內容,配合的圖示包括: 第1圖為一簡化的方塊圖,描述一晶片或一積體電路,其中包括根據本發明一種實施方式所實現的一無時脈狀態回歸骨牌電路;第2圖為一方塊圖,圖解根據本發明一種實施方式所實現的一無時脈狀態回歸骨牌邏輯閘,可被用來實現第1圖無時脈狀態回歸骨牌電路內的一個或多個無時脈狀態回歸骨牌邏輯閘;第3圖為一示意方塊圖,圖解根據第2圖無時脈狀態回歸骨牌邏輯閘一種回歸邏輯’0’實施方式所實現的一無時脈回歸邏輯’0’骨牌邏輯閘;第4圖為一回歸邏輯’0’骨牌電路的示意圖,圖解第3圖回歸邏輯’0’骨牌電路的一種實施方式;第5圖為一時序圖,圖解第3圖無時脈回歸邏輯’0’骨牌邏輯閘的操作,其中採用第4圖之回歸邏輯’0’骨牌電路的一種實施方式;第6圖為一示意方塊圖,圖解一無時脈回歸邏輯’0’骨牌邏輯閘,用以實現一邏輯或閘,對M個輸入信號I1…IM進行邏輯或運算;第7圖為一簡化方塊圖,圖解一串疊邏輯閘設計,其中有三個耦接在一起的無時脈狀態回歸骨牌邏輯閘,用以實現一邏輯運算;第8圖為一示意方塊圖,圖解根據本發明另一種實施方式實現的一無時脈狀態回歸骨牌邏輯閘,用以實現多樣化的邏輯運算;第9圖為一示意方塊圖,圖解一無時脈回歸邏輯’0’骨牌邏輯閘,用以實現一邏輯及運算,對M個回歸邏輯’0’輸入信號I1…IM進行邏輯及運算;The following description will be helpful in understanding the advantages, features, and improvements of the present invention. 1 is a simplified block diagram depicting a wafer or an integrated circuit including a clockless state return domino circuit implemented in accordance with an embodiment of the present invention; and FIG. 2 is a block diagram illustrating A clockless state return domino logic gate realized by an embodiment of the invention can be used to implement one or more clockless state regression domino logic gates in the domino circuit state without the clock state in FIG. 1; FIG. For a schematic block diagram, a clockless regression logic '0' domino logic gate implemented by a regression logic '0' implementation according to Fig. 2 without clocking state returning to the domino logic gate; Fig. 4 is a regression logic Schematic diagram of the '0' domino circuit, illustrating an embodiment of the return logic '0' domino circuit of Fig. 3; Fig. 5 is a timing diagram illustrating the operation of the novo clock return logic '0' domino logic gate of Fig. 3, One embodiment of the regression logic '0' domino circuit of FIG. 4 is used; and FIG. 6 is a schematic block diagram illustrating a clockless return logic '0' domino logic gate for implementing a logic or gate. M input signals I1...IM are logically ORed; Figure 7 is a simplified block diagram illustrating a cascade of logic gate designs in which three clockless state-returned domino logic gates are coupled together to implement a Logic operation; FIG. 8 is a schematic block diagram illustrating a clockless state return domino logic gate implemented in accordance with another embodiment of the present invention for implementing diverse logic operations; FIG. 9 is a schematic block diagram, Graphical a clockless regression logic '0' domino logic gate, used to implement a logical AND operation, logically AND operations on M regression logic '0' input signals I1...IM;
第10圖為一示意方塊圖,圖解另一個無時脈回歸邏輯’0’骨牌邏輯閘,用以實現一邏輯及閘,對M個回歸狀態’0’輸入信號I1…IM作邏輯及運算,其中包括一簡化的重置電路;Figure 10 is a schematic block diagram illustrating another clockless return logic '0' domino logic gate for implementing a logic and gate, and logically ANDing the M regression state '0' input signals I1...IM, Which includes a simplified reset circuit;
第11圖為一示意方塊圖,圖解一無時脈回歸邏輯’1’骨牌邏輯閘,乃根據第2圖的無時脈狀態回歸骨牌邏輯閘的一種回歸邏輯’1’實施方式實現;Figure 11 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate, which is implemented according to a regression logic '1' implementation of the clockless state returning domino logic gate of Fig. 2;
第12圖為回歸邏輯’1’骨牌電路一示意圖,圖解第11圖回歸邏輯’1’骨牌電路的一種實施方式;Figure 12 is a schematic diagram of a regression logic '1' domino circuit, illustrating an embodiment of the return logic '1' domino circuit of Figure 11;
第13圖為一時序圖,用以說明第11圖無時脈回歸邏輯’1’骨牌邏輯閘的操作,其中採用第12圖回歸邏輯’1’骨牌電路的一種實施方式;Figure 13 is a timing diagram for explaining the operation of the Fig. 11 without the clock return logic '1' domino logic gate, wherein an embodiment of the logic logic '1' domino circuit of Fig. 12 is employed;
第14圖為一示意方塊圖,圖解一無時脈回歸邏輯’1’骨牌邏輯閘,其中實現一邏輯或閘,對M個回歸邏輯’1’輸入信號I1…IM作邏輯或運算;Figure 14 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate in which a logic OR gate is implemented to logically OR the M regression logic '1' input signals I1...IM;
第15圖為一無時脈回歸邏輯’1’骨牌邏輯閘1500的一示意方塊圖,乃根據另一種實施方式所製,用以執行一多樣化的邏輯運算;Figure 15 is a schematic block diagram of a clockless regression logic '1' domino logic gate 1500, which is constructed in accordance with another embodiment for performing a variety of logic operations;
第16圖為一無時脈回歸邏輯’1’骨牌邏輯閘的一示意方塊圖,用以實現一邏輯及閘,對M個回歸邏輯’1’輸入信號I1…IM作邏輯及運算;且Figure 16 is a schematic block diagram of a clockless return logic '1' domino logic gate for implementing a logic AND gate to logically AND the M regression logic '1' input signals I1...IM;
第17圖為另一個無時脈回歸邏輯’1’骨牌邏輯閘的一示意方塊圖,用以實現一邏輯及閘,對M個回歸邏輯’1’入信號I1…IM進行邏輯及運算,其中包括有一簡化的重置電路。Figure 17 is a schematic block diagram of another clockless logic logic '1' domino logic gate for implementing a logic and gate, and performing logical AND operations on M regression logic '1' input signals I1...IM, wherein Includes a simplified reset circuit.
200...無時脈狀態回歸骨牌邏輯閘200. . . No clock state return to domino logic gate
201...狀態回歸估算電路201. . . State regression estimation circuit
202...預置節點202. . . Preset node
203...狀態回歸重置電路203. . . State regression reset circuit
204...狀態回歸致能節點204. . . State regression enable node
205...狀態回歸骨牌電路205. . . State regression domino circuit
206...重置節點206. . . Reset node
207...狀態回歸致能電路207. . . State regression enabling circuit
208...輸出節點208. . . Output node
210...第二重置節點210. . . Second reset node
IN...輸入信號IN. . . input signal
OUT...輸出端OUT. . . Output
OUT(RTS)...狀態回歸輸出信號OUT (RTS). . . State regression output signal
PSET...預置輸入輸出端PSET. . . Preset input and output
RST...重置信號RST. . . Reset signal
RTSE...狀態回歸致能信號RTSE. . . State regression enable signal
VSRC1、VSRC2...電源電位VSRC1, VSRC2. . . Power supply potential
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US12/839,630 US7936185B1 (en) | 2010-07-20 | 2010-07-20 | Clockless return to state domino logic gate |
US12/839,558 US7940087B1 (en) | 2010-07-20 | 2010-07-20 | Clockless return to state domino logic gate |
US12/839,586 US7990181B1 (en) | 2010-07-20 | 2010-07-20 | Clockless return to state domino logic gate |
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