TWI478497B - Clockless return to state domino logic gate and integrated circuit and logic function evaluation method corresponding thereto - Google Patents

Description

No-clock state regression domino logic gate and related integrated circuit and logic operation estimation method

The present invention relates to logic circuits, and particularly relates to a self-resetting return to state (RTS) domino logic gate, the operation of which does not depend on a clock signal, and is used to respond to state regression. (RTS) signal.

The setting of logic circuits on integrated circuits (ICs) is usually done for fast execution of logic operations, so there are many possible layouts. In many instances, directing a clock signal to a circuit that provides logic operations is difficult and difficult to implement. Including static as well as dynamic logic gates and circuits, most logic circuits need to operate according to an input clock. The static complementary MOS logic gate operates at a relatively low energy, but has a considerable input capacitance, and the signal is complementary. The P-type device and the N-type device are in a mutual force. Therefore, the static complementary MOS logic is half-logic. The operation of the gate is quite slow. Dominos are faster than the opposite static devices, but are almost always controlled by an input clock signal.

This field of technology requires a logic circuit or logic gate that can perform logic operations in a faster and more efficient manner without the need for a clock signal.

A clockless state return domino logic gate formed according to an embodiment of the present invention has a plurality of nodes, a domino circuit, an estimating circuit, a matching circuit, and a reset circuit. Each of the above nodes is designed to switch between a first state and a second state. Each of the input nodes is set to the first state, and then returns to the second state according to the state regression operation. The domino circuit has a preset state and a latched state. When the domino circuit is in the preset state, the domino circuit sets a preset node and a consistent energy node to the first state, and sets the output node and a first reset node to the second state. When the preset node transitions to the second state, the domino circuit switches to the latched state to transition the output node to the first state and to transition the enable node to the second state. When the first reset node transitions to the first state, the domino circuit resets to the preset state. When the input node is in any one of the at least one estimated state, the estimating circuit shifts the preset node to the second state, and vice versa, the estimating circuit does not affect the level of the preset node. When the enabling node is in the second state, the enabling circuit switches the second reset node to the first state, and vice versa, the enabling circuit does not affect the level of the second reset node. The reset circuit couples the first and second reset nodes together when the input node is not any of the at least one estimated state. The reset circuit isolates the first and second reset nodes from each other when the input node is any of the at least one estimated state. The estimation circuit and the reset circuit can be designed in a dual configuration with each other. The state regression technique may be implemented by a regression logic '0' design for responding to the return logic '0' input signal, or may be implemented by a regression logic '1' design for responding to the return logic '1' input signal.

An integrated circuit implemented in accordance with an embodiment of the present invention includes a first logic and a clockless state return domino logic gate. The first logic supplies a plurality of state regression signals. The state regression signals are each switched to a first state and a second state. Regarding each state regression signal, after being set to the first state, the first logic sets each state regression signal to the second state according to the state regression operation. The clockless state return domino logic gate includes a preset node, a consistent energy node, an output node, and a first and a second reset node, each of which switches to the first and second states. The clockless state return domino logic gate further includes a domino circuit, an estimation circuit, a uniformity circuit, and a reset circuit.

A logic operation estimation method implemented in accordance with an embodiment of the present invention. The method includes receiving a plurality of state regression signals. Regarding each state regression signal, a second state is returned according to the state regression operation after being set to a first state. The method further includes supplying a domino circuit having a preset state and a latched state. When the domino circuit is in the preset state, a preset node and a consistent energy node are set to a first state, and an output node and a reset node are set to a second state. When the preset node is transitioned to the second state, the domino circuit switches to the latched state. When the reset node transitions to the first state, the domino circuit transitions back to the preset state to transition the output node to the first state and transitions the enable node to the second state. The method further includes estimating the state regression input signal, wherein when the state regression input signal is in any of the at least one estimated state, transitioning the preset node to the second state causes the domino circuit to switch to Latched state. The method is further included when the enabling node is in the second state and the state regression signal is no longer any of the at least one estimated state, and the reset node is in the first state to reset the domino circuit For this preset state.

A clockless state return domino logic gate formed according to an embodiment of the present invention has a plurality of nodes, a domino circuit, an estimation circuit, a uniformity circuit, and a reset circuit. Each node switches to a first state and a second state. At least one input node is a state regression node, and after being set to the first state, the second state is returned according to the state regression operation. The domino circuit has a preset state and a latched state. When the domino circuit is in the preset state, the domino circuit sets a preset node and a consistent energy node to the first state, and sets an output node and a first reset node to the second state. When the preset node is pulled to the second state, the domino circuit switches to the latched state to pull the output node to the first state and pull the enabling node to the second state. When the first reset node is pulled to the first state, the domino circuit is reset back to the preset state. When the input node is in any of the at least one estimated state, the estimating circuit pulls the preset node to the second state; otherwise, the estimating circuit does not interfere with the level of the preset node. The enabling circuit pulls the second reset node to the first state when the enabling node is in the second state. When the input node is not in any of the at least one estimated state, the reset circuit couples the first and second reset nodes together; otherwise, the reset circuit converts the first and second weights The nodes are isolated from each other.

The state regression technique described above can be implemented as a regression logic '0' architecture for responding to the return logic '0' input signal. Alternatively, the state regression technique described above can be implemented as an architecture of regression regression logic '1' for responding to the return logic '1' input signal. The estimation circuit and the reset circuit can be used to jointly perform any required logic operation or function, and need not be limited to each other's dual configuration design. In one embodiment, the estimation circuit corresponds to the aggregate state of the input node, and the reset circuit is coupled to the input node that is less than the total number of input nodes. Regarding the input nodes provided to the reset circuit, each is a state regression node.

As for an integrated circuit fabricated in accordance with an embodiment of the present invention, the first logic and a clockless state are returned to the domino logic gate. The first logic provides at least one state regression signal, switching to a first state and a second state. Regarding each state regression signal, the first logic sets the state regression signal back to the second state according to the state regression operation after the state regression signal is set to the first state. The clockless state return domino logic gate has a preset node, a consistent energy node, an output node, and a first and a second reset node; each of the nodes switches in the first and second states. The clockless state return domino logic gate further includes a domino circuit, an estimation circuit, a uniformity circuit, and a reset circuit.

As for a method of estimating a logical operation formed according to an embodiment of the present invention, the following steps are included. First, a plurality of input signals are received, each of which switches between a first state and a second state. In addition, a domino circuit is provided that operates in a preset state and a latched state. In the preset state, the domino circuit sets a preset node and a consistent energy node to a first state, and sets an output node and a reset node to a second state. When the preset node is pulled to the second state, the domino circuit switches to the latched state, transitions the output node to the first state, and pulls the enabling node to the second state. When the reset node is pulled to the first state, the domino circuit is reset back to the preset state. The method further includes: estimating the state regression input signal, and when the state regression input signal is in any one of the at least one estimation state, pulling the preset node to the second state to transition the domino circuit to the latch status. The method further includes: when the enabled node is in the second state and the state regression input signal is not any one of the at least one estimated state, pulling the reset node to the first state to reset the domino Circuit. The input signal includes at least one state regression signal, and after being set to the first state, returns to the second state according to the state regression operation.

A clockless state return domino logic gate implemented in accordance with an embodiment of the present invention includes a domino circuit and an input circuit. The clockless state return domino logic gate is responsive to a plurality of input logic signals, wherein each input logic signal is designed to switch between the first and second logic states. The domino circuit includes three inverters, a first and a second device having a first conductive form, and a device having a second conductive form. The first inverter is coupled between the input and output nodes. The second inverter is coupled between the output node and the consistent energy node. The third inverter is coupled to the first reset node by the input end. The first device of the first conductive form has a control end coupled to the output node, a first current terminal coupled to the first power potential node with respect to the first logic state, and a second current terminal coupled to the pre-predator Set the node. The first device of the second conduction state has a first current end coupled to a second power supply potential of the second logic state, a control terminal coupled to the enable node, and a second current terminal coupled to the first Reset the node. The second device of the first conduction mode has a first current terminal coupled to the first power potential node, a control terminal coupled to the output terminal of the third inverter, and a second current terminal coupled to the preset node. When the input logic signal is in an estimated state, the input circuit pulls the preset node to the second logic state. When the input signal transitions away from the estimated state, the input circuit temporarily pulls the first reset node to the first logic state.

In one embodiment, the input circuit includes an estimation circuit, a uniformity circuit, and a reset circuit. When the input logic signal is in an estimated state, the estimating circuit pulls the preset node to the second logic state. When the enabling node is in the second logic state, the enabling circuit pulls a second reset node to the first logic state. The reset circuit is coupled to the first reset node to the second reset node when the input logic signal is not in the estimated state. In one embodiment, the first power supply potential node has a positive power supply potential, the second power supply potential node has a reference potential, the first conductive form is a semiconductor P-type design, and the second conductive form is a semiconductor N Type design. In another embodiment, the first power supply potential node has a reference potential, the second power supply potential node has a positive power supply potential, the first conductive form is a semiconductor N-type design, and the second conductive form is a semiconductor P-type design. The input signal may include at least one state regression signal that may be returned to logic '1' or regression logic '0' depending on the design.

An integrated circuit implemented in accordance with an embodiment of the present invention includes at least one clockless state return domino logic gate and a first circuit. The first circuit supplies at least one state regression signal, and after the state regression signal is set to the first state, is set to the second state according to the state regression operation. The no-clock state return to the domino logic gate can be designed in a similar manner as described above.

A method of estimating multiple input logic signals. The input logic signals include at least one state regression input signal. The method includes setting a preset node to a first logic state, the first logic state being an inversion of a second logic state. The method further includes inverting the preset node to determine a logic state of an output node, inverting the output node to determine a logic state of the consistent energy node, and shifting the state when the enable node is in the first logic state Setting a node to the second logic state, inverting the reset node to determine a logic state of an inverting reset node, and transitioning the preset node to the inverting reset node when the second logic state is a first logic state, when the input signal forms an estimated state, forcing the preset node to the second logic state, and supplying at least one state regression signal that is transitioned to the second logic state after the transition state is the first logic state, And forcing the reset node to be the first logic state when the enable node is in the second logic state and the input signal trips the estimated state according to the state regression operation. In addition, when the reset node is forced to the first logic state, the inverting reset node returns to the second logic state, and then, the preset node is in the first logic state, and then, the transition state is Returning the node to the second logic state, and then transitioning the enable node back to the first logic state, then transitioning the reset node back to the second logic state, and then transitioning the inverted logic state The node returns to the first logical state.

The following description will assist those skilled in the art to make and use the invention disclosed herein. A person skilled in the art may develop various modifications in accordance with the embodiments disclosed below, and the techniques disclosed in the specification may be implemented in other embodiments. Therefore, the scope of the invention is not intended to be limited The inventors have discovered a need in the industry for high speed, efficient, and logical operations that do not rely on clock signals. Therefore, the inventors developed a state-return domino logic gate without the need for a clock signal, which is discussed below in Figures 1-17.

1 is a simplified block diagram illustrating a wafer (or integrated circuit, IC) 101 including a clockless return to state domino circuit implemented in accordance with an embodiment of the present invention. ) 105. The integrated circuit 101 can be of any type and can include any number of electronic circuits that have been developed in the art. In one embodiment, the wafer 101 is a processor, such as a microcontroller or microprocessor, and the like, and any type of integrated circuit or wafer may be used for it. A clock signal CLK is disposed on the integrated circuit 101 and is received by a state regression logic 103. The state regression logic 103 outputs one or more state regression input signals IN (RTS) to a plurality of input nodes coupled to the corresponding inputs of the clockless state regression domino circuit 105. The clock signal CLK is also routed to the NON-RTS logic 104. The non-state regression logic 104 outputs one or more non-state regression signals IN (NON-RTS) to a plurality of inputs coupled to the corresponding inputs of the clockless state regression domino circuit 105. This is described in more detail below. The content of the input signal IN (the combination of IN (RTS) and IN (NON-RTS)) will vary depending on the design of the clockless state return domino circuit 105. In some applications (eg, dual configurations), each input signal IN is a state regression signal RTS (exemplified by a logic or gate design). In addition, in other applications (for example, non-dual configuration), at least one of the input signals IN is a state regression signal RTS, and the remaining signals in the input signal IN are state regression signals RTS or non- The state returns to the NON-RTS signal. Generally, it is necessary to develop and provide the above state regression signal under the following conditions. The clockless state return domino circuit 105 outputs one or more state regression output signals OUT (RTS) to the associated input of another logic circuit 107, and the clock signal CLK is also coupled to the clock input of the logic circuit 107. . State regression logic 103 includes any combination of static or dynamic circuitry, and further includes any combination of latch or scratchpad circuitry to provide an input signal IN (RTS) in accordance with a state regression operation. Logic 107 includes any combination of static or domino circuits (footed or footless) and/or any combination of latches or registers to receive, or latch, or temporarily store the output signal OUT ( RTS).

The state regression input and output signals IN and OUT represent that the signal will return to a predetermined state or a first state after switching to a second state. In binary logic, state regression does not return to logic '0' (RT0, whose default logic state is logic '0'), or returns to logic '1' (RT1, whose default logic state is logic '1' '). The no-vehicle state return domino circuit 105 includes one or more clockless state return domino logic gates. The clockless state return domino logic gates are cascaded to each other or coupled together according to any series or parallel connection. A variety of non-synchronous state return domino logic gates have the opportunity to be cascaded or concatenated together, limited only by time conditions, which are defined by whether the corresponding output signal is valid or not. Each clockless state return domino logic gate can receive any number of state regression input signals and output at least one state regression output signal to other circuits - including other no clock state return domino logic gates, or logic circuit 107, or the like Circuit.

FIG. 2 is a block diagram illustrating a clockless state return domino logic gate 200 implemented in accordance with an embodiment of the present invention for effecting one or more clockless states in the clockless state return domino circuit 105. Return to the domino logic gate. One or more signals in the input signal IN are supplied to the corresponding input node for input to a corresponding input of a state regression estimation circuit 201, and at least one of the above-described input signals IN is supplied to a state regression reset circuit 203. Although the same input signal IN is supplied to both circuits 201 and 203, in some embodiments - as will be discussed in detail below - only the input signal IN may be supplied to the state return reset circuit 203. A collection of ones. Additionally, the input signal IN can be a state regression signal (RTS) or can include one or more non-state regression signals (non-RTS). The clockless state return domino logic gate 200 further includes a state return domino circuit 205; the state return domino circuit 205 is coupled to a pair of power supply potentials VSRC1 and VSRC2. The power supply potentials VSRC1 and VSRC2 are each provided by a power supply circuit (not shown in the figure), and the power supply potential is uniformly supplied to a plurality of electronic circuits on the integrated circuit 101 at an appropriate potential, and the adopted technology can be a common technology in the technical field. . The potential supplied by each of the power supply potentials and the potential interval corresponding to the power supply potentials VSRC1 and VSRC2 are related to the circuit type and the particular technique or process, for example, 5 volts, 3.3 volts, or 2.1 volts. Typically, one of the power supply potentials VSRC1 and VSRC2 is a reference potential (e.g., VSS) and the other is a supply potential VDD, which can be implemented by techniques common in the art. The state regression estimation circuit 201, the state regression reset circuit 203, and the state regression enable circuit 207 can collectively constitute an input circuit that operates in response to the input signal IN.

The state regression estimation circuit 201 is coupled to the power supply potential VSRC2, and is further coupled to a preset node 202 for coupling to a preset input/output terminal PSET of the state return domino circuit 205. The state return domino circuit 205 has an output that supplies a state regression output signal OUT (RTS) to an output node 208, and has a reset input and output terminal RST that generates a reset signal (also labeled as RST) for a reset. Node 206, and also having a state regression enable signal output terminal RTSE supplies a state regression enable signal (also labeled RTSE) to the corresponding one state regression enable node 204. The clockless state return domino logic gate 200 includes a state return enable circuit 207 coupled to the power supply potential VSRC1. The state transition enabling circuit 207 has an input coupled to the node 204 to receive the state regression enable signal RTSE and another endpoint coupled to a second reset node 210. The state regression reset circuit 203 is coupled between the reset nodes 210 and 206.

Each signal node (eg, IN, OUT, PSET, RST, RTSE, etc.) has a first logic state and a second logic state; the first logic state is related to a power supply potential VSRC2, and the second logic state is related to a power source Potential VSRC1. The state regression estimation circuit 201 has an initial preset state, in which case each input signal IN is in the first logic state described above, and is the same as its return state. When the input signal IN is rotated together to form any one of one or more estimated states, the state regression estimating circuit 201 enters an estimated state to generate an estimated event. One or more estimated states of the input signals IN - generating the estimated events - are related to the respective logic design of the state regression estimation circuit 201. For example, if the state regression estimation circuit 201 is designed as a logic or gate, an estimation event occurs when any one or more of the input signals IN transitions from the first state to the second state. In another embodiment, if the state regression estimation circuit 201 is implemented as a logic gate, an estimation event occurs only when each input signal IN transitions from the first logic state to the second logic state. The state return domino circuit 205 typically has two states, including a preset state ("preset" state) and a latch state ("latch" state). The preset state is typically the initial, or preset, value of the state return to the domino circuit 205. In the preset state, the state return domino circuit 205 presets its preset input/output terminal PSET, so the node 202 is in the second logic state. In addition, in the preset state, the state return domino circuit 205 initially sets the reset signal RST to the first logic state and sets the state regression enable signal RTSE to the second logic state. The state regression reset circuit 203 has an isolation state and a reset state determined by the state of the input signals IN applied thereto. When the input signals IN applied to the state regression reset circuit 203 are each in or returning to the first logic state, the state regression reset circuit 203 is in its reset state. Otherwise, the state regression reset circuit 203 is in its isolated state. It must be particularly noted that the state regression reset circuit 203 is in its isolated state whenever the collective state of the input signals IN conforms to any one of the one or more estimated states. When the state regression enable signal RTSE is in the second logic state, the state regression enabling circuit 207 is in its initial preset state; when the state regression enabling signal RSTE is in the first logic state, the state returns to The power circuit 207 is transitioned to a consistent state.

The operation of the clockless state return to the domino logic gate 200 is discussed below. An estimated event occurs when the input signal IN transitions to any one of the one or more estimated states; at this time, the state regression estimation circuit 201 enters its estimated state, and the state regression reset circuit 203 enters its isolation. status. In the above estimated state, the state regression estimating circuit 201 changes the signal of the node 202, and therefore, the preset input/output terminal PSET of the state return domino circuit 205 transitions to the first logic state, causing the state to return to the domino circuit 205 from The preset state is switched to the latched state. The state return domino circuit 205 switches the output signal OUT to the second logic state when switching to its latched state, and switches the state regression enable signal RTSE to the first logic state and no longer affects the reset signal RST. The state regression enabling circuit 207 enters its enabled state, coupling the node 210 to the power supply potential VSRC1 in response to the state return enable signal RTSE of the first logic state. Since the state regression reset circuit 203 is in response to the input signal IN being in its isolated state, even if the state regression enabling circuit 207 is enabled, the reset signal RST is not affected. For the above reasons, the reset signal RST remains in the first logic state.

When the state regression input signal IN supplied to the state regression reset circuit 203 returns to its preset state according to the state regression operation, the state regression reset circuit 203 enters its reset state, coupling the reset nodes 210 and 206 together. The reset signal RST is pulled to the second logic state by circuits 203 and 207. The transition of the reset signal RST to the second logic state causes a reset event to cause the state return domino circuit 205 to return to its preset state. As explained below, the state return domino circuit 205 changes the potential of its preset input and output terminal PSET, causing the node 202 to return to the second logic state. In addition, the state regression domino circuit 205 switches the output signal OUT back to the first logic state, and the switching state regression enable signal RTSE returns to the second logic state. The state regression enabling circuit 207 is effectively turned off corresponding to the state transition enable signal RTSE to the transition state of the second logic state, and the state return domino circuit 205 pulls the reset signal RST back to the first logic state.

In summary, when the input signal IN is transitioned together to any one of the one or more estimated states, the state regression estimation circuit 201 transitions to an estimated state, generating an estimated event, and the state regression reset circuit 203 enters a Isolated state. In response to the estimated event, the state return domino circuit 205 transitions from its preset state to the latched state, switches the output signal OUT, and switches the state regression enable signal RTSE to enable the state regression enable circuit 207. When the respective state regression input signals IN, or at least the state regression input signals IN supplied to the state regression reset circuit 203 return to the first logic state according to the state regression operation, the state regression estimation circuit 201 returns to its preset state. And the state regression reset circuit 203 enters its reset state to pull the reset signal RST to the second logic state to generate a reset event. The reset event should be returned. The state returns to the domino circuit 205 to return to its preset state, causing the state regression enable signal RSTE to return to the second logic state to disable the state regression enable circuit 207. Once the state regression enable circuit 207 is disabled, the state of the state regression reset circuit 203 no longer affects operation until another estimated event occurs. The state return domino circuit 205 then pulls the reset signal RST back to the first logic state, causing the no-clock state to return to the domino logic gate 200 ready for the next estimated event. In this way, the clockless state is returned to the domino logic gate 200 as a self-resetting circuit, and a logic condition estimation is implemented without the clock signal.

A regression logic '0' (RT0) logic gate design and a regression logic '1' (RT1) logic gate design for the clockless state return domino logic gate 200 are discussed further below. The regression logic '0' logic gate design is used to respond to the return logic '0' input signal. The regression logic '1' logic gate design is used to respond to the return logic '1' input signal. In some embodiments, state regression estimation circuit 201 and state regression reset circuit 203 are dual configurations designed to respond to the same state regression input signal IN. In such an embodiment (e.g., the embodiments shown in Figures 10 and 17), the state regression reset circuit 203 is simplified, wherein the state regression input signals IN supplied to the state regression estimation circuit 201 are also supplied. The state regression reset circuit 203 is simultaneously subjected to the same logic operation as the state regression estimation circuit 201 by the state regression reset circuit 203 on the selected subset of the state regression input signals IN. In other embodiments, circuits 201 and 203 are not of a dual configuration design, and only a subset of the input signals IN supplied to circuit 201 are supplied to the state regression reset circuit 203. The input signals IN supplied to the state regression reset circuit 203 are state regression signals, regardless of whether the remaining input signal IN is a state regression (RTS) or a non-state return (non-RTS) signal. In any of the embodiments described above, when the estimated state is true, the reset state is not established. The state regression estimation circuit shows that the estimated state is not true when the estimated state is not met. The reset state is established when the estimation state is not established but the reset condition of the state regression reset circuit is established.

Figure 3 is a block diagram illustrating a clockless regression logic '0' domino logic gate 300, a regression logic '0' implementation for returning to the domino logic gate 200 without the clock state. The output signal OUT and the at least one input signal IN are designed to be a return logic '0' signal with a logic '0' as a predetermined logic state. Based on the prior art in the art, the power supply potential VSRC1 is taken as a supply potential VDD, and the power supply potential VSRC2 is taken as a reference potential VSS. The state regression estimation circuit 201, the state regression domino circuit 205, and the state regression reset circuit 203 are implemented as a regression logic '0' estimation circuit 301, a regression logic '0' domino circuit 305, and a regression logic '0' reset, respectively. Circuit 303 is designed to operate according to a return logic '0'. It must be noted that although any of circuits 301 and 303 may isolate other circuits from a return logic '1' circuit (as viewed from its output), it is still with its input and return logic '0' domino logic gate 300. The overall function view is regarded as the return logic '0' technology. The aforementioned preset input and output terminal PSET is implemented as a precharge input/output terminal PCHG. The pre-charge input and output terminal PCHG is coupled to a pre-charge node 302; the pre-charge node 302 implements the preset node 202. The clockless return logic '0' domino logic gate 300 sets a return logic '0' output signal OUT to an output node 308, and the reset signal RST is generated at the reset node 306. The state transition enable node 204 is implemented as a return logic '0' enable node 304 coupled to the gate of the P channel device P1. The P-channel device P1 implements the aforementioned state regression enabling circuit 207. The source of the P-channel device P1 is coupled to the power supply VDD and its drain is coupled to the return logic '0' reset circuit 303 via a second reset node 310. The return logic '0' reset circuit 303 is further coupled to the reset node 306.

Figure 4 illustrates a regression logic '0' domino circuit 400 as an embodiment of a return logic '0' domino circuit 305. The pre-charging node 302 is coupled to the input of an inverter 401 and coupled to the drains of the P-channel devices P2 and P3. The output coupled to the output node 308 of the inverter 401 provides the return logic '0' output signal OUT (RT0) and supplies it to the gate of the P-channel device P3 and the input of the other inverter 403. The output of inverter 403 is coupled to node 304 to supply a return logic '0' enable signal RT0E to the gate of N-channel device N1. The source of the N-channel device N1 is coupled to the reference potential VSS, and its drain is coupled to the reset node 306 to supply the reset signal RST. The reset signal RST is supplied to the input of an inverter 405. An output of the inverter 405 is supplied with an inverted reset signal RSTB. The inverted reset signal RSTB is supplied to the gate of the P channel device P2, and its source is coupled to the power supply potential VDD. The inverter 401, together with the P channel device P3, constitutes a half-keeper circuit 402 to maintain the level of the precharge input and output terminal PCHG until the return logic '0' estimation circuit 301 pulls it low. The precharge input/output terminal PCHG is initially precharged to a high level, and therefore, the inverter 401 causes the output signal OUT to be at a low level to turn on the P channel device P3. The P channel device P3 pulls the precharge input and output terminal PCHG to the power supply potential VDD to maintain the high level logic state of the precharge input and output terminal PCHG. Since the output signal OUT is initially at a low level, the inverter 403 causes the return logic '0' enable signal RT0E to turn on the N-channel device N1 to pull down the level of the reset signal RST. Inverter 405 thus provides a high level inverted reset signal RSTB that disables P channel device P2.

Referring to Figures 3 and 4, in response to an estimated event generated when one or more of the input signals IN transitions to one of one or more estimated states, the return logic '0' estimation circuit 301 will precharge the input and output. The PCHG level is pulled low, causing the return logic '0' domino circuit 400 to transition to its latched state. Therefore, the inverter 401 pulls up the level of the output signal OUT, so that the P-channel device P3 is not turned on. The inverter 403 pulls down the level of the return logic '0' enable signal RT0E to turn on the P-channel device P1 and disable the N-channel device N1. Turning on the P-channel device P1 causes the node 310 to be coupled to the supply potential VDD. The non-conduction of the N-channel device N1 causes the reset signal RST to no longer be limited to a low level. The estimated state of the input signal IN causes the return logic '0' reset circuit 303 to transition to its isolated state, causing node 306 to isolate node 310. As a result, the reset node 306 is temporarily isolated, so the reset signal RST is not intentionally driven to any state. Since there is no other device function, the reset signal RST is still maintained at a low level. In another embodiment, another N-channel device N2 (indicated by a dashed line) is provided in the circuit of FIG. 4, and an inverter 405 is formed in the other half to maintain the low-level state of the reset signal RST. The N-channel device N2 has a gate receiving inverted reset signal RSTB, a drain coupled to the node 306, and a source coupled to the reference potential VSS. Since the inverted reset signal RSTB is initially at a high level, the N-channel device N2 causes the node 306 to remain at a low level in a state where the N-channel device N1 is not conducting. The N-channel device N2 is used to ensure or ensure that the reset signal RST is still at a low level in the aforementioned state. When the input signal IN is in the estimated state, the return logic '0' reset circuit 303 maintains its isolated state.

When the return signal '0' input signal IN supplied to the return logic '0' reset circuit 303 returns to its preset state, the return logic '0' reset circuit 303 transitions to its reset state, resulting in A reset event in which the P channel device P1 and the return logic '0' reset circuit 303 together pull the reset signal RST to a high level. Note that if the circuit has an N-channel device N2, the return logic '0' reset circuit 303 is designed to oppose the N-channel device N2 to pull up the level of the reset signal RST. The inverter 405 thus pulls down the level of the inverted reset signal RSTB to turn on the P-channel device P2. The turned-on P-channel device P2 pulls the potential of the pre-charge input and output terminal PCHG to its preset state. Please note that when the return signal '0' input signal IN supplied to the return logic '0' reset circuit 303 returns to the preset state, the input signal IN is no longer in an estimated state, so the return logic '0' The estimation circuit 301 no longer pulls down the level of the preset input and output terminal PCHG. In this way, the P channel device P2 pulls the level of the precharge input/output terminal PCHG back to its precharge state. When the level of the precharge input and output terminal PCHG is a high level, the inverter 401 causes the output signal OUT to be at a low level again to turn on the P channel device P3, and maintain the precharge input and output terminal PCHG at a high level. The inverter 403 pulls the return logic '0' enable signal RT0E to a high level to turn on the N-channel device N1 and disable the P-channel device P1. Since the P-channel device P1 is not turned on, the return logic '0' reset circuit is isolated from the supply potential VDD, and the reset signal RST is no longer pulled up. In addition, the turned-on N-channel device N1 pulls the reset signal RST to a low level, and the inverter 405 pulls the inverted reset signal RSTB to a high level to make the P-channel device P2 non-conductive (and In the example in which the N-channel device N2 is supplied, the N-channel device N2 is further turned on. Although the P-channel device P2 is not turned on, the semi-sustain circuit 402 maintains the pre-charge input and output terminal PCHG at a high level. As a result, the regression logic '0' domino circuit 400 is reset back to its preset state, ready for the next estimated event.

Figure 5 illustrates the operation of the clockless regression logic '0' domino logic gate 300 in a timing diagram in which the regression logic '0' domino circuit 400 is used to implement the regression logic '0' domino circuit 305 in accordance with one embodiment. The first state signal EVAL displays an estimated state of the regression logic '0' estimation circuit 301, the establishment of which represents the generation of an estimated event. The first state signal EVAL is a high level when the estimated state is established, and is a low level when the estimated state is not established. The number of estimated states of the input signal IN is determined by the logic function design of the regression logic '0' domino circuit 305. For example, if the regression logic '0' domino circuit 305 is designed to be a logic or function, the condition that any one or more of the input signals IN are at a high level will correspond to an estimated state, respectively. If the regression logic '0' domino circuit 305 is designed to implement a logic and function, the input signal IN has only one estimated state; in this estimated state, each input signal IN is at a high level. The second state signal RESET displays a reset state of the reset logic '0' reset circuit 303; when the reset state is established, the second state signal RESET is a high level; when the reset state is not established, the second state The signal RESET is at a low level. The reset state is determined by the design of the return logic '0' reset circuit 303 and the state of the input signals IN supplied to the return logic '0' reset circuit 303. Each time the input signal IN is any one of one or more of the estimated states, the reset state is not established and the return logic '0' reset circuit 303 is in its isolated state. Whenever the return signal '0' input signal IN supplied to the return logic '0' reset circuit 303 returns to logic '0', the return logic '0' reset circuit 303 is in its reset state. The reset event occurs only when the return logic '0' enable signal RTOE is a low level that turns P channel device P1 on, and the return logic '0' reset circuit 303 is in its reset state. A few applications rely on the design of the evaluation and reset circuits. Regardless of the dual configuration or the non-dual configuration design, when all input signals IN return to logic '0', the reset state is established and the estimation state is not established. In the dual configuration and non-dual configuration design, when the estimation state is established, the reset state is not established. In the non-dual configuration design, only a subset of the input signal IN is supplied to the return logic '0' reset circuit 303, and the reset state may not be true when the estimated state is not established, and may still be after the estimated state transitions to not established. Maintenance is not established.

Figure 5 contains timing diagrams for the signals EVAL, RESET, PCHG, OUT, RT0E, RST, and RSTB. The transition delay of the signal shown is for illustrative purposes only and is not intended to limit the delay time for a particular design. At the initial time T0, the first state signal EVAL is at a low level, indicating that the input signal IN is not in an estimated state. The second state signal RESET is a meaningless signal at timing T0. Note that, according to the regression logic '0' operation, the input signal IN (at least the signals of the regression logic '0') is returned to logic '0' after an estimation interval and before the next estimation interval. However, each input signal may have a different time delay. When the input signal IN is all set to the preset state, the first state signal EVAL is at a low level and the second state signal RESET is at a high level. If one or more of the input signals are converted to a high level but still do not meet the conditions of the estimated state (before the next estimation interval), the second state signal RESET may be toggled one or more times between the two states and simultaneously The status signal EVAL maintains a low level. Therefore, the second state signal RESET is not in a specific state as shown, and further, since the state regression enabling circuit 207 (implemented by the P channel device P1 in the regression logic '0' example) does not function, the prediction is earlier than the estimation. Any bimorphic change in an event is not important. The signals PCHG, OUT, RT0E, RST, and RSTB are initially set to logic '1', '0', '1', '0', and '1', respectively, at time T0.

At the subsequent time point T1, the input signal IN enters an estimated state together, so the first state signal EVAL is pulled high and the second state signal RESET is pulled low. In response to the high level first state signal EVAL, the return logic '0' estimation circuit 301 pulls down the precharge input and output PCHG potential by a continuation time point T2 after a short delay to initiate an estimation event. Since the second state signal RESET is at a low level, the return logic '0' reset circuit 303 is in its isolated state. In response to the precharge input and output signal PCHG pulled to the low level, the inverter 401 pulls up the level of the output signal OUT at the continuation time point T3 after the short delay. As the output signal OUT rises, the inverter 403 pulls down the level of the return logic '0' enable signal RT0E at the subsequent time T4 after the short delay to turn on the P channel device P1 and not turn on the N channel device. N1. Since the return logic '0' reset circuit 303 is non-conducting, the reset signal RST is not affected by any device and is maintained at a low level (or maintained at a low level by the N-channel device N2). The state of the clockless return logic '0' domino logic gate 300 remains unchanged and the first state signal EVAL is at a high level. At the subsequent time point T5, one or more signals in the input signal IN change its state, causing the estimation state to be unsatisfactory, and accordingly, the first state signal EVAL transitions to a low level. If the input signals supplied to the return logic '0' reset circuit 303 are each returned to the logic '0', the second state signal RESET is pulled up as indicated by the broken line 501 at the time point T5. In the case of a non-dual configuration design, there is a delay between the transition of the first state signal EVAL to the low level and the transition of the second state signal RESET to the high level. It must be noted that since the first state signal EVAL is at a low level, the estimation state is not established, and the return logic '0' estimation circuit 301 does not pull down the precharge input/output signal PCHG after the time point T5. The precharge input and output signal PCHG maintains a low level until it is subsequently pulled up to a high level by the P channel device P2. Please note that another semi-sustaining circuit (not shown) can be used to maintain the precharge input and output signal PCHG at a low level in the above conditions.

At the time point T5 or the subsequent time point T6, the input signal IN supplied to the return logic '0' reset circuit 303 is turned to zero to start the reset state of the return logic '0' reset circuit 303, so that The two-state signal RESET is at a high level. The return logic '0' reset potential 303, in conjunction with the P-channel device P1, pulls the potential of the reset signal RST high at a time point T7 after a brief delay to initiate a reset event. The inverter 405 pulls the inverted reset signal RSTB low in response to the short delay T8. The inverted reset signal RSTB transitions to a low level to turn on the P channel device P2, and pulls the precharge input and output signal PCGH back to a preset state at a time point T9 after a short delay. When the precharge input and output signal PCHG is at the high level, the inverter 401 sets the output signal OUT to the low level again at the time point T10 after the short delay. The output signal OUT, which is transitioned to a low level, turns on the P-channel device P3, causing the semi-sustain circuit 402 to maintain the pre-charge input and output signal PCHG at a high level until the next estimation interval will be pulled down. The inverter 403 pulls the return logic '0' enable signal RT0E to a high level at a time point T11 after a short delay. The high-level state of the return logic '0' enable signal RT0E turns on the N-channel device N1 and disables the P-channel device P1. Since the P channel device P1 is not turned on, the return logic '0' reset circuit 303 no longer pulls up the reset signal RST. The conduction of the N-channel device N1 causes the reset signal RST to be pulled back to the low level at a time point T12 after a short delay. The inverter 405 pulls up the inverted reset signal RSTB to a high level at a time point T13 after a short delay, and therefore, the P channel device P2 no longer pulls up the precharge input/output signal PCHG. At this time, the precharge input/output PCHG is maintained at a high level by the half sustain circuit 402. At a later time point T14 at time point T13, the signal returns to its preset state, and the return logic '0' estimation circuit 301 and the P channel device P1 are in their preset states, and the return logic '0' domino circuit 305 returns to its pre-predetermined state. The state is set. Further, assuming that each signal in the input signal IN is at a low level, the return logic '0' reset circuit 303 is in its reset state. In summary, an estimated state of the input signal IN triggers an estimated event, causing the output signal OUT to be at a high level and enabling a subsequent reset event. The reset state of the input signal IN causes the return logic '0' reset circuit 303 to initiate a reset event, and the clockless return logic '0' domino logic gate 300 returns to its initial state, ready for the next estimated interval.

As shown, the second state signal RESET is at a high level until time T11. At time T11, the return logic '0' enable signal RT0E transitions to a high level to determine that the clockless return logic '0' domino logic gate returns to its initial state, and thereafter, the second state signal RESET is Meaningless. Please note that when the reset signal RST is pulled to the high level at the time point T7, even if the reset state is not established and the second state signal RESET is pulled low, the reset signal RST is maintained at the high level because the N-channel device N1 is still It is not conductive and cannot affect the reset signal RST. Therefore, although the reset state should be maintained until the return logic '0' enable signal RT0E transitions to the high level, the input signal can pull the level of the second state signal RESET after the time point T7 and before the time point T11. Without impact, therefore, proper circuit operation can be maintained. Once the return logic '0' enable signal RT0E is at a high level, the P channel device P1 is not conducting, and any meaningless transition of the input signal IN has no effect after the time point T11. A situation other than the above meaningless transition may additionally trigger an estimated state. Please note that the state regression signal RTS may not have a meaningless transition. However, some input signals may be non-state regression signals and may have meaningless transitions. The input signal IN supplied to the regression logic '0' estimation circuit 301 is selected to avoid the occurrence of a potential estimation state.

Figure 6 is a schematic block diagram illustrating a clockless regression logic '0' domino logic gate 600 for implementing a logic or gate, logically ORing the input signals I1...IM of the M regression logic '0' Where M is a positive integer greater than one. In such an embodiment, the input signals I1...IM are all regression logic '0' signals. The clockless return logic '0' domino logic gate 600 includes a return logic '0' domino circuit 305. The regression logic '0' domino circuit 305 is coupled to a regression logic '0' estimation circuit 601 (to implement the regression logic '0' estimation circuit 301), and coupled to a regression logic '0' reset circuit 603 (for A regression logic '0' reset circuit 303 is implemented. The regression logic '0' estimation circuit 601 includes M N-channel devices NA...NM, each of which is coupled to the node 302 with a drain, and each of which is coupled to the reference potential VSS with a source. The N-channel devices NA...NM each have a gate corresponding to the received input signals I1...IM as shown. Similarly, the return logic '0 reset circuit 603 includes M P channel devices PA...PM connected in series between the second reset node 310 and the reset node 306. As shown, the first P-channel device PA and the P-channel device P1 are coupled to the node 310, and the P-channel device PA is coupled to the source of the next P-channel device. In accordance with this concatenation rule, the last P-channel device PM is coupled to node 306 with its drain. The P channel devices PA...PM each receive one of the input signals I1...IM as a gate as shown. Although only two of the plurality of N-channel devices NA...NM, NA and NM, two of the plurality of P-channel devices PA...PM, PA, and two of the plurality of input signals I1...IM are drawn in the illustration. Signals I1 and IM, it must be understood that any number of such devices and signals may be their implementation (e.g., input signals I2 to the gates of N-channel devices NB and P-channel devices PB, etc.).

The clockless regression logic '0' domino logic gate 600 is an embodiment of a dual configuration design in which the return logic '0' reset circuit 603 is a dual configuration design of the regression logic '0 estimation circuit 601. In the dual configuration design, the signals supplied to the return logic '0' estimation circuit 601 and the return logic '0' reset circuit 603 are both input signals I1...IM. The operation of the clockless return logic '0' domino logic gate 600 generally conforms to the timing diagram shown in FIG. In such a state, when the input signals I1...IM are all logical "0" according to the return logic '0', the first state signal EVAL is at a low level and the second state signal RESET is at a high level. When any of the input signals I1...IM is at a high level, the estimated state is established and the reset state is not established; therefore, the first state signal EVAL is in the high level state and the second state signal RESET is in the low level state. Because the circuits 601 and 603 are of a dual configuration design, as the input signal IN switches, the first state signal EVAL and the second state signal RESET are switched and maintained in phase with each other. As any of the input signals IN transitions to a logic '1', the precharge input and output signal PCHG transitions to a low level, and the output signal OUT transitions to a high level after a short delay, and the return logic is '0'. The enable signal RT0E transitions to a low level after another short delay to enable a reset event. When the input signals I1...IM are each returned to logic '0' according to the return logic '0', the return logic '0' reset circuit 603 triggers the reset event, causing the reset signal RST to transition to a high level, The phase reset signal RSTB transitions to a low level, the precharge input and output signal PCHG is pulled high to a high level, and the output signal OUT returns to a low level as previously described.

In some designs, the number of P-channel devices cascaded within the return logic '0' reset circuit 603 is limited to a particular number to ensure proper operation. For example, in one embodiment, the maximum number of P-channel devices allowed to be connected in series between the supply potential VDD and the reset node 306 is 4, and the number of input signals is thus limited to 3 (M is 3). In order to perform a logical OR operation on a large number of input signals, a plurality of clockless regression logic '0' domino logic gates 600 may be combined or cascaded together, and a logical OR operation is performed on any number of input signals by a large number of logic gates. , detailed below.

Figure 7 is a simplified block diagram illustrating a joint logic gate design 700 consisting of three clockless state regression domino logic gates 701, 703 and 705 for implementing a logic operation. The joint logic gate design 700 is shown as a state regression pattern and can be applied to any regression logic '0' or regression logic '1' application. In one embodiment, the six input signals I1...I6 are logically operated to produce a state regression output signal OUT. At least one or all of the input signals I1...I3 are state regression signals, and at least one or all of the input signals I4...I6 are state regression signals. The joint logic gate design 700 includes two three-input no-cycle state return domino logic gates 701 and 703, and another dual input state return domino logic gate 705. The state return domino logic gate 701 receives the input signals I1...I3 and supplies a state regression output signal O1 (RTS) as an input signal for the state return domino logic gate 705. Similarly, state return domino logic gate 703 receives input signals I4...I6 and supplies a state regression output signal O2 (RTS) as another input signal for state return domino logic gate 705. The state return domino logic gate 705 supplies a state return signal OUT (RTS) at its output. In this way, multiple clockless state return domino logic gates can be combined or stacked to cope with a large number of input signals to perform a specific logic operation. In addition, there are other designs that do the same. For example, the first stage structure is implemented with three dual input logic gates, each receiving two of the six input signals, and each generating an output signal to combine as an input signal to a three input logic gate. Alternatively, the techniques can be applied to implement logical operations of other numbers of input signals, and the six input signals described above are for illustrative purposes only.

The logic gates 701, 703, and 705 within the joint logic gate design 700 can each be based on different logic operation requirements - for example, logical AND, OR, NAND, logic, or ( NOR), logical exclusive OR (XOR), etc. or any collection of such logical operations - implemented with appropriate or available input signals. For example, a logical exclusive OR operation of the signal A and the signal B - XOR (A, B) - a state exclusive return input signal A and B and its inverted signals A' and B' (labeled "'" The representative is the inverted signal) needs to be supplied. The logic gates 701, 703, and 705 in the joint logic gate design 700 can perform different operations. Although only three logic gates are shown in the figures, it must be stated that any number of logic gates can be connected in series, in parallel, or otherwise combined based on techniques well known to those skilled in the art. For example, each of the logic gates 701, 703, and 705 can be implemented as a logic or gate in accordance with the clockless return logic '0' domino logic circuit 600. In such an embodiment, the logic gate 701 is designed as a logic or gate, logically ORing the input signals I1...I3 to supply the output signal O1; the logic gate 703 is designed as a logic or gate, and the input signals I4...I6 A logical OR operation is performed to supply the output signal O2; and the logic gate 705 is designed as a logic or gate, and a logical OR operation is performed on the signals O1 and O2 to generate an output signal OUT. As a result, a large number of clockless regression logic '0' domino logic gates can be combined or cascaded to handle a large number of logical operations of the input signal, for example, to implement a logical OR operation.

Figure 8 is a block diagram illustrating a clockless regression logic '0' domino logic gate 800 in which a hybrid logic operation is implemented in accordance with another embodiment of the present invention. The clockless regression logic '0' domino logic gate 800 includes the above-described regression logic '0' domino circuit 305. The regression logic '0' domino circuit 305 is coupled to a regression logic '0' estimation circuit 801 (to implement the regression logic '0' estimation circuit 301) and a regression logic '0' reset circuit 803 (to achieve the Regression logic '0' resets circuit 303). The regression logic '0' estimation circuit 801 includes three N-channel devices NA, NB and NC, each of which is coupled to the node 302 with a drain, and each of which is coupled to a relay node 802 by a source. The regression logic '0' estimation circuit 801 further includes two N-channel devices ND and NE, each of which is coupled to the node 802 with a drain, and each of which is coupled to the reference potential VSS with a source. The N channel devices NA...NE receive five input signals I1...I5 at the gates, respectively. In this embodiment, the regression logic '0' estimation circuit 801 performs a logic operation such that OUT = (I1 | I2 | I3) & (I4 | I5), wherein the symbol "|" represents a logical OR operation, and The symbol "&" represents a logical sum operation. An estimated state occurs when any of the input signals I1...I3 is at a high level and at least one of the input signals I4 and I5 is at a high level. The return logic '0' reset circuit 803 includes two P channel devices PA and PB connected in series between the drain of the P channel device P1 and the reset node 306, and is coupled to the node of the P channel device P1. 310. Specifically, the P-channel device PA is coupled to the drain of the P-channel device P1 by a source, and is coupled to the source of the P-channel device PB by a drain, and the P-channel device PB is coupled to the reset node by a drain. 306. The input signal I4 is supplied to the gate of the P channel device PA, and the input signal I5 is supplied to the gate of the P channel device PB. In this embodiment, the reset state occurs only when the input signals I4 and I5 are both at a low level. Input signals I4 and I5 are regression logic '0' signals; input signals I1...I3 may be regression logic '0' signals but need not necessarily be regression logic '0' signals. Although the state regression signal is the expected setting, in some designs, combining non-state regression signals with state regression signals can be a quite useful design. The non-state regression signal may need to meet certain time conditions relative to the state regression signals. For example, in one embodiment, the non-state regression signal may be set or maintained corresponding to a state regression signal.

The operation of the clockless return logic '0' domino logic gate 800 generally conforms to the timing diagram shown in FIG. In such an embodiment, the estimated state is established when at least one of the input signals I1...I3 is at a high level and at least one of the input signals I4 and I5 is at a high level, the estimated state triggering an estimated event at time T1 . Referring to the foregoing description, in response to the estimated event, the precharge input and output signal PCHG transitions to a low level, and then, the output signal OUT transitions to a high level, and then, the return logic '0' enable signal RT0E transitions to Low level; the transitions are separated by a short delay. The first state signal EVAL maintains a high level in the interval in which the estimated state is established. The reset state is established only when the input signals I4 and I5 are both set to a low level. The second state signal RESET is maintained at a low level because any of the input signals I4 and I5 is at a high level. Therefore, the second state signal RESET is maintained low when the first state signal EVAL is at a high level. Level. When the first state signal EVAL transitions to the low level at the time point T5, if the input signals I4 and I5 are simultaneously at the low level, the second state signal RESET will transition to the high level. At the time point T5, if the input signals I4 and I5 are both turned to the low level, the second state signal RESET can be turned to the high level, but the second state signal RESET is also likely to remain at the low level for a longer time. . For example, if the input signals I1...I3 are all turned to the low level and any of the input signals I4 and I5 are maintained at the high level, the second state signal RESET remains when the first state signal EVAL transitions to the low level. Do not turn to high level. The input signals I4 and I5 are all low level according to the return logic '0' operation (for example, refer to the time point T6 of FIG. 5), then the second state signal RESET transitions to a high level and the return logic '0' resets the circuit. 803 enters its reset state to cause a reset event. As described above, in response to the reset event, the reset signal RST transitions to a high level, the inverted reset signal RSTB transitions to a low level, and the precharge input and output signal PCHG transitions back to a high level. And the output signal OUT is turned back to the low level, and the above transition states are each delayed by a short delay.

The clockless regression logic '0' domino logic gate 800 is a non-dual configuration implementation in which the return logic '0' reset circuit 803 is not a dual configuration design of the return logic '0' estimation circuit 801. In this embodiment, only a subset of the input signals I1 ... I5 - input signals I4 and I5 - are supplied to the return logic '0' reset circuit 803. However, since the estimation state is only established when at least one of the input signals I4 and I5 is at a high level, therefore, when the regression logic '0' estimation circuit 801 is in its estimated state, the return logic '0' reset circuit 803 is necessarily in its Isolation status ensures proper operation. In particular, at the beginning of the estimation event, the return logic '0' reset circuit 803 is in its isolated state, and the return logic '0' domino circuit 305 transitions to its latched state to turn on the P channel device P1. The reset signal RST is not subject to any device determining potential under the estimated conditions. When the input signals I4 and I5 are all converted to a low level according to the return logic '0' operation, the regression logic '0' estimation circuit 801 is out of its estimated state, and the return logic '0' circuit 803 enters its reset state, causing a heavy Set the event. The reset event causes the regression logic '0' domino circuit 305 to transition back to its preset state, causing the P channel device P1 to be non-conducting, and then lowering the level of the reset signal RST to prepare for the next estimated event. .

The logic operation of the clockless regression logic '0' domino logic gate 800 can be used for a joint logic gate structure similar to the joint logic gate design 700. For example, logic gate 701 can be implemented by a three-input logic or gate that receives input signals I1...I3 to supply an output signal O1. Logic gate 703 can be implemented by a dual input logic or gate to receive two input signals I4 and I5 to supply an output signal O2. The logic gate 705 can be implemented by a dual input logic and gate to logically AND the signals O1 and O2. As a result, the joint structure will implement logical operations (II|I2|I3)&(I4|I5). In another architecture, a third P-channel device (not shown) may be provided in series between nodes 310 and 306. The three P-channel devices connected in series are used to receive the input signals I1, I2 and I3, respectively. The resulting operation is equivalent, even though the states of the three input signals (I1, I2, and I3) may cause the return logic '0' domino circuit 305 to be relative to the state of the two input signals (I4 and I5). It takes a little longer for the latch state to transition back to the preset state.

Figure 9 is a schematic block diagram illustrating a clockless regression logic '0' domino logic gate 900 in which a logic AND gate is implemented to logically AND the M regression logic '0' input signals I1...IM. In such logic and embodiments, the input signals I1...IM are each a return logic '0' signal. The clockless regression logic '0' domino logic gate 900 includes the regression logic '0' domino circuit 305, coupled to the regression logic '0' estimation circuit 901 (implementing the regression logic '0' estimation circuit 301) and a regression A logic '0' reset circuit 903 (implementing the regression logic '0' estimation circuit 303). The regression logic '0' estimation circuit 901 includes M N channel devices NA...NM connected in series between the precharge input and output node 302 and the reference potential VSS. As shown, the drain of the N-channel device NA is coupled to node 302, and its source is coupled to the drain of the next N-channel device in the series, and follows this rule until the last stage N-channel device NM, and will N The source of the channel device NM is coupled to the reference potential VSS. As shown, the N-channel devices NA...NM each provide a gate receive input signal I1...IM. Correspondingly, the regression logic '0' reset circuit 903 includes M P channel devices PA...PM connected in parallel between the node 310 and the reset node 306. In particular, the source of the P-channel device PA...PM is coupled to the node 310, and the drain is coupled to the reset node 306.

The clockless regression logic '0' domino logic gate 900 is an embodiment of another dual configuration design. The operation of the clockless regression logic '0' domino logic gate 900 is generally in accordance with the timing diagram disclosed in FIG. In such an embodiment, the estimated state is established when all of the input signals I1...IM are at a high level. At this time, the N-channel devices NA...NM are all turned on, and the pre-charge input/output terminal PCHG is pulled to the reference potential together. VSS. When any of the input signals I1...IM is at a low level, the reset state is established. In this embodiment, the regression logic '0' estimation and reset circuits 901 and 903 are of a dual configuration design with each other. Depending on the application, the logic gate can be designed to receive a variety of input signals. However, as previously discussed with respect to the clockless regression logic '0' domino logic gate 600, to ensure operational accuracy, the number of N-channel devices cascaded within the regression logic '0' estimation circuit 901 is limited to a certain number. .

As with the joint logic gate design 700 discussed previously, the clockless regression logic '0' domino logic gate 900 can employ a cascade technique to implement the logical AND of any number of input signals with multiple logic and gates. Each of the logic gates 701, 703, and 705 can be implemented as a logic and gate with reference to the clockless return logic '0' domino logic gate 900. In one embodiment, the logic gate 701 is designed as a logic gate for logically ANDing the input signals I1...I3 to generate the signal O1; the logic gate 703 is designed as a logic and gate, and the input signals I4...I6 The logic AND operation is performed to generate the signal O2; the logic gate 705 is designed as a logic and gate, and the signals O1 and O2 are logically ANDed to generate the output signal OUT. As such, a plurality of clockless regression logic '0' domino logic gates can be combined or stacked to achieve a particular logical operation - for example, a logical AND operation - for processing a large number of input signals.

Figure 10 is a block diagram illustrating another clockless regression logic '0' domino logic gate 1000 for implementing a logic and gate, and logically ANDing the M regression logic '0' input signals I1...IM, A simplified reset circuit 1003 is included. The clockless regression logic '0' domino logic gate 1000 is substantially similar to the clockless regression logic '0' domino logic gate 900, in which the same components are numbered the same. Comparing the two circuits, the return logic '0' reset circuit 903 is implemented by a return logic '0' reset circuit 1003. The operation of the clockless regression logic '0' domino logic gate 1000 generally also conforms to the timing diagram disclosed in FIG. The return logic '0' reset circuit 1003 includes only a P-channel device PA, the source is coupled to the drain of the P-channel device P1 to the node 310, and the reset node 306 is coupled with the drain. Any of the input signals I1...IM, indicated as signal IX in the figure, is supplied to the gate of the P-channel device PA.

Compared to the clockless regression logic '0' domino logic gate 900, the operations performed by the clockless regression logic '0' domino logic gate 1000 are the same, but are designed to be non-dual configuration. The operation of the clockless return logic '0' domino logic gate 1000 is substantially similar to the clockless return logic '0' domino logic gate 900, except that its reset state is established only when the input signal IX is low. When the input signals I1...IM, including the signal IX, are all transitioned to a high level, the reset state is not established and an estimated event occurs. When the signal IX transitions to a logic '0', the estimated state does not hold and the reset state is established, a reset event is triggered, causing the no-wheel-return logic '0' domino circuit 305 to return to its preset state. . The advantage of the clockless regression logic '0' domino logic gate 1000 is the simplified return logic '0' reset circuit, which is implemented with only one P channel device; however, if signal IX returns to zero in a slower manner than the other input signals At the level, there will be a certain speed loss. The advantage of no clock return logic '0' domino logic gate 900 is that it may increase the reaction speed because the reset event will occur immediately after the event is estimated to be zero when any of the input signals is zero. However, more complex regression logic '0' will be required to reset the circuit design. If one of the input signals IN must be the fastest regression logic '0' signal, it can be selected as signal IX to account for the reaction speed problem of the clockless regression logic '0' domino logic gate 1000.

Referring to the timing diagram of Figure 5, a regression-free logic '0' domino logic gate 300 using regression logic '0' domino circuit 400 is reviewed, wherein multiple or all of the selected input signals are selected (depending on their specific design) When the return logic '0' is operated (or transitioned to) logic '0', the clockless return logic '0' domino logic gate 300 is its initial preset state. When the input signal causes the estimated state to be true, the reset state is not established, and an estimated event occurs. In the state where the estimation state is established, the reset state is maintained as not established. When the return logic '0' input signal supplied to the reset circuit returns to its predetermined logic '0' state, the estimated state transition is not true, and thereafter the reset state is established. The reset ultimately occurs based on the regression logic '0' operation. Regarding the clockless regression logic '0' domino logic gate 600, the reset event occurs when the input signals I1...IM are each transitioned to logic '0'. Regarding the clockless regression logic '0' domino logic gate 800, the reset event occurs when a subset of the input signals I1...I5, i.e., input signals I4 and I5, transitions to logic '0'. Regarding the clockless regression logic '0' domino logic gate 900, the reset event occurs when either of the input signals I1...IM transitions to logic '0'. Regarding the clockless regression logic '0' domino logic gate 1000, the reset event occurs when the selected one of the input signals, i.e., signal IX, transitions to logic '0'.

Figure 11 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1100 implemented in accordance with a regression logic '1' implementation that returns to the domino logic gate 200 without the clock state. The one or more input signals and the resulting output signal are designed as a return logic '1' signal having a predetermined logic state of logic '1'. The power supply potential VSRC1 is designed to be the reference potential VSS, and the power supply potential VSRC2 is designed as the supply potential VDD, as opposed to the design of the clockless return logic '0' domino logic gate 300. The state regression estimation circuit 201, the state regression domino circuit 205, and the state regression reset circuit 203 are respectively a regression logic '1' estimation circuit 1101, a regression logic '1' domino circuit 1105, and a regression logic '1' reset circuit. The 1103 implementation is designed according to a state return '1' operation. Please note that although circuits 1101 and 1103 may each be considered as a return logic '0' circuit due to the operation of their output signals, they are still considered regression logic according to their input signals and the regression logic '1' domino logic gate 1100 as a whole. '1' circuit. The preset input and output terminal PSET is replaced by a pre-clear input and output terminal PCLR coupled to a pre-clear node 1102. The output of the clockless regression logic '1' domino logic gate 1100 sets a return logic '1' output signal OUT at an output node 1108 and a reset signal RST at a reset node 1106. The state regression enable node 204 is implemented by a regression logic '1' enable node 1104 coupled to the gate of the N-channel device N1 to implement the state regression enable circuit 207. The N-channel device N1 is coupled to the reference potential VSS by a source and coupled to the second reset node 1110 by a source, and the return logic '1' reset circuit 1103 is coupled between the reset nodes 1110 and 1106.

Figure 12 is a schematic block diagram illustrating a regression logic '1' domino circuit 1200 as an embodiment of a return logic '1' domino circuit 1105. The regression logic '1' domino circuit 1200 is an inverted design of the return logic '0' domino circuit 300, in which the reference potential VSS is substituted for the supply potential VDD in the circuit 300, and the supply potential VDD is substituted for the reference potential VSS in the circuit 300. The P-channel device replaces the N-channel device in circuit 300, replaces the P-channel device in circuit 300 with an N-channel device, and causes the operational state of each node to be the inverted state of the corresponding node in circuit 300 (logical '0' state Replaced with a logical '1' state and a logical '1' state replaced with a logical '0' state). In addition, the P-channel and N-channel devices and the power supply potential design in each inverter are both inverted designs of the circuit 300; since the same calculations are performed in the figure, they are denoted by the same symbols. The pre-clearing node 1102 is coupled to the input end of the inverter 1201 and coupled to the drains of the N-channel devices N2 and N3. The output of the inverter 1201 is coupled to the output node 1108 to supply the return logic '1' output signal, and is further coupled to the gate of the N-channel device N3 and the input of the inverter 1203. The output of inverter 1203 is coupled to node 1104 to supply a return logic '1' enable signal RT1E for application to the gate of P-channel device P1. The P-channel device P1 is coupled to the supply potential VDD with a source and coupled to the reset node 1106 with a drain to supply a reset signal RST. The reset signal RST is supplied to the input of the inverter 1205, and the output of the inverter 1205 is supplied with an inverted reset signal RSTB. The inverted output signal RSTB is supplied to the gate of the N-channel device N2, and the source of the N-channel device N2 is coupled to the reference potential VSS. The inverter 1201 and the N-channel device N3 constitute a half-maintenance circuit 1202, and maintain the pre-clear input/output terminal PCLR potential at a low level until the return logic '1' estimation circuit 1101 pulls up the potential of the pre-clear input/output terminal PCLR. The P-channel device P2 is shown as a broken line (corresponding to the N-channel device N2 in the dominating logic '0' domino circuit 300), receives the inverted reset signal RSTB with its gate, and is coupled to the node 1106 with the drain, and the source The pole is coupled to the power supply potential VDD. The pre-clear input/output terminal PCLR is initially pre-cleared to a low level, so the inverter 1201 sets the output signal OUT to a high level to turn on the N-channel device N3. The N-channel device N3 thus maintains the pre-clear input and output terminal PCLR at a low level. Since the initial state of the output signal OUT is a high level, the inverter 1205 sets the regression logic '1' to enable the signal RT1E to be low, and the P channel device P1 is turned on, and the turned-on P channel device P1 is pulled high. Signal RST. The inverter 1205 thus pulls the inverted reset signal RSTB low and the initial state of the N-channel device N2 is non-conductive.

Referring to Figures 11 and 12, in response to an estimated event occurring when one or more of the input signals IN transitions to any one or more of the estimated states, the regression logic '1' estimates the circuit 1101 to pull up the pre-clear input and output. The level of the PCLR is such that the return logic '1' domino circuit 1200 is in its latched state. In particular, the inverter 1201 pulls down the output signal OUT to disable the N-channel device N3. The inverter 1203 pulls up the level of the return logic '1' enable signal RT1E to turn on the N-channel device N1 and disable the P-channel device P1. The turned-on N-channel device N1 couples the node 1110 to the reference potential VSS. The non-conducting P-channel device P1 will no longer limit the reset signal RST to a high level. The estimated state of the input signal IN causes the return logic '1' reset circuit 1103 to transition to its isolated state, thereby isolating nodes 1106 and 1110 from each other. As a result, the reset node 1106 is temporarily isolated, and the reset signal RST is no longer limited to a specific state. However, since no other device attempts to change the state of the reset signal RST, the reset signal RST is maintained at a high level. When the input signal IN is in an estimated state, the return logic '1' reset circuit 1103 is maintained in its isolated state.

When the input signals IN supplied to the return logic '1' reset circuit 1103 are each returned to their preset states, the return logic '1' resets the circuit 1103 to its reset state, causing a reset event, wherein The N-channel device N1 and the return logic '1' reset circuit 1103 jointly pull the reset signal RST to a low level. The inverter 1205 will then pull the inverted reset signal RSTB to a high level to turn on the N-channel device N2. The turned-on N-channel device N2 pulls the potential of the pre-clear input and output terminal PCLR to a preset value. Please note that when each input signal IN supplied to the return logic '1' reset circuit 1103 returns to a preset state, the input signals IN will no longer be in an estimated state, therefore, the return logic '1' estimation circuit 1101 The pre-clear input and output terminal PCLR is no longer pulled to the high level. In this way, the N-channel device N2 can again pull the pre-clear input and output terminal PCLR to the pre-clear state. If the pre-clear input and output terminal PCLR is turned to the high level, the inverter 1201 sets the output signal OUT to the high level again, so that the N-channel device N3 is turned on, and the pre-clear input and output terminal PCLR is kept at the low level. The inverter 1103 pulls the return logic '1' enable signal RT1E low to turn on the P channel device P1 and disable the N channel device N1. Since the N-channel device N1 is not turned on, the return logic '1' reset circuit 1103 is isolated from the reference potential VSS, and the level of the reset signal RST is no longer pulled low. In addition, the conduction of the P-channel device P1 pulls the reset signal RST to a high level, and the inverter 1105 pulls the inverted reset signal RSTB to a low level, so that the N-channel device N2 is not turned on. Although the N-channel device N2 is not turned on, the semi-sustain circuit 1202 maintains the pre-clear input and output terminal PCLR potential at a low level. As such, the regression logic '1' domino circuit 1200 is reset back to its preset state to prepare for the next estimated event.

Figure 13 depicts the operation of the clockless regression logic '1' domino logic gate 1100 in a timing diagram in which the regression logic '1' domino circuit 1105 employs an embodiment of a regression logic '1' domino circuit 1200. The timing diagram of Figure 13 is essentially similar to the timing diagram of Figure 5, except for a few signal names and the level adjustment of the circuit signal (inverting it). In particular, compared with Figure 5, Figure 13 replaces the precharge input and output signal PCHG with the pre-clear input and output signal PCLR, and replaces the return logic '0' output signal OUT with the return logic '1' output signal OUT (RT1). (RT0), and replace the return logic '0' enable signal RT0E with the return logic '1' enable signal RT1E. The signals PCLR, OUT(RT1), RT1E, RST, and RSTB in Fig. 13 are the inverse of the signals PCHR, OUT(RT0), RT0E, RST, and RSTB of the fifth figure, respectively. In addition, the transition time basically has the same short delay. Compared with Fig. 5, Fig. 13 also includes the waveforms of the first state signal EVAL and the second state signal RESET, and the reaction is similar. In this embodiment, the first status signal EVAL is used to indicate the estimated state of the regression logic '1' estimation circuit 1101, which is a high level when the estimated state is established, and a low level when the estimated state is not established. The second state signal RESET is used to indicate the reset state of the return logic '1' reset circuit 1103, which is a high level when the reset state is established, and a low level when the reset state is not established. The reset state causes a reset event to occur only when the return logic '1' enable signal RT1E is at a high level after an estimated event.

Figure 13 presents the signals EVAL, RESET, PCRL, OUT(RT1), RT1E, RST, and RSTB in a timing diagram. The transition delays that exist between the individual signals are for illustrative purposes only and do not accurately show the actual conditions. Referring to the initial time point T0, the initial state of the first state signal EVAL is a low level, and the display input signal IN is not in an estimated state. Further, based on the content discussed in FIG. 5, the second state signal RESET is meaningless at the time point T0. At time point T0, signals PCLR, OUT (RT1), RT1E, RST, and RSTB are initially set to logic '0', '1', '0', '1', and '0', respectively.

At the subsequent time point T1, the input signal IN enters the estimation state together, causing the first state signal EVAL to transition to the high level, and the second state signal RESET to the low level. In response to the high level state of the first state signal EVAL, the return logic '1' estimating circuit 1101 pulls up the preamplifier input and output terminal PCLR potential at a time point T2 after a short delay, causing an estimation event. Since the second state signal RESET is at a low level, the return logic '1' reset circuit 1103 is in its isolated state. In response to the action of pre-clearing the signal of the input/output terminal PCLR to the high level, the inverter 1201 pulls the level of the output signal OUT low at the continuation time point T3 after a short delay. In response to the output signal OUT of the low level, the inverter 1203 raises the level of the return logic '1' enable signal RT1E at a subsequent time T4 after a short delay to turn on the N channel device N1 and make the P channel Device P1 is not conducting. Since the return logic '1' reset circuit 1103 does not function, the reset signal RST is not affected by any device and is maintained at a high level (or, in the embodiment with the designed P channel device P2, maintained by the P channel device P2 High standard). The state of the clockless regression logic '1' domino circuit 1200 remains unchanged when the first state signal EVAL is at a high level. At the subsequent time point T5, one or more input signals IN change state, causing the estimated state to be unsuccessful, and the first state signal EVAL is correspondingly transitioned to a low level. If the input signals IN supplied to the return logic '1' reset circuit 1103 each return to logic '1', the second state signal RESET transitions to a high level at time T5 as indicated by the broken line 501. However, with regard to the non-dual configuration design, there is a delay between the transition of the first state signal EVAL to the low level and the transition of the second state signal RESET to the high level. Please note that since the first state signal EVAL is at a low level, the estimation state is not established, so the return logic '1' estimation circuit 1101 does not pull up the potential of the pre-clear input/output terminal PCLR after the time point T5. Pre-clear the input and output terminals PCLR potential will remain at the high level until the N channel device N2 Role, pull its level low.

At the time point T5 or the subsequent time point T6, the input signal IN supplied to the return logic '1' reset circuit 1103 is turned to the high level to start the reset logic '1' reset circuit 1103 reset state, so that The second state signal RESET transitions to a high level. The return logic '1' reset circuit 1103, in conjunction with the N-channel device N1, pulls the level of the reset signal RST low at a time point T7 after a short delay to initiate a reset event. The inverter 1205 responds to the above operation, and raises the level of the inverted reset signal RSTB at a time point T8 after a short delay. The inverted reset signal RSTB, which is transitioned to a high level, turns on the N-channel device N2, and pulls the level of the pre-clear input and output terminal PCLR low at a time point T9 after a short delay. When the level of the pre-clear input and output terminal PCLR is lowered, the inverter 1201 sets the output signal OUT to a high level at a time point T10 after a short delay. The output signal OUT, which is transitioned to a high level, causes the N-channel device N3 to conduct, causing the semi-sustain circuit 1202 to maintain the potential of the pre-clear input and output terminal PCLR at a low level until a later estimation interval pulls its level high. The inverter 1203 pulls the level of the return logic '1' enable signal RT1E low at a time point T11 after a brief delay. The return logic '1' enable signal RT1E of the low level state turns on the P channel device P1 and makes the N channel device N1 non-conductive. Since the N-channel device N1 is not turned on, the return logic '1' reset circuit 1103 no longer pulls down the level of the reset signal RST. The turned-on P-channel device P1 pulls the reset signal RST back to the high level at a time point T12 after a short delay. The inverter 1205 pulls down the level of the inverted reset signal RSTB at a time point T13 after a short delay, so that the N-channel device N2 no longer pulls down the level of the pre-clear input and output terminal PCLR. At this time, the semi-sustaining circuit 1202 is responsible for maintaining the level of the pre-clear input and output terminal PCLR to a low level. At a time point T14 following time point T13, the signal returns to the initial preset state. Therefore, the regression logic '1' estimation circuit 1101 and the N channel device N1 are in their preset states, and the regression logic '1' domino circuit 1105 returns to its preset state. In addition, it is assumed that the input signals IN are each high level, and the regression logic The '1' reset circuit 1103 is in its reset state. In summary, the estimated state of the input signal IN triggers an estimated event, causing the output signal OUT to transition to a low level and enabling a subsequent reset event. The reset state of the input signal IN causes the return logic '1' reset circuit 1103 to initiate a reset event and returns the clockless return logic '1' domino logic gate 1100 to its initial state to accommodate the next estimated interval.

As discussed in Figure 5, the second state signal RESET is at a high level until the time point T11 - the return logic '1' enables the signal RTE1 to transition to a low level - to ensure that there is no clock return logic '1' logic gate Returning to its initial state, after that, the second state signal RESET is meaningless as shown. Please note that when the reset signal RST is pulled to the low level at the time point T7, if the reset state is not established, the second state signal RESET is pulled low to the low level, and the reset signal RST is still maintained at the low level, because P The channel device P1 is still non-conducting and has no effect on the reset signal RST. Therefore, although the reset state should be maintained until the return logic '1' enable signal RT1E transitions to the low level, if the input signal is after the time point T7 and before the time point T11, the second state signal RESET is pulled down. Still does not affect the correct circuit operation. Once the return logic '1' enable signal RT1E is at a low level, the P-channel device P1 is turned on, and any meaningless transition of the input signal IN does not affect the overall circuit state after the time point T11.

Figure 14 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1400 for implementing a logical OR operation to logically OR the M input signals I1...IM. The clockless regression logic '1' domino logic gate 1400 includes a return logic '1' domino circuit 1105. The circuit 1105 is coupled to a regression logic '1' estimation circuit 1401 (for implementing the foregoing regression logic '1' estimation circuit 1101) and a regression logic '1' reset circuit 1403 (for implementing the aforementioned regression logic '1' reset Circuit 1103). The return logic '1' estimation circuit 1401 includes M P channel devices PA...PM, each of which is coupled to the node 1102 with a drain, and each of which is coupled to the supply potential VDD with a source. The P channel devices PA...PM each provide a gate to receive one of the input signals I1...IM. In a similar manner, the regression logic '1' reset circuit 1403 includes M N-channel devices NA...NM connected in series between the node 1110 and the reset node 1106. As shown, the N-channel device NA of the first stage is coupled to the node 1110 on the drain of the N-channel device N1 by a source and coupled to the source of the next-stage N-channel device with a drain; following the rules until the end One-stage N-channel device NM. The drain of the last stage N-channel device NM is coupled to node 1106. The N-channel devices NA...NM each provide a gate to receive one of the input signals I1...IM as shown. Although only two of the N-channel devices (NA, NM), two of the P-channel devices (PA, PM), and only the input signals I1 and IM are shown, in fact, according to the disclosed The rule that the omitted portion may include any number of the devices and associated signals (e.g., input signal I2 supplied to the gates of the N-channel and P-channel devices NB and PB).

The clockless regression logic '1' domino logic gate 1400 is a dual configuration design in which the regression logic '1' reset circuit 1403 is a dual configuration design of the regression logic '1' estimation circuit 1401. Further, in the dual configuration design, the same input signals I1...IM are supplied to the regression logic '1' estimation circuit 1401 and the regression logic '1' reset circuit 1403. The operation of the clockless regression logic '1' domino logic gate 1400 generally conforms to the timing shown in Figure 13. In this embodiment, when the input signals I1...IM are in logic '1' according to the operation of the return logic '1', the first state signal EVAL is at a low level and the second state signal RESET is at a high level. When any of the input signals I1...IM transitions to a low level, the estimated state is established and the reset state is not established, so the first state signal EVAL is at a high level and the second state signal RESET is at a low level. Since the circuits 1401 and 1403 are of a dual configuration, as the switching state of the input signal IN switches, the states of the first state signal EVAL and the second state signal RESET are switched, and are maintained as the opposite phase of the other. In response to the estimated event caused by the low-level transition of any of the input signals IN, the PCLR transition state of the input and output terminals is pre-determined to a high level, and the output signal OUT transitions to a low level after a short delay, and the regression The logic '1' enable signal RT1E transitions to a high level after another short delay to enable a reset event. When the input signals I1...IM are all rotated back to logic '1' according to the return logic '1' operation, the return logic '1' reset circuit 1403 triggers a reset event, causing the reset signal RST to transition to a low level, The phase reset signal RSTB transitions to a high level, and the pre-clear input and output terminal PCLR is pulled back to the low level, and the output signal OUT is pulled back to the high level as described above.

In some designs, the number of N-channel devices cascaded in the return logic '1' reset circuit 1403 may need to be limited to a certain amount to ensure proper operation of the circuit. For example, in one embodiment, the upper limit of the number of N-channel devices connected in series between the reference potential VSS and the reset node 1106 is 4, and therefore, the number of input signals is limited to 3 (i.e., M is 3). Referring to Figure 7, logic gates 701, 703, and 705 can each be implemented by a return logic '1' logic or gate, and each logic gate uses a clockless regression logic '1' domino logic gate 1400 technique. In this embodiment, logic gate 701 is designed as a logic OR gate that logically ORs the return logic '1' input signals I1...I3 to supply a return logic '1' signal O1. Logic gate 703 is designed as a return logic '1' logic or gate, and logically ORs the return logic '1' input signals I4...I6 to supply a return logic '1' signal O2. Logic gate 705 is designed as a return logic '1' logic or gate that logically ORs signals O1 and O2 to supply an output signal OUT that is a return logic '1' signal. As such, a plurality of clockless regression logic '1' domino logic gates can be combined or cascaded to perform a particular logical operation, such as a logical OR operation, on a large number of regression logic '1' input signals.

Figure 15 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1500 in which diverse logic operations are implemented in accordance with another embodiment. The clockless regression logic '1' domino logic gate 1500 includes a regression logic '1' domino circuit 1105. The circuit 1105 is coupled to the regression logic '1' estimation circuit 1501 (to implement the regression logic '1' estimation circuit 1101) and a regression logic '1' reset circuit 1503 (to implement the regression logic '1' reset circuit 1103) . The design of the clockless regression logic '1' domino logic gate 1500 is basically identical to the clockless regression logic '0' domino logic gate 800, except for the inverse design of the return logic '1' operation. Illustrated, compared to the logic gate 800, the logic gate 1500 replaces the reference potential VSS with the power supply potential VDD, replaces the power supply potential VDD with the reference potential VSS, replaces the P channel device with the N channel device, and replaces the N channel device with the P channel device. The input signals I4 and I5 adopt the regression logic '1' operation mode instead of the return logic '0' operation mode, and the signal state is inverted, and the input signals I1...I3 are the return logic '1' or the non-regressive logic '1'. signal. The aforementioned nodes 302, 304, 306, 308, and 310 are replaced with similar nodes 1102, 1104, 1106, 1108, and 1110, respectively, to perform similar operations in a manner similar to the 11th-14th. The operation of the clockless regression logic '1' domino logic gate 1500 generally conforms to the timing diagram disclosed in FIG. The clockless regression logic '1' domino logic gate 1500 implements a logic operation OUT=~((~I1|~I2|~I3)&(~I4|~I5)), where the symbol "~" represents logic Inverted.

Similar to the clockless regression logic '0' domino logic gate 800, the clockless regression logic '1' domino logic gate 1500 is another implementation of the non-dual configuration, wherein the regression logic '1' reset circuit 1503 is not a regression The logic '1' estimates the dual configuration design of circuit 1501. Only a subset of the input signals I1...I5 - input signals I4 and I5 - are supplied to the return logic '1' reset circuit 1503. Since one of the input signals I4 and I5 must be at a low level when the estimated state is established, the return logic '1' reset circuit 1503 is in an isolated state. As long as the regression logic '1' estimation circuit 1501 is in the estimated state, the regression logic '1' reset circuit 1503 must be in its isolated state to ensure normal operation in the manner previously described as a clockless regression logic '0' domino logic gate 800. In addition, the clockless regression logic '1' domino logic gate 1500 can implement a cascade of logic gates using techniques similar to the joint logic gate design 700. In one embodiment, a third N-channel device (not shown) is added to the tandem device between nodes 1110 and 1106 to cause three cascaded N-channel devices to receive input signals I1, I2, and I3. The above-mentioned correction achieves an equivalent logical operation, but the time taken by the regression logic '1' domino circuit 1105 to return to the preset state from the latched state transition state, the state of the three input signals (I1...I3) It takes less time than the two input signals (I4 and I5).

Figure 16 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1600 as a logical AND gate that performs a logical AND operation on the M regression logic '1' input signals I1...IM. The clockless regression logic '1' domino logic gate 1600 includes a regression logic '1' domino circuit 1105. The circuit 1105 is coupled to a regression logic '1' estimation circuit 1601 (for implementing the foregoing regression logic '1' estimation circuit 1101) and a regression logic '1' reset circuit 1603 (for implementing the aforementioned regression logic '1' reset Circuit 1103). The design of the clockless regression logic '1' domino logic gate 1600 is basically similar to the clockless regression logic '0' domino logic gate 900, except that the domino logic gate 1600 is a deformation based on the regression logic '1' operation. . In addition, compared with the domino logic gate 900, the domino logic gate 1600 replaces the reference potential VSS with the power supply potential VDD, and replaces the power supply potential VDD with the reference potential VSS, replaces the P channel device with the N channel device, and replaces the N channel with the P channel device. The device makes the input signal I1...15 return to the logic '1' design instead of the return logic '0' design, so that the output signal OUT is the regression logic '1' design instead of the return logic '0' design, and the signal state is reversed. Phase design. Nodes 302, 304, 306, 308, and 310 are replaced by similar nodes 1102, 1104, 1106, 1108, and 1110, respectively, to implement the equivalent operations discussed in Figures 11...14.

The clockless regression logic '1' domino logic gate 1600 is another implementation of a dual configuration design. The operation of the clockless regression logic '1' domino logic gate 1600 generally conforms to the timing diagram shown in FIG. In this embodiment, the estimation state is established only when the input signals I1...IM are all set to a low level, so that the P channel devices PA...PM are all turned on, and the resultant force pulls the level of the pre-clear input and output terminal PCLR to the power supply potential VDD. The reset state is established when either of the input signals I1...IM is at a high level. In such an embodiment, the regression logic '1' estimate and reset circuits 1601 and 1603 are in a dual configuration design with each other. The circuit is designed to accept the required number of input signals, depending on the requirements. Referring to the previous discussion of the clockless regression logic '1' domino logic gate 1400, similarly, the number of P channel devices cascaded within the regression logic '1' estimation circuit 1601 may need to be limited to a certain number to ensure proper circuit operation. operating. Referring to Figure 7, each of the logic gates 701, 703, and 705 can be implemented using a return logic '1' logic and gate without the clock-return logic '1' domino logic gate 1600 technique. In this way, several clockless regression logic '1' domino logic gates can be combined or cascaded to perform specific logic operations on a large number of input signals, such as logic and operations.

Figure 17 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate 1700, which is a logic and gate, logically ANDing M input signals I1...IM, wherein a simplified reset circuit is employed 1703. The clockless regression logic '1' domino logic gate 1700 is basically similar to the clockless regression logic '1' domino logic gate 1600, in which the same components are numbered the same, and the return logic '1' reset circuit 1603 is changed by The return logic '1' reset circuit 1703 is replaced. Clock-free Regression Logic '1' Domino Logic Gate 1700 generally conforms to the timing diagram shown in Figure 13. The return logic '1' reset circuit 1703 has only one N-channel device NA, the source is coupled to the drain of the N-channel device N1 to the node 1110, and the reset node 1106 is coupled with the drain. Any of the input signals I1...IM, generally designated IX, will be supplied to the gate of the N-channel device NA.

The operation of the clockless regression logic '1' domino logic gate 1700 is equivalent to the clockless regression logic '0' domino logic gate 1600, except that the domino logic gate 1700 is a non-dual configuration design implementation. The operation of the clockless regression logic '1' domino logic gate 1700 is substantially similar to the clockless regression logic '1' domino logic gate 1600, except that the reset state is only true if the input signal IX is at a high level. When the input signals I1...IM, including the input signal IX, are each transitioned to a low level, the reset state is not established and an estimated event occurs. When the input signal IX transitions to logic '0', the estimated state is not true and the reset state is asserted, causing a reset event to cause the clockless regression logic '1' domino circuit 1105 to return to its preset state. The advantage of the clockless regression logic '1' domino logic gate 1700 is that its return logic '1' reset circuit is simplified, only one N channel device is included, however, if the input signal IX transitions back to logic '1' The speed is slower than other input signals, and there is a problem with the speed of response. The advantage of the clockless regression logic '1' domino logic gate 1600 is that there may be a faster response speed because after any event is estimated, once any of the input signals transitions to a logic '1', a reset is initiated. The cost of the event is that the design of the return logic '1' reset circuit is more complicated. The speed problem of the domino logic gate 1700 can be avoided by making the input signal IN, the input signal that can be most rapidly transitioned to logic '1', the input signal IX.

Recall that there is no clock return logic '1' domino logic gate 1100, which uses the regression logic '1' domino circuit 1200 operating according to the timing diagram of Figure 13, no clock return logic '1' domino logic gate 1100 in the input signal according to The return logic '1' operation is (or transitioned to) the initial preset state when it is (or transitioned to) logic '1'. When the input signal causes the estimated state to be true, the reset state is not established and an estimated event is raised. When the estimated state is established, the reset state remains unchanged. After the estimation state is established, the reset state is established if the input signal supplied to the reset circuit is returned to its preset logic '1' state. The reset eventually occurs according to the regression logic '1' operation. Taking the clockless regression logic '1' domino logic gate 1400 as an example, the reset event occurs when each of the input signals I1...IM is turned back to logic '1'. Taking the clockless regression logic '1' domino logic gate 1500 as an example, the reset event occurs when a subset of the input signals I1...I5 - the input signals I4 and I5 - transition to logic '1'. Taking the clockless regression logic '1' domino logic gate 1600 as an example, the reset event occurs when any of the input signals I1...IM transitions back to logic '1'. Taking the clockless regression logic '1' domino logic gate 1700 as an example, the reset event occurs when the selected signal in the input signal is referred to as the input signal IX-transition to logic '1'.

While the above-described several preferred embodiments of the invention have been described in detail, it is possible that other embodiments or variations may be present. For example, the above circuits can be implemented in any other suitable manner including logic devices or circuits. Any number of operations of the described logic circuits can be implemented by software or similar techniques within a firmware or integrated device. The circuitry can include an inverting device to perform normal phase or inverting logic or other techniques that can invert the signal. The circuit operations employed by the disclosed techniques can be digital, binary, or word, as is well known in the art, with respect to digital or binary circuit applications for any number of bits. Those skilled in the art will be able to design or adapt the remaining structures based on the concepts and embodiments disclosed above, and the same as defined in the following claims, without departing from the spirit of the present invention. The role.

101. . . Integrated circuit

103. . . State regression logic

104. . . Non-state regression logic

105. . . No clock state return to the domino circuit

107. . . Logic circuit

200. . . No clock state return to domino logic gate

201. . . State regression estimation circuit

202. . . Preset node

203. . . State regression reset circuit

204. . . State regression enable node

205. . . State regression domino circuit

206. . . Reset node

207. . . State regression enabling circuit

208. . . Output node

210. . . Second reset node

300. . . Clock-free regression logic '0' domino logic gate

301. . . Regression logic '0' estimation circuit

302. . . Precharge node

303. . . Regression logic '0' reset circuit

304. . . Regression logic '0' enable node

305. . . Regression logic '0' domino circuit

306. . . Reset node

308. . . Output node

310. . . Second reset node

400. . . Regression logic '0' domino circuit

401. . . inverter

402. . . Semi-sustained circuit

403, 405. . . inverter

501. . . The response of the second state signal RESET indicating the dual configuration design

600. . . Clock-free regression logic '0' domino logic gate

601. . . Regression logic '0' estimation circuit

603. . . Regression logic '0' reset circuit

700. . . Joint logic gate design

701, 703, 705. . . No clock state return to domino logic gate

800. . . Clock-free regression logic '0' domino logic gate

801. . . Regression logic '0' estimation circuit

802. . . Relay node

803. . . Regression logic '0' reset circuit

900. . . Clock-free regression logic '0' domino logic gate

901. . . Regression logic '0' estimation circuit

903. . . Regression logic '0' reset circuit

1000. . . Clock-free regression logic '0' domino logic gate

1003. . . Regression logic '0' reset circuit

1100. . . Clock-free regression logic '1' domino logic gate

1101. . . Regression logic '1' estimation circuit

1102. . . Pre-clear node

1103. . . Regression logic '1' reset circuit

1104. . . Regression logic '1' enabling node

1105. . . Regression logic '1' domino circuit

1106. . . Reset node

1108. . . Output node

1110. . . Second reset node

1200. . . Regression logic '1' domino circuit

1201. . . inverter

1202. . . Semi-sustained circuit

1203, 1205. . . inverter

1400. . . Clock-free regression logic '1' domino logic gate

1401. . . Regression logic '1' estimation circuit

1403. . . Regression logic '1' reset circuit

1500. . . Clock-free regression logic '1' domino logic gate

1501. . . Regression logic '1' estimation circuit

1502. . . Relay node

1503. . . Regression logic '1' reset circuit

1600. . . Clock-free regression logic '1' domino logic gate

1601. . . Regression logic '1' estimation circuit

1603. . . Regression logic '1' reset circuit

1700. . . Clock-free regression logic '1' domino logic gate

1703. . . Regression logic '1' reset circuit

CLK. . . Clock signal

EVAL. . . First state signal

I1...I6. . . input signal

11(RT0)...IM(RT0), IX(RT0). . . Return logic '0' input signal

I1(RT1)...IM(RT1), IX(RT1). . . Return logic '1' input signal

IN. . . input signal

IN(NON-RTS). . . Non-state regression input signal

IN(RTS). . . State regression input signal

N1, N2, NA...NM. . . N channel device

O1 (RST), O2 (RST). . . output signal

OUT. . . Output

OUT(RT0). . . Return logic '0' output signal

OUT (RT1). . . Return logic '1' output signal

OUT (RTS). . . State regression output signal

P1, P2, P3, PA...PM. . . P channel device

PCHG. . . Precharge input/output/signal

PCLR. . . Pre-clear input/output/signal

PSET. . . Preset input and output

RESET. . . Second state signal

RST. . . Reset signal

RSTB. . . Inverted reset signal

RT0E. . . Regression logic '0' enable signal

RT1E. . . Regression logic '1' enable signal

RTSE. . . State regression enable signal

T0...T14. . . Time point

VDD. . . Supply potential

VSRC1, VSRC2. . . Power supply potential

VSS. . . Reference potential

The following description will be helpful in understanding the advantages, features, and improvements of the present invention. 1 is a simplified block diagram depicting a wafer or an integrated circuit including a clockless state return domino circuit implemented in accordance with an embodiment of the present invention; and FIG. 2 is a block diagram illustrating A clockless state return domino logic gate realized by an embodiment of the invention can be used to implement one or more clockless state regression domino logic gates in the domino circuit state without the clock state in FIG. 1; FIG. For a schematic block diagram, a clockless regression logic '0' domino logic gate implemented by a regression logic '0' implementation according to Fig. 2 without clocking state returning to the domino logic gate; Fig. 4 is a regression logic Schematic diagram of the '0' domino circuit, illustrating an embodiment of the return logic '0' domino circuit of Fig. 3; Fig. 5 is a timing diagram illustrating the operation of the novo clock return logic '0' domino logic gate of Fig. 3, One embodiment of the regression logic '0' domino circuit of FIG. 4 is used; and FIG. 6 is a schematic block diagram illustrating a clockless return logic '0' domino logic gate for implementing a logic or gate. M input signals I1...IM are logically ORed; Figure 7 is a simplified block diagram illustrating a cascade of logic gate designs in which three clockless state-returned domino logic gates are coupled together to implement a Logic operation; FIG. 8 is a schematic block diagram illustrating a clockless state return domino logic gate implemented in accordance with another embodiment of the present invention for implementing diverse logic operations; FIG. 9 is a schematic block diagram, Graphical a clockless regression logic '0' domino logic gate, used to implement a logical AND operation, logically AND operations on M regression logic '0' input signals I1...IM;

Figure 10 is a schematic block diagram illustrating another clockless return logic '0' domino logic gate for implementing a logic and gate, and logically ANDing the M regression state '0' input signals I1...IM, Which includes a simplified reset circuit;

Figure 11 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate, which is implemented according to a regression logic '1' implementation of the clockless state returning domino logic gate of Fig. 2;

Figure 12 is a schematic diagram of a regression logic '1' domino circuit, illustrating an embodiment of the return logic '1' domino circuit of Figure 11;

Figure 13 is a timing diagram for explaining the operation of the Fig. 11 without the clock return logic '1' domino logic gate, wherein an embodiment of the logic logic '1' domino circuit of Fig. 12 is employed;

Figure 14 is a schematic block diagram illustrating a clockless regression logic '1' domino logic gate in which a logic OR gate is implemented to logically OR the M regression logic '1' input signals I1...IM;

Figure 15 is a schematic block diagram of a clockless regression logic '1' domino logic gate 1500, which is constructed in accordance with another embodiment for performing a variety of logic operations;

Figure 16 is a schematic block diagram of a clockless return logic '1' domino logic gate for implementing a logic AND gate to logically AND the M regression logic '1' input signals I1...IM;

Figure 17 is a schematic block diagram of another clockless logic logic '1' domino logic gate for implementing a logic and gate, and performing logical AND operations on M regression logic '1' input signals I1...IM, wherein Includes a simplified reset circuit.

200. . . No clock state return to domino logic gate

201. . . State regression estimation circuit

202. . . Preset node

203. . . State regression reset circuit

204. . . State regression enable node

205. . . State regression domino circuit

206. . . Reset node

207. . . State regression enabling circuit

208. . . Output node

210. . . Second reset node

IN. . . input signal

OUT. . . Output

OUT (RTS). . . State regression output signal

PSET. . . Preset input and output

RST. . . Reset signal

RTSE. . . State regression enable signal

VSRC1, VSRC2. . . Power supply potential

Claims (60)

A clockless state regression domino logic gate includes: a plurality of nodes, each designed to switch between a first state and a second state, including a plurality of input nodes, a preset node, an output node, and a uniform node And a first and a second reset node, wherein the plurality of input nodes each comprise a state regression node, and after being set to the first state, returning to the second state according to a state regression operation; a domino circuit having a preset state and a latched state, when the domino circuit is in the preset state, the domino circuit sets the preset node and the enabling node to the first state, and sets the output node and the first weight Setting the node to the second state, when the preset node is transitioned to the second state, the domino circuit switches to the latched state, causing the output node to transition to the first state and transitioning the enablement Node to the second state, when the first reset node is transitioned to the first state, the domino circuit is reset back to the preset state; an estimation circuit is When the node is in at least one of the estimated states, the preset node is switched to the second state, and the input node does not interfere with the level of the preset node when the input node is not in the estimated state; When the enabling node is in the second state, the second reset node is transitioned to the first state, otherwise, the second reset node is not interfered with; and a reset potential is not applied to the input signal. When the at least one of the at least one estimated state is coupled to the first reset node and the second reset node, and resetting the first reset when the input signal is any one of the at least one estimated state The node isolates the second reset node. The clockless state is returned to the domino logic gate as described in claim 1 of the patent application, wherein the estimation circuit and the reset circuit are designed in a dual configuration. The clockless state is returned to the domino logic gate as described in claim 1 of the patent application, wherein the estimating circuit performs a logical OR operation on the plurality of input nodes. The clockless state is returned to the domino logic gate as described in claim 1 of the patent application, wherein the estimating circuit performs a logical AND operation on the plurality of input nodes. The clockless state return domino logic gate as described in claim 1 wherein: the plurality of input nodes comprise a plurality of regression logic '0' nodes, wherein each of the plurality of input nodes is designed to be in a logic ' a 0' state and a logic '1' state switch, and each of the plurality of input signals transitions back to logic '0' after being set to logic '1'; the preset node includes a precharge node, and the domino circuit includes a return logic '0' domino circuit; when the domino circuit is in the preset state, the domino circuit sets the precharge node and the enable node to logic '1', and sets the output node and the first reset Node to logic '0', when the domino circuit is in the latched state, the domino circuit transitions the output node to logic '1' and the enabled node is logic '0' when the first reset When the node transitions to logic '1', the domino circuit is reset back to the preset state; when the plurality of input nodes are any one of the at least one estimated state, the estimating circuit shifts the pre-charge node to Series '0', when said When the plurality of input nodes are not any of the at least one estimated state, the estimating circuit does not affect the preset node; and when the enabling node is logic '0', the enabling circuit shifts the second weight Set the node to logic '1', otherwise the enable circuit does not affect the second reset node. The clockless state is back to the domino logic gate as described in claim 1, wherein: the plurality of input nodes include a plurality of regression logic '1' nodes, each having a logical '1' state and a logical '0' a state, wherein each of the plurality of input nodes respectively returns to a logic '1' after being set to logic '0'; the preset node includes a pre-clear node, and the domino circuit includes a regression logic '1' domino circuit; When the domino circuit is in the preset state, the domino circuit sets the pre-clear node and the enable node to logic '0', and sets the output node and the first reset node to logic '1', when the dominoes When the circuit is in the latched state, the domino circuit shifts the output node to logic '0' and transitions the enable node to logic '1', when the first reset node transitions to logic '0', The domino circuit is reset back to the preset state; when the plurality of input nodes form any of the at least one estimated state, the estimating circuit shifts the pre-clear node to a logic '1', and when the plurality of inputs When the input node does not form any of the at least one estimated state, the estimating circuit does not affect the preset node; and when the enabling node is logic '1', the enabling circuit shifts the second reset node To logic '0', otherwise the enable circuit does not affect the second reset node. The clockless state returning domino logic gate as described in claim 1 wherein: the plurality of input nodes comprise a plurality of regression logic '0' input nodes; the preset node comprises a precharge node; the estimation circuit The circuit includes a plurality of N-channel devices, each of which is coupled to the pre-charging node by a drain, coupled to a reference potential by a source, and coupled to the corresponding one of the plurality of input nodes by a gate; the enabling circuit The first P-channel device includes a source coupled to the supply potential, a drain coupled to the second reset node, and a gate coupled to the enable node; and the reset circuit includes a plurality of second The P-channel device is connected in series between the first and the second reset nodes, and each of the gates is coupled to the corresponding one of the plurality of input nodes. The clockless state returning domino logic gate as described in claim 1 wherein: the plurality of input nodes comprise a plurality of regression logic '0' input nodes; the preset node includes a precharge node; the estimation circuit The device includes a plurality of N-channel devices connected in series between the pre-charging node and the reference potential, each of which is coupled to the corresponding one of the plurality of input nodes by a gate; the enabling circuit includes a first P channel The device is coupled to the power supply potential by a source, is coupled to the second reset node by a drain, and is coupled to the enable node by a gate; and the reset circuit includes a plurality of second P channel devices, each of which The source is coupled to the second reset node, coupled to the first reset node by a drain, and coupled to the corresponding one of the plurality of input nodes by a gate. The clockless state returning domino logic gate as described in claim 1 wherein: the plurality of input nodes comprise a plurality of regression logic '0' input nodes; the preset node includes a precharge node; the estimation circuit a plurality of N-channel devices are connected in series between the pre-charging node and the reference potential, each of which is coupled to the corresponding one of the plurality of input nodes by a gate; the enabling node includes a first P channel The device is coupled to the power supply potential by a source, coupled to the second reset node by a drain, and coupled to the enable node by a gate; and the reset circuit includes a second P channel device to the source The first reset node is coupled to the first reset node, and the gate is coupled to one of the plurality of input nodes. The clockless state return domino logic gate as described in claim 1 wherein: the plurality of input nodes comprise a plurality of regression logic '1' input nodes; the preset node includes a pre-clear node; the estimation circuit The circuit includes a plurality of P-channel devices, each of which is coupled to the pre-clearing node by a drain, coupled to the power supply potential by a source, and coupled to the corresponding one of the plurality of input nodes by a gate; the enabling circuit The first N-channel device includes a source coupled to the reference potential, a drain coupled to the second reset node, and a gate coupled to the enable node; and the reset circuit includes a plurality of second The N-channel device is connected in series between the first and the second reset nodes, and each of the gates is coupled to the corresponding one of the plurality of input nodes. The clockless state returning domino logic gate as described in claim 1 wherein: the plurality of input nodes comprise a plurality of regression logic '1' input nodes; the preset node comprises a pre-clear node; the estimating circuit a plurality of P-channel devices are connected in series between the pre-clear node and the power supply potential, and each of the plurality of input nodes is coupled to the input node by a gate; the enabling circuit includes a first N channel a device, the source is coupled to the reference potential, the drain is coupled to the second reset node, and the gate is coupled to the enable node; and the reset circuit includes a plurality of second N-channel devices, each of which The source is coupled to the second reset node, and the first reset node is coupled to the drain, and the gate is coupled to the corresponding one of the plurality of input nodes. The clockless state return domino logic gate as described in claim 1 wherein: the plurality of input nodes comprise a plurality of regression logic '1' input nodes; the preset node comprises a pre-clear node; The estimating circuit includes a plurality of P-channel devices connected in series between the pre-clearing node and the power supply potential, each of which is coupled to the corresponding one of the plurality of input nodes by a gate; the enabling circuit includes a first An N-channel device, the source is coupled to the reference potential, the drain is coupled to the second reset node, and the gate is coupled to the enable node; and the reset potential includes a second N-channel device. The second reset node is coupled to the source, the first reset node is coupled to the drain, and one of the input nodes of the plurality of input nodes is coupled by the gate. An integrated circuit includes: a first logic for supplying a plurality of state regression signals, each of the state regression signals being designed to be switched between a first state and a second state, wherein the plurality of state regression signals are each set to be the above After the first state, the first logic is set to the second state according to the state regression operation; a clockless state is returned to the domino logic gate, and the plurality of state regression signals are received, and the clockless state return domino logic gate includes a preset node, a consistent energy node, an output node, and a first and a second reset node, each designed to switch between the first and second states; a domino circuit having a preset state and a latch a lock state, wherein when the domino circuit is in the preset state, the domino circuit sets the preset node and the enable node to the first state, and sets the output node and the first reset node to the foregoing a second state, when the preset node is transitioned to the second state, the domino circuit switches to the latched state, causing the output node to transition to the upper state a first state, and transitioning the enabling node to the second state, when the first reset node transitions to the first state, the domino circuit is reset back to the preset state; an estimating circuit is as described above And when the plurality of state regression signals are at least one of the estimated states, the preset node is transitioned to the second state, and when the plurality of state regression signals are not any of the at least one estimated state, Activating the preset node; the consistent energy circuit, when the enabling node is in the second state, shifting the second reset node to the first state; otherwise, does not affect the second reset node; And the circuit is coupled to the first reset node to the second reset node when the plurality of state regression signals are not the at least one estimated state, and the plurality of state regression signals are at least When any of the states is estimated, the first reset node is isolated from the second reset node. The integrated circuit of claim 13, wherein the first logic supplies a plurality of regression logic '0' signals, the first state is a logic '1' and the second state is a logic '0', and The clockless state return domino logic gate includes a clockless return logic '0' domino logic gate. The integrated circuit of claim 13, wherein the first logic supplies a plurality of regression state '1' signals, the first state is a logic '0' and the second state is a logic '1', and The clockless state return domino logic gate includes a clockless return logic '1' domino logic gate. The integrated circuit of claim 13, wherein the clockless state return domino logic gate comprises a plurality of clockless state return domino logic gates of the tandem design. A method for estimating a logic operation, comprising: receiving a plurality of state regression input signals, each of the state regression input signals is designed to return to a second state according to a state regression operation after being set to a first state; the supply has a preset state And a domino circuit in a latched state, when the domino circuit is in the preset state, the domino circuit sets a preset node and the consistent energy node to be in the first state, and set an output node and a reset node as In the second state, when the preset node is switched to the second state, the domino circuit switches to the latch state to switch the output node to the first state and transitions the enable node to the second state. a state, when the reset node transitions to the first state, the domino circuit is reset back to the preset state; and the plurality of state regression input signals are estimated, wherein the plurality of state regression input signals are at least one estimated state Switching the preset node to the second state to switch the domino circuit to the latched state; and the enabling message When a plurality of states and said input signal is a return to the second state is not any one of the aforementioned plurality of estimated state, the transient state to the first node reset, to reset the circuit into the preset state dominoes. The method of claim 17, wherein the switching the domino circuit to the latch state to switch the enable node to the second state when the preset node transitions to the second state The steps include: enabling a reset condition of the domino circuit. The method of claim 17, wherein the step of estimating the plurality of state regression input signals comprises performing a logical OR operation to transition at least one of the plurality of state regression input signals to the first state Transmitting the preset node to the second state, and wherein the resetting the domino circuit comprises: when the enabling node is in the second state and the plurality of state regression input signals are all in the second state The state resets the node to the first state. The method of claim 17, wherein the step of estimating the plurality of state regression input signals comprises performing a logical AND operation to shift the input signals to the first state when the plurality of state regression input signals are all converted. And the step of resetting the domino circuit, wherein the step of resetting the domino circuit comprises when the enabling node is in the second state and at least one of the plurality of state regression input signals returns to the second state The state transitions the node to the first state. A clockless state returning domino logic gate includes: a plurality of nodes, each switching to a first state and a second state, wherein the plurality of input nodes, a preset node, an output node, a consistent node, and a a first and a second reset node, wherein at least one of the plurality of input nodes includes a state regression node, and after setting to the first state, transitioning back to the second state according to a state return operation; a domino circuit having a a preset state and a latch state, when the domino circuit is in the preset state, the domino circuit sets the preset node and the enable node to be in the first state, and set the output node and the first reset node In the second state, when the preset node transitions to the second state, the domino circuit switches to the latched state, and the output node is in the first state, and the enabled node is in the transition state. The second shape above a state, when the first reset node transitions back to the first state, the domino circuit is reset back to the preset state; an estimating circuit, when the plurality of input nodes are any one of at least one estimated state, Transitioning the preset node to the second state, and when the plurality of input nodes are not any of the at least one estimated state, the preset node is not affected; the consistent energy circuit is configured by the enabling node In the second state, the second reset node is in the first state, and the second reset node is not affected when the enable node is not in the second state; and a reset circuit is in the plurality of The first node is coupled to the second reset node when the input node is not at least one of the at least one estimated state, and is configured to be when the plurality of input nodes are any of the at least one estimated state The reset node isolates the second reset node. The clockless state is returned to the domino logic gate as described in claim 21, wherein the estimation circuit and the reset circuit are designed in a non-dual configuration. The clockless state is returned to the domino logic gate as described in claim 21, wherein the reset circuit is coupled to a subset of the plurality of input nodes, the subset comprising at least one but not all of the above inputs a node, the input nodes belonging to the subset each include a state regression node, each of the at least one estimated state occurring only when at least one of the subset of the plurality of input nodes transitions from the second state, and the domino The circuit resets back to the preset state only when the subset of the plurality of input nodes is the second state. Return to bone without the clock state as described in claim 21 a logic gate, wherein: the plurality of input nodes include at least one regression logic '0' node, each of the at least one regression logic '0' nodes being designed to switch between a logic '0' state and a logic '1' state, and The at least one regression logic '0' node is respectively turned back to logic '0' after being set to logic '1'; the preset node includes a pre-charge node, and the domino circuit includes a regression logic '0' domino circuit; When the domino circuit is in the preset state, the domino circuit sets the precharge node and the enable node to logic '1', and sets the output node and the first reset node to logic '0' when When the domino circuit is in the latched state, the domino circuit shifts the output node to logic '1' and the enabled node is logic '0', and when the first reset node transitions back to logic '1 When the domino circuit is reset back to the preset state; when the plurality of input nodes are any of the at least one estimated state, the estimating circuit shifts the precharge node to a logic '0', when the complex When the input node is not any of the at least one estimated state, the estimating circuit does not affect the preset node; and when the enabling node is logic '0', the enabling circuit shifts the second reset The node to logic '1', and when the enable node is not logic '0', the enable circuit does not affect the second reset node. The clockless state is returned to the domino logic gate as described in claim 24, wherein the reset circuit is coupled to a subset of the plurality of input nodes, the subset comprising at least one but not all of the input nodes. The input nodes in the subset of the plurality of input nodes each include a regression logic '0' node, and each of the at least one estimated state occurs only When at least one input node in the subset of the plurality of input nodes is switched from logic '0' to logic '1', and the domino circuit is only for all input nodes in the subset of the plurality of input nodes Reset to the preset state when logic '0'. The clockless state return domino logic gate as described in claim 21, wherein: the plurality of input nodes include at least one regression logic '1' node, and the at least one regression logic '1' node is each designed to be logic Switching between a '1' state and a logical '0' state, each of the at least one regression logic '1' node is returned to logic '1' after being set to logic '0'; the preset node includes a pre-clear node, and the domino The circuit includes a regression logic '1' domino circuit; when the domino circuit is in the preset state, the domino circuit sets the pre-clear node and the enable node to logic '0', and sets the output node and the first The reset node is logic '1'. When the domino circuit is in the latched state, the domino circuit transitions the output node to logic '0', and the enabled node is logically '1', when the first When the reset node transitions back to logic '0', the domino circuit is reset back to the preset state; when the plurality of input nodes are any of the at least one estimated state, the estimating circuit shifts the pre-predetermined state The node is logic '1', and when the plurality of input nodes are not any of the at least one estimated state, the estimating circuit does not affect the preset node; and when the enabling node is logic '1', The enabling circuit transitions the second reset node to a logic '0', and when the enabling node is not logic '1', the enabling circuit does not affect the second reset node. The clockless state returning domino logic gate as described in claim 26, wherein the reset circuit is coupled to a subset of the plurality of input nodes, the subset comprising at least one but not all of the input nodes, The input nodes in the subset of the plurality of input nodes each include a regression logic '1' node, and the at least one estimated state each occurs only in the subset of the plurality of input nodes and has at least one input node from the logic ' When the 1' transition state is logic '0', the domino circuit resets to the preset state only when all of the input nodes of the plurality of input nodes are logically '0'. The clockless state returning domino logic gate as described in claim 21, wherein: at least one of the plurality of input nodes includes a regression logic '0' input node; the preset node includes a pre-clear node; The domino circuit includes: a first inverter coupled to the precharge node and having an output coupled to the output node; a first P channel device having a gate coupled to the output node, Having a source coupled to a supply potential and having a drain coupled to the precharge node; a second inverter having an input coupled to the output node and having an output coupled to the enable node a first N-channel device having a source coupled to a reference potential, a gate coupled to the enable node, and a drain coupled to the reset node; a third inverter having an input The reset node is coupled to the reset node and has an output end; and a second P-channel device having a source coupled to the supply potential, having a gate coupled to the output of the third inverter, and having A flip-flop is coupled to the pre-charge node. The clockless state return domino logic gate as described in claim 28, wherein the estimation circuit includes a plurality of second N channel devices, and the reset circuit includes at least one third P channel device. The clockless state return domino logic gate as described in claim 21, wherein: at least one of the plurality of input nodes includes a regression logic '1' input node; the preset node includes a pre-clear node; The domino circuit includes: a fifth inverter having an input coupled to the pre-clear node and having an output coupled to the output node; a first N-channel device having a gate coupled to the output node Having a source coupled to a reference potential and having a drain coupled to the pre-clear node; a second inverter having an input coupled to the output node and having an output coupled to the enable a first P-channel device having a source coupled to a supply potential, a gate coupled to the enable node, and a drain coupled to the reset node; a third inverter having an input The terminal is coupled to the reset node and has an output terminal; and a second N-channel device having a source coupled to the reference potential, having a gate coupled to the output of the third inverter, and There is a pole coupled to the pre-clear node. The clockless state return domino logic gate as described in claim 30, wherein the estimation circuit includes a plurality of second P channel devices, and the reset circuit includes at least one third N channel device. An integrated circuit includes: a first logic, supplying at least one state regression signal, wherein the at least one state regression signal is designed to be switched in a first state and a second state, and the first logic operates according to a state regression The at least one state regression signal is set to the first state and then set back to the second state; and a clockless state is returned to the domino logic gate, and the plurality of input nodes receive the at least one state regression signal, the no clock The state return domino logic gate includes: a preset node, a uniform energy node, an output node, and a first and second reset node, each designed to switch between the first state and the second state; a domino circuit having a pre- And a latching state, wherein when the domino circuit is in the preset state, the domino circuit sets the preset node and the enabling node to be in the first state, and set the output node and the first weight Setting the node to the second state, when the preset node transitions to the second state, the domino circuit switches to the latched state To transfer to the state of the output node of said first shape And transitioning the enabling node to the second state, when the first reset node returns to the first state, the domino circuit is reset back to the preset state; an estimating circuit is in the plurality of When the input node is in any one of the estimated states, the preset node is transitioned to the second state, and the preset is not affected when the plurality of input nodes are not the at least one of the estimated states a node; a consistent energy circuit, when the enabled node is in the second state, transitioning the second reset node to the first state, and not affecting the second weight when the enabled node is not in the second state And a resetting circuit, coupled to the first reset node to the second reset node, and at the plurality of inputs, when the plurality of input nodes are not any of the at least one estimated state When the node is any of the at least one estimated state, the first reset node is isolated from the second reset node. The integrated circuit of claim 32, wherein the estimating circuit and the reset circuit are of a non-dual configuration. The integrated circuit of claim 32, wherein the reset circuit is coupled to a subset of the plurality of input nodes, the subset comprising at least one but not all of the input nodes, the plurality of input nodes Each of the input nodes in the subset is a state regression node, and the plurality of estimated states each occur only when at least one input node in the subset of the plurality of input nodes transitions from the second state, and the dominoes The circuit resets back to the preset state when all of the input nodes in the subset of the plurality of input nodes are in the second state. The integrated circuit of claim 34, wherein the first logic supplies at least one regression logic '0' signal, the first state is a logic '1' and the second state is a logic '0', The no-vehicle state return domino logic gate includes a clockless regression logic '0' domino logic gate, and the input nodes in the subset of the plurality of input nodes each include a regression logic '0' node. The integrated circuit of claim 34, wherein the first logic supplies at least one regression logic '1' signal, wherein the first state is a logic '0' and the second state is a logic '1' The clockless state return domino logic gate includes a clockless regression logic '1' domino logic gate, and the input nodes in the subset of the plurality of input nodes each include a regression logic '1' node. A method for estimating a logic operation, comprising: receiving a plurality of input signals, each designed to switch between a first state and a second state, wherein the plurality of input signals includes at least one state regression signal, and the at least one state regression signal After being set to the first state, resetting back to the second state according to the state return operation; supplying a domino circuit having a preset state and a latch state, when the domino circuit is in the preset state, the domino The circuit sets a preset node and the consistent energy node to a first state, and sets an output node and a reset node to a second state, and when the preset node transitions to the second state, the domino circuit switches Up to the latched state, to switch the output node to the first state and the transition state to the second state, and when the reset node is in the first state, the domino circuit is reset back The preset state; estimating the plurality of input signals, wherein when the plurality of input signals are at least one of the estimated states, the preset section is transitioned Up to the second state, the domino circuit is switched to the latched state; and when the enabling node is in the second state and the plurality of input signals are not any of the at least one estimated state, The node is reset to the first state to reset the domino circuit to the preset state. The method of claim 37, wherein the resetting step comprises the enabling node being in the second state and each of the at least one state regression signals transitioning back to the second state after switching to the first state In the state, the state is reset to the first state. The method of claim 37, wherein the estimating step comprises: transitioning the preset node to the second state when at least one transition state in the at least one state regression signal is to the first state; The resetting step includes transitioning the reset node to the first state when the enabling node is in the second state and the at least one state regression signal is all returned to the second state. The method of claim 37, wherein the estimating step comprises: shifting the preset node to the second state when the at least one state regression signal is fully converted back to the first state; and the resetting The step includes transitioning the reset node to the first state when the enabling node is in the second state and the at least one state regression signal is fully transitioned back to the second state. A clockless state is returned to the domino logic gate, and responds to a plurality of input logic signals, wherein the input logic signals are each switched to a first and a second logic state, and the clockless state return domino logic gate comprises: a domino circuit, The method includes: a plurality of nodes, switching to the first and second logic states, wherein the node includes a preset node, an output node, a consistent energy node, and a first reset node; and a first inverter having an input The end is coupled to the preset node, and has an output coupled to the output node; a first device in a first conduction form having a control end coupled to the output node, having a first current terminal coupled thereto a first power supply potential node associated with the first logic state, and having a second current terminal coupled to the preset node; a second inverter having an input coupled to the output node and having an output coupling Connected to the enabling node; a first device in the form of a second conduction having a first current terminal coupled to a second power potential node associated with the second logic state, having a control terminal Connected to the enabling node, and having a second current terminal coupled to the first reset node; a third inverter having an input coupled to the first reset node and having an output; a second device of the first conduction type, having a first current terminal coupled to the first power potential node, having a control terminal coupled to the output terminal of the third inverter, and having a second current terminal coupling Connected to the preset node; and an input circuit coupled to the preset node, the reset node, and the enable node, configured to respond to the plurality of input logic signals, wherein When the plurality of input logic signals are any one of the at least one estimated state, the input circuit transitions the preset node to the second logic state, and when the plurality of input logic signals transition away from the at least one estimated state In one case, the input circuit temporarily transitions the first reset node to the first logic state. The clockless state returning domino logic gate as described in claim 41, wherein the input circuit comprises: an estimating circuit designed to respond to the plurality of input logic signals, wherein when the plurality of input logic signals are In at least one of the estimated states, the estimating circuit transitions the preset node to the second logic state; the consistent energy circuit, when the enabled node is in the second logic state, transitions to a second reset node And the reset circuit is configured to respond to the at least one input logic signal within the plurality of input logic signals, wherein when the plurality of input logic signals are not any of the at least one of the estimated states The reset circuit is coupled to the first reset node to the second reset node. The clockless state return domino logic gate as described in claim 42 wherein at least one of the plurality of input signals includes a state regression signal supplied to the estimation circuit and a state return signal of the reset circuit. The non-clock state returning domino logic gate according to claim 41, further comprising a second device of the second conduction form, having a control end coupled to the output end of the third inverter, having A first current terminal is coupled to the first reset node, and a second current terminal is coupled to the second power potential node. The clockless state return domino logic gate as described in claim 41, wherein the first power supply potential node has a positive power supply potential, and the second power supply potential node has a reference potential, the first conduction form includes The semiconductor P form, and the second conductive form comprises a semiconductor N form. The clockless state return domino logic gate as described in claim 41, wherein the first power supply potential node has a reference potential, and the second power supply potential node has a positive power supply potential, and the first conduction form includes The semiconductor N form, and the second conductive form comprises a semiconductor P form. The clockless state return domino logic gate as described in claim 41, wherein the first and second power supply potential nodes respectively have a positive power supply potential and a reference potential, and at least one of the plurality of input logic signals Including a regression logic '0' signal, wherein: the preset node includes a pre-charge node; the first device of the first conduction form includes a first P-channel device having a gate coupled to the output node, a source receiving the positive power supply potential and having a drain coupled to the precharge node; the first device of the second conductive form includes a first N channel device having a source receiving the reference potential, a gate is coupled to the enabling node and has a drain coupled to the reset node; and the second device in the first conductive form includes a second P channel device having a source receiving the positive power supply The potential has a gate coupled to the output node of the third inverter, and has a drain coupled to the precharge node. The clockless state return domino logic gate as described in claim 41, wherein the first and the second power supply potential nodes respectively comprise a reference potential and a positive power supply potential, wherein the plurality of input logic signals are At least one of the signals includes a regression logic '1', wherein: the preset node includes a pre-clear node; the first device of the first conduction form includes a first N-channel device having a gate coupled to the output a node having a source receiving the reference potential and having a drain coupled to the pre-clear node; the first device of the second conductive form comprising a first P-channel device having a source receiving the positive power supply a potential having a gate coupled to the enabling node and having a drain coupled to the reset node; and the second device in the first conductive form includes a second N channel device having a source receiving the The reference potential has a gate coupled to the output of the third inverter and has a drain coupled to the pre-clear node. An integrated circuit includes: a first circuit that supplies at least one state regression signal, wherein the at least one state regression signal is each switched to a first state and a second state, and the first circuit is configured to After the first state, the first state is set back to the second state according to the state regression operation; the plurality of nodes are switched to the first and second logic states, and the plurality of nodes include a preset node, an output node, and a uniform energy. a node, a reset node, and a plurality of input nodes, at least one of the plurality of input nodes receiving one of the at least one state regression signal; a first inverter having an input coupled to the preset node, and Having an output terminal coupled to the output node; a first device in a first conduction state, having a control terminal coupled to the output node, having a first current terminal receiving a first power source associated with the first logic state a second current terminal coupled to the preset node; a second inverter having an input coupled to the output node Having an output terminal coupled to the enable node; a first device in a second conduction form having a first current terminal receiving a second power supply potential with respect to the second logic state, having a control terminal coupled to the An energy node having a second current terminal coupled to the reset node; a third inverter having an input coupled to the reset node and having an output; a second in a first conduction form The device has a first current terminal for receiving the first power supply potential, a control terminal coupled to the output end of the third inverter, and a second current terminal coupled to the preset node; and an input circuit And coupling the preset node, the reset node, the enabling node, and the plurality of input nodes, wherein when the plurality of input nodes are any one of at least one estimated state, the input circuit shifts the pre- Setting the node to the second logic state, when the plurality of input node transition states are not any of the at least one estimated state, the input circuit temporarily transitions the reset node to the first logic state. The integrated circuit of claim 49, further comprising a second device of the second conductive form, having a control end coupled to the output end of the third inverter, having a first current end The reset node is coupled to the second power terminal to receive the second power supply potential. The integrated circuit of claim 49, wherein the first power supply potential comprises a positive power supply potential, the second power supply potential comprises a reference potential, the first conductive form comprises a semiconductor P-type technology, and the The second form of conduction includes a semiconductor N-type technique. The integrated circuit of claim 49, wherein the first power supply potential comprises a reference potential, the second power supply potential comprises a positive power supply potential, the first conductive form comprises a semiconductor N-type technology, and the The second form of conduction includes semiconductor P-type technology. The integrated circuit of claim 49, wherein the first and second power supply potentials respectively comprise a positive power supply potential and a reference potential, and wherein: the preset node comprises a precharge node; The first device includes a first P-channel device having a gate coupled to the output node, a source coupled to the positive power supply potential, and a drain coupled to the pre-charge node; The first device of the second conductive form includes a first N-channel device having a source receiving the reference potential, having a gate coupled to the enable node, and having a drain coupled to the reset node; The second device of the first conductive form includes a second P-channel device having a source receiving the positive power supply potential, having a gate coupled to the output of the third inverter, and having a gate The bungee is coupled to the pre-charge node. The integrated circuit of claim 49, wherein the first and second power supply potentials respectively comprise a reference potential and a positive power supply potential, and wherein: the preset node comprises a pre-clear node; The first device of the first conductive form includes a first N-channel device having a gate coupled to the output node, having a source receiving the reference potential, and having a drain coupled to the pre-clear node; The first device includes a first P channel device having a source receiving the positive power supply potential, a gate coupled to the enable node, and a drain coupled to the reset node; The second device of the first conductive form includes a second N-channel device having a source receiving the reference potential, having a gate coupled to the output of the third inverter, and having a drain The pre-clear node is coupled. A method for estimating a plurality of logic signals, wherein the plurality of logic signals includes at least one state regression input signal, including: setting a preset node to a first logic state, the first logic being a reverse of a second logic state Phase inverting the preset node to define a logic state of an output node; inverting the output node to define a logic state of the consistent energy node; and transitioning the reset node to the first logic state when the enable node is The second logic state; inverting the reset node to determine a logic state of an inverting reset node; and when the inverting reset node is in the second logic state, transitioning the preset node to the first logic a state; forcing the preset node to be the second logic state only when the plurality of input signals are at least one of the estimated states, the plurality of input signals including at least one state regression input signal, and the state regression logic signal Returning to the second logic state after the transition state is the first logic state; wherein the enable node is the second logic state and the plurality of input signals are back according to the state When the operation is off an estimated state, the reset node is forced to the first logic state; and when the reset node is forced to the first logic state, the inverted reset node transitions to the second logic state, and then Transitioning the preset node back to the first logic state, and then transitioning the output node back to the second logic state, and then transitioning the enable node back to the first logic state, and then transitioning the reset node Returning to the second logic state, then transitioning the inverting reset node back to the first logic state. The method of claim 55, wherein the step of forcing the preset node to the second logic state comprises transitioning at least one of the at least one state regression input signal to the first logic state, And the step of forcing the reset node to the first logic state comprises transitioning at least one of the at least one state regression input signal back to the second logic state. The method of claim 55, further comprising using the half sustain circuit to maintain the reset node as the first logic state. The method of claim 55, further comprising using the half sustain circuit to maintain the reset node as the second logic state. The method of claim 55, wherein the step of setting the preset node to the first logic state comprises pre-charging a pre-charge node to a logic '1', and the resetting the reset node to The step of the second logic state includes transitioning the reset node to a logic '0', and the step of transitioning the preset node to the first logic state includes transitioning the precharge node to a logic '1 ', the step of forcing the preset node to the second logic state comprises forcing the pre-charge node to drop to logic '0', and the step of forcing the reset node to the first logic state comprises forcing the reset node Up to logic '1'. The method of claim 55, wherein the step of setting the preset node to the first logic state comprises setting a pre-clear node to a logic '0', and the resetting the reset node to the second The step of logic state includes transitioning the reset node to logic '1', and the step of transitioning the preset node to the first logic state includes transitioning the pre-clear node to logic '0', and the above-mentioned mandatory The step of presetting the node to the second logic state includes forcing the pre-clear node to logic '1', and the step of forcing the reset node to be the first logic state comprises forcing the reset node to decrease to logic '0' .