CN102355254A - Non-clock-state regression domino logic gate and related integrated circuit and estimation method - Google Patents

Abstract

The invention relates to a non-clock-state regression domino logic gate and a related integrated circuit and an estimation method. The non-clock-state regression domino logic gate responds to a plurality of input nodes comprising at least one state regression node, and a preset node is prearranged to a first state by a domino circuit. When the preset node is pulled to a second state, the domino circuit switches to a locking state and switches the state of an output node; and when a reset node is pulled to the first state, the domino circuit resets to the preset state and switches the output node to a preset value. When the above input node is in an estimation state, an estimation circuit pulls the preset node to a second state, and when the domino circuit is in a locking state, an enable circuit enables a reset condition. After an estimation event, if the rest condition is satisfied and the input node is not in an estimation state, a reset circuit pulls the rest node to a first state.

Description

No clock status returns domino logic gate and relevant integrated circuit and evaluation method

Technical field

The present invention relates to logical circuit; And be particularly related to self-Reset Status and return dominoes formula gates (self-resetting return to state (RTS) domino logic gate); Its operation need not rely on clock signal, and is used for response state recurrence (RTS) signal.

Background technology

The setting of logical circuit on integrated circuit (IC) is purpose with quick actuating logic computing usually, therefore, multiple possibility layout arranged.In many examples, it is difficulty and difficult the realization that clock signal is directed to the circuit that logical operation is provided.Comprise static state and dynamic logic gate and circuit, most logical circuit all need be operated according to an input clock.Static CMOS (Complementary Metal Oxide Semiconductor) gate is with quite low energy operation; But has considerable input capacitance; And wherein signal is that complementary P type device and N type device are wrestled each other and got, and therefore, the operation of static CMOS (Complementary Metal Oxide Semiconductor) gate is quite slow.The staticizer that dominoes formula circuit (Domino) is more relative is quick, but almost always will be controlled by an input clock signal.

This technical field needs a kind of logical circuit or gate, can need not under the state of clock signal with faster and effective and efficient manner carry out logical operation.

Summary of the invention

Return domino logic gate according to the formed a kind of no clock status of one embodiment of the present invention, have a plurality of nodes, a dominoes circuit, an estimation circuit, an activation circuit and a reset circuit.Above-mentioned node designs separately at one first state and one second state and switches.After above-mentioned each leisure of input node is set at above-mentioned first state, returns operation according to state and return above-mentioned second state.The dominoes circuit has a preset condition and a latch mode.When this dominoes circuit was this preset condition, this dominoes circuit was set one and is preset node and an activation node to above-mentioned first state and set this output node and one first replacement node is above-mentioned second state.When this presets the node transition to above-mentioned second state, this dominoes circuit switches to this latch mode, with this output node of transition to above-mentioned first state and this activation node of transition to above-mentioned second state.When this first replacement node transition is above-mentioned first state, this dominoes circuit this preset condition of resetting back.When above-mentioned input node be at least one estimated state any the time, this presets node to this second state this estimation circuit transition, on the contrary then this estimation circuit does not influence the level of this preset node.When this activation node is above-mentioned second state, this second replacement node of this enable circuit transition to above-mentioned first state, on the contrary then this enable circuit does not influence the level of this second replacement node.When above-mentioned input node be not in above-mentioned at least one estimated state any the time, this reset circuit is coupled in above-mentioned first and second replacement node together.When above-mentioned input node be in above-mentioned at least one estimated state any the time, this reset circuit is isolated from each other above-mentioned first and second replacement node.This estimation circuit and this reset circuit can be two configuration designs each other.Said state regression technique can be realized by returning logic ' 0 ' design, is used for responding recurrence logic ' 0 ' input signal, perhaps, can realize by returning logic ' 1 ' design, is used for responding recurrence logic ' 1 ' input signal.

According to the integrated circuit that one embodiment of the present invention realized, return domino logic gate comprising one first logic and a no clock status.This first logic is supplied a plurality of states and is returned signal.Said state returns signal and switches on one first state and one second state separately.Return signal about each state, after being set at first state, it is second state that this first logic can return each state recurrence signal of operating and setting according to state.No clock status returns domino logic gate and comprises a preset node, an activation node, an output node and one first and one second replacement node, switches on first and second state separately.No clock status returns domino logic gate and also comprises a dominoes circuit, an estimation circuit, an activation circuit and a reset circuit.

According to the logical operation evaluation method that one embodiment of the present invention realized.Said method comprises that receiving a plurality of states returns signal.Return signal about each state, can after being set to one first state, return operation and return one second state according to state.This method comprises that also supply has a dominoes circuit of a preset condition and a latch mode.This dominoes circuit can be set one and preset node and an activation node is one first state when this preset condition, and sets an output node and a replacement node is one second state.When this preset node by transition to this second state, this dominoes circuit switched to this latch mode.When this replacement node transition to this first state, this preset condition is returned in this dominoes circuit transition, with this output node of transition to this first state and this activation node of transition to this second state.This method comprises that also the above-mentioned state of estimation returns input signal, and wherein, when said state recurrence input signal was in any of at least one estimated state, this preset node to this second state transition, makes this dominoes circuit switch to its latch mode.This method still is included in the transition when this second state and said state return signal no longer for any of above-mentioned at least one estimated state of this activation node should be this preset condition for this first state with this dominoes circuit of resetting by the replacement node.

Return domino logic gate according to one embodiment of the present invention formed one no clock status, have a plurality of nodes, a dominoes circuit, an estimation circuit, an activation circuit and a reset circuit.Each node switches on one first state and one second state.At least one input node is that a state returns node, can after be set at this first state, return operation according to state and return this second state.This dominoes circuit has a preset condition and a latch mode.When this dominoes circuit is this preset condition, this dominoes circuit set one preset node and an activation node to this first state and set an output node and one first replacement node to this second state.Be pulled to this second state when this presets node, this dominoes circuit switches to this latch mode, this output node is pulled to this first state and this activation node is pulled to this second state.When this first replacement node is pulled to this first state, this dominoes circuit this preset condition of resetting back.When above-mentioned input node was in any of at least one estimated state, this estimation circuit preset node with this and is pulled to this second state; Otherwise this estimation circuit does not interfere this to preset the level of node.When this activation node was in this second state, this enable circuit drew high this second replacement node to this first state.When above-mentioned input node was not in above-mentioned at least one estimated state any, this reset circuit was coupled in above-mentioned first and second replacement node together; Otherwise this reset circuit can be isolated above-mentioned first and second replacement node each other.

Above-mentioned state regression technique can be embodied as the framework that returns logic ' 0 ', returns logic ' 0 ' input signal in order to respond.Perhaps, above-mentioned state regression technique can be embodied as the framework that returns logic ' 1 ', returns logic ' 1 ' input signal in order to respond.Estimation circuit and reset circuit can be used for carrying out jointly the logical operation or the function of any demand, and need not to be defined as two configuration designs each other.In one embodiment, the Set Status of the corresponding above-mentioned input node of estimation circuit, this reset circuit then couple the input node that is less than above-mentioned input node sum.About offering the input node of this reset circuit, each all is that state returns node.

As for integrated circuit, return domino logic gate comprising first logic and a no clock status according to one embodiment of the present invention made.This first logic provides at least one state to return signal, switches on one first state and one second state.Return signal about each state, this first logic can return operation according to this state it setting is back to second state after said state returns signal sets to be first state.Said no clock status returns domino logic gate and has the node of presetting, an activation node, an output node and one first and one second replacement node; Each comfortable above-mentioned first and second state of above-mentioned node switches.Said no clock status returns domino logic gate and also comprises a dominoes circuit, an estimation circuit, an activation circuit and a reset circuit.

As for method, comprising following steps according to formed a kind of estimation one logical operation of one embodiment of the present invention.At first, receive a plurality of input signals, each comfortable first state of said input signal and second state switch.In addition, a dominoes circuit is provided, operates in a preset condition and a latch mode.Under this preset condition, this dominoes circuit is set one and is preset node and an activation node to one first state and set an output node and a replacement node to one second state.When this preset node and is pulled to this second state, this dominoes circuit switched to this latch mode, this output node of transition to this first state and move this activation node to this second state.When this replacement node is moved this first state to, this dominoes circuit this preset condition of resetting back.Said method also comprises: estimate that above-mentioned state returns input signal, when above-mentioned state returns input signal and is in any one at least one estimated state, this preset node move second state to, with this dominoes circuit of transition to this latch mode.Said method also comprises: when this activation node is in this second state and above-mentioned state and returns input signal in above-mentioned at least one estimated state any one, should move this first state to this dominoes circuit of resetting by the replacement node.Above-mentioned input signal comprises that at least one state returns signal, after being set at first state, returns the operation recurrence according to state and is this second state.

No clock status according to one embodiment of the present invention realized returns domino logic gate, comprises a dominoes circuit and an input circuit.This no clock status returns domino logic gate and is used to respond a plurality of input logic signals, and wherein each input logic signal is designed to switch in first and second logic state.The dominoes circuit comprises three inverters, has one first and one second device of one first conductive form and the device with one second conductive form.First inverter is coupled between above-mentioned input and the output node.Second inverter is coupled between an above-mentioned output node and the activation node.The 3rd inverter couples one first replacement node with input.Above-mentioned first device of first conductive form has that a control end couples above-mentioned output node, one first current terminal couples about one first power supply potential node of above-mentioned first logic state and one second current terminal and couples the above-mentioned node that presets.First device of second conducted state has one first current terminal and couples that a second source current potential, a control end about this second logic state couples this activation node and one second current terminal couples this first replacement node.This second device of first conductive form has one first current terminal and couples output and one second current terminal that this first power supply potential node, a control end couple the 3rd inverter and couple this and preset node.When above-mentioned input logic signal was an estimated state, this input circuit preset node with this and moves this second logic state to.When this estimated state was left in above-mentioned input signal transition, this input circuit was temporarily moved this first replacement node to this first logic state.

In one embodiment, this input circuit comprises an estimation circuit, an activation circuit and a reset circuit.When above-mentioned input logic signal was an estimated state, this estimation circuit preset node with this and moves this second logic state to.When this activation node was this second logic state, this enable circuit was moved one second replacement node to this first logic state.When this input logic signal was not this estimated state, this reset circuit coupled this first replacement node to this second replacement node.In one embodiment, this first power supply potential node has one on the occasion of power supply potential, and this second source potential nodes has a reference potential, and this first conductive form is the design of semiconductor P type, and this second conductive form is the design of semiconductor N type.In another embodiment, this first power supply potential node has a reference potential, and this second source potential nodes has one on the occasion of power supply potential, and this first conducting form is the design of semiconductor N type, and this second conducting form is the design of semiconductor P type.Above-mentioned input signal can comprise that at least one state returns signal, and according to different designs, said input signal can return logic ' 1 ' or return logic ' 0 '.

Comprise that according to the integrated circuit that one embodiment of the present invention realized at least one no clock status returns domino logic gate and one first circuit.This at least one state of first circuit supply returns signal, and after above-mentioned state returns signal sets to be first state, according to state recurrence operation it is set at second state.No clock status returns domino logic gate can above-mentioned similar fashion design.

A kind of method of estimating a plurality of input logic signals.Said input logic signal comprises that at least one state returns input signal.This method comprises that it is one first logic state that node is preset in setting one, and this first logic state is the anti-phase of one second logic state.Said method also comprises anti-phase, and this presets node to determine the logic state of an output node; This output node of anti-phase is to determine the logic state of an activation node; Transition one replacement node is to this second logic state when this activation node is this first logic state; Anti-phase should the replacement node to determine a logic state of an anti-phase replacement node; This anti-phase replacement node when this second logic state transition this preset node to this first logic state;, force above-mentioned input signal this to preset node when forming an estimated state to this second logic state; Be supplied in transition and be transition after first logic state and return at least one state of second logic state and return signal, and when this activation node returns this estimated state of operation escape for this second logic state and above-mentioned input signal according to state, force this replacement node to be this first logic state.In addition, when the replacement node is forced this first logic state, this second logic state is returned in the transition of anti-phase replacement node; Then; This presets node for this first logic state transition, comes again, and the above-mentioned output node of transition returns this second logic state; Then; This activation node of transition is got back to this first logic state, and then, transition should be returned this second logic state by the replacement node; And then, this anti-phase replacement node of transition returns this first logic state.

Description of drawings

Below narration will help to understand advantage of the present invention, characteristic and improve content, and the diagram of cooperation comprises:

Fig. 1 is a calcspar of simplifying, and describes a chip or an integrated circuit, comprising returning the dominoes circuit according to the no clock status that one embodiment of the present invention realized;

Fig. 2 is a calcspar, and diagram returns domino logic gate according to the no clock status that one embodiment of the present invention realized, can be used to realize that Fig. 1 does not have clock status and returns the one or more no clock status recurrence domino logic gate in the dominoes circuit;

Fig. 3 is a block schematic diagram, and diagram does not have clock status according to Fig. 2 and returns no clock recurrence logic ' 0 ' domino logic gate that a kind of recurrence logic ' 0 ' execution mode of domino logic gate is realized;

Fig. 4 is a sketch map that returns logic ' 0 ' dominoes circuit, and diagram Fig. 3 returns a kind of execution mode of logic ' 0 ' dominoes circuit;

Fig. 5 is a sequential chart, and diagram Fig. 3 does not have the operation that clock returns logic ' 0 ' domino logic gate, wherein adopts a kind of execution mode of recurrence logic ' 0 ' the dominoes circuit of Fig. 4;

Fig. 6 is a block schematic diagram, and diagram one no clock returns logic ' 0 ' domino logic gate, in order to realize a logic sum gate, M input signal I1...IM is carried out the logic OR computing;

Fig. 7 is a simplification calcspar, and the design of a string repeatedly gate of diagram wherein has three no clock status that are coupled in together to return gates, in order to realize a logical operation;

Fig. 8 is a block schematic diagram, and diagram returns domino logic gate according to the no clock status that another embodiment of the present invention realizes, in order to realize diversified logical operation;

Fig. 9 is a block schematic diagram, and diagram one no clock returns logic ' 0 ' domino logic gate, in order to realize a logic and operation, returns logic ' 0 ' input signal I1...IM to M and carries out logic and operation;

Figure 10 is a block schematic diagram, and another no clock of diagram returns logic ' 0 ' domino logic gate, and in order to realize a logical AND gate, ' 0 ' input signal I1...IM makes logic and operation to M persistent state, comprising a reset circuit of simplifying;

Figure 11 is a block schematic diagram, and diagram one no clock returns logic ' 1 ' domino logic gate, and a kind of recurrence logic ' 1 ' execution mode that its no clock status according to Fig. 2 returns domino logic gate is realized;

Figure 12 is for returning logic ' 1 ' dominoes circuit one sketch map, and diagram Figure 11 returns a kind of execution mode of logic ' 1 ' dominoes circuit;

Figure 13 is a sequential chart, and Figure 11 does not have the operation that clock returns logic ' 1 ' domino logic gate in order to explanation, wherein adopts Figure 12 to return a kind of execution mode of logic ' 1 ' dominoes circuit;

Figure 14 is a block schematic diagram, and diagram one no clock returns logic ' 1 ' domino logic gate, wherein realizes a logic sum gate, returns logic ' 1 ' input signal I1...IM to M and does the logic OR computing;

Figure 15 is the block schematic diagram that a no clock returns logic ' 1 ' domino logic gate 1500, and is made according to another kind of execution mode, in order to carry out a diversified logical operation;

Figure 16 is the block schematic diagram that a no clock returns logic ' 1 ' domino logic gate, in order to realize a logical AND gate, returns logic ' 1 ' input signal I1...IM to M and makes logic and operation; And

Figure 17 is a block schematic diagram of another no clock recurrence logic ' 1 ' domino logic gate, in order to realize a logical AND gate, M recurrence logic ' 1 ' is gone into signal I1...IM carry out logic and operation, comprising a reset circuit of simplifying is arranged.

[main element symbol description]

101～integrated circuit; 103～state returns logic;

104～non-state returns logic;

105～no clock status returns the dominoes circuit;

107～logical circuit;

200～no clock status returns domino logic gate;

201～state returns estimation circuit; 202～preset node;

203～state returns reset circuit; 204～state returns the activation node;

205～state returns the dominoes circuit; 206～replacement node;

207～state returns enable circuit; 208～output node;

210～the second replacement nodes;

300～no clock returns logic ' 0 ' domino logic gate;

301～recurrence logic ' 0 ' estimation circuit; 302～precharged node;

303～recurrence logic ' 0 ' reset circuit;

304～recurrence logic ' 0 ' activation node;

305～recurrence logic ' 0 ' dominoes circuit; 306～replacement node;

308～output node; 310～the second replacement nodes;

400～recurrence logic ' 0 ' dominoes circuit; 401～inverter;

402～half holding circuits; 403,405～inverter;

The reactions of the second status signal RESET of the two configuration designs of 501～sign;

600～no clock returns logic ' 0 ' domino logic gate;

601～recurrence logic ' 0 ' estimation circuit;

603～recurrence logic ' 0 ' reset circuit;

The design of 700～associating gate;

701,703,705～no clock status returns domino logic gate;

800～no clock returns logic ' 0 ' domino logic gate;

801～recurrence logic ' 0 ' estimation circuit; 802～via node;

803～recurrence logic ' 0 ' reset circuit;

900～no clock returns logic ' 0 ' domino logic gate;

901～recurrence logic ' 0 ' estimation circuit;

903～recurrence logic ' 0 ' reset circuit;

1000～no clock returns logic ' 0 ' domino logic gate;

1003～recurrence logic ' 0 ' reset circuit;

1100～no clock returns logic ' 1 ' domino logic gate;

1101～recurrence logic ' 1 ' estimation circuit; 1102～in advance clear node;

1103～recurrence logic ' 1 ' reset circuit;

1104～recurrence logic ' 1 ' activation node;

1105～recurrence logic ' 1 ' dominoes circuit; 1106～replacement node;

1108～output node; 1110～the second replacement nodes;

1200～recurrence logic ' 1 ' dominoes circuit; 1201～inverter;

1202～half holding circuits; 1203,1205～inverter;

1400～no clock returns logic ' 1 ' domino logic gate;

1401～recurrence logic ' 1 ' estimation circuit;

1403～recurrence logic ' 1 ' reset circuit;

1500～no clock returns logic ' 1 ' domino logic gate;

1501～recurrence logic ' 1 ' estimation circuit; 1502～via node;

1503～recurrence logic ' 1 ' reset circuit;

1600～no clock returns logic ' 1 ' domino logic gate;

1601～recurrence logic ' 1 ' estimation circuit;

1603～recurrence logic ' 1 ' reset circuit;

1700～no clock returns logic ' 1 ' domino logic gate;

1703～recurrence logic ' 1 ' reset circuit;

CLK～clock signal;

EVAL～first status signal;

I1...I6～input signal;

I1 (RT0) ... IM (RT0), IX (RT0)～recurrence logic ' 0 ' input signal;

I1 (RT1) ... IM (RT1), IX (RT1)～recurrence logic ' 1 ' input signal;

IN～input signal;

IN (NON-RTS)～non-state returns input signal;

IN (RTS)～state returns input signal;

N1, N2, NA...NM～N lane device;

O1 (RST), O2 (RST)～output signal;

OUT～output;

OUT (RT0)～recurrence logic ' 0 ' output signal;

OUT (RT1)～recurrence logic ' 1 ' output signal;

OUT (RTS)～state returns the output signal;

P1, P2, P3, PA...PM～P lane device;

PCHG～preliminary filling input/output terminal/signal;

PCLR～in advance clear input/output terminal/signal;

PSET～preset input/output terminal;

RESET～second status signal;

RST～reset signal; RSTB～anti-phase reset signal;

RT0E～recurrence logic ' 0 ' enable signal;

RT1E～recurrence logic ' 1 ' enable signal;

RTSE～state returns enable signal;

T0...T14～time point;

VDD～power supply current potential;

VSRC1, VSRC2～power supply potential; VSS～reference potential.

Embodiment

Below explanation will help those skilled in the art to be able to application-specific and condition are made and applied to the disclosed summary of the invention of this specification.Those skilled in the art possibly developed according to following disclosed execution mode and various deformation, and the disclosed skill of specification also possibly realize with other execution modes.Therefore, scope of the present invention be not intention be limited to following shown in or described specific embodiment, in fact, should be with the widest scope explanation of disclosed skill and characteristic.The inventor found industry at a high speed, efficient and need not rely on the demand of the logical operation of clock signal.Therefore, the inventor develop need not clock signal state return domino logic gate, Fig. 1～Figure 17 discussion below is provided.

Fig. 1 is a calcspar of simplifying; Diagram one a chip (or integrated circuit; IC) 101, comprising returning dominoes circuit (clockless return to state domino circuit) 105 according to the no clock status that one embodiment of the present invention realized.Integrated circuit 101 can be any form, and can comprise any amount of electronic circuit that the present technique field has been developed.In one embodiment, chip 101 is a processor, for example a microcontroller (microcontroller) or microprocessor similar devices such as (microprocessor), and in addition, the integrated circuit of any kind or chip all possibly used for it.One clock signal clk is arranged on this integrated circuit 101, returns logical one 03 by a state and receives.This state returns logical one 03 one or more state of output and returns input signal IN (RTS) to a plurality of input nodes that couple these no clock status recurrence dominoes circuit 105 corresponding inputs.This clock signal clk is also pulled strings to non-state recurrence logic (NON-RTS logic) 104.This non-state returns one or more non-state of logical one 04 output and returns signal IN (NON-RTS) to a plurality of inputs that couple these no clock status recurrence dominoes circuit 105 corresponding inputs.Below more be described in detail.The design that returns dominoes circuit 105 along with no clock status is different, and the content of input signal IN (combination of IN (RTS) and IN (NON-RTS)) can be different.(for example, two configuration design/dual configurations) in some applications, each input signal IN is that state returns signal RTS (being designed to example with logic sum gate).In addition; In other are used (for example; Non-two configuration design/non-dual configuration), has one among the input signal IN at least, then return signal RTS or non-state recurrence NON-RTS signal for state as for remaining each signal in the input signal IN for state returns signal RTS.Usually, be under following situation, to need development to return signal with above-mentioned state is provided.Above-mentioned no clock status returns the one or more states of dominoes circuit 105 outputs and returns the relevant input of output signal OUT (RTS) to another logical circuit 107, and clock signal clk also is connected to the input end of clock of logical circuit 107.State returns logical one 03 and comprises the combination of any static state or dynamic circuit, and also comprises the combination of any latching (latch) or buffer circuit, to return operation according to state input signal IN is provided (RTS).Logical one 07 comprises that the combination and/or any of any static state or dominoes circuit (pin position footed is arranged or do not have pin position footless) is latched or the combination of buffer, to receive or to latch or temporary said output signal OUT (RTS).

What described state returned input and output signal IN and OUT representative is that signal can be got back to a predetermined state or one first state after switching to one second state.In the binary system logic, it is not to get back to logic ' 0 ' RT0 that state returns, and its logic of propositions state is a logic ' 0 '), get back to logic ' 1 ' (RT1, its logic of propositions state is a logic ' 1 ') exactly.No clock status returns dominoes circuit 105 and comprises that one or more no clock status returns domino logic gate.Said no clock status returns domino logic gate and goes here and there each other repeatedly (cascade), or is coupled in together according to any serial or parallel connection mode.The no clock status recurrence domino logic gate of multiple quantity is all had an opportunity to be gone here and there repeatedly or is cascaded, and only is subject to time conditions, and whether effectively said time conditions is defined in corresponding output signal.Each no clock status returns domino logic gate and can receive any amount of state and return input signal and export at least one state and return and output signal to other no clock status recurrence domino logic gate or logical circuit 107 or other similar circuit of other circuit-comprise.

Fig. 2 is a calcspar, and the no clock status that diagram is realized according to a kind of execution mode of the application returns domino logic gate 200, returns domino logic gate in order to realize the one or more no clock status that this no clock status returns in the dominoes circuit 105.One or more signal provision in the input signal IN are given on the corresponding input node, return the corresponding input of estimation circuit 201 with the state that inputs to, and at least one above-mentioned input signal IN can offer a state and returns reset circuit 203.Though indicate among the figure will same input signal IN supplying to circuit 201 and 203 both, in some embodiments-following will go through-be supplied to this state recurrence reset circuit 203 can only be the subclass of above-mentioned input signal IN.In addition, input signal IN can be state and returns signal (RTS) and can comprise that maybe one or more non-state returns signal (non-RTS).No clock status returns domino logic gate 200 and comprises that also a state returns dominoes circuit 205; This state returns dominoes circuit 205 and couples pair of electrical source electric potential VSRC1 and VSRC2.Each is provided power supply potential VSRC1 and VSRC2 by a power circuit (do not have and show in the drawings), and unifies the power supply current potential with appropriate potential and give a plurality of electronic circuits on the integrated circuit 101, and institute's employing technology can be present technique field common technique.Current potential that each power supply potential is supplied and corresponding potential region and circuit pattern and particular technology or technology between power supply potential VSRC1 and VSRC2 are relevant, for example, can be 5 volts, 3.3 volts or 2.1 volts etc.Usually, one of power supply potential VSRC1 and VSRC2 are that (for example, VSS), and another is a power supply current potential VDD to a reference potential, can present technique field common technique realize.State returns estimation circuit 201, state returns reset circuit 203 and can form an input circuit jointly with state recurrence enable circuit 207, corresponding input signal IN action.

State returns estimation circuit 201 and couples power supply potential VSRC2, and also couples one and preset node 202 and return one of dominoes circuit 205 and preset I/O end PSET to couple this state.This state recurrence dominoes circuit 205 has an output and supplies state recurrence output signal OUT (RTS) in an output node 208; And have a replacement input/output terminal RST and produce a reset signal (being designated as RST equally), and also have a state and return enable signal output RTSE and supply a state and return enable signal (being designated as RTSE equally) and return activation node 204 in a state of correspondence in a replacement node 206.No clock status returns domino logic gate 200 and comprises that a state returns enable circuit 207 and couples power supply potential VSRC1.This state returns enable circuit 207 to have an input and couples node 204 and return enable signal RTSE to receive this state, and has another end points and couple one second replacement node 210.This state returns reset circuit 203 and is coupled between above-mentioned replacement node 210 and 206.

Each signal node (for example, IN, OUT, PSET, RST, RTSE etc.) has one first logic state and one second logic state; This first logic state is relevant to power supply potential VSRC2, and this second logic state is relevant to power supply potential VSRC1.State returns estimation circuit 201 and has an initial preset state, and this moment, each input signal IN was above-mentioned first logic state, and (return state) is identical with its persistent state.When together transition of above-mentioned input signal IN, when forming in one or more estimated state any, this state returns estimation circuit 201 and gets into an estimated state, produces an estimation incident.The said estimation incident of one or more estimated state-generations of said input signal IN-relevant by this state recurrence estimation circuit 201 logical design separately.For example, be designed to a logic sum gate, then take place during the transition of an estimation incident arbitrary or a plurality of generation first state to the second state in said input signal IN if this state returns estimation circuit 201.In the another kind of execution mode, be to be embodied as a logical AND gate if this state returns estimation circuit 201, then an estimation incident only can be at each input signal IN be all taken place during to this second logic state by this first logic state transition.This state returns dominoes circuit 205 and has two states usually, comprises a preset condition (" preset " state) and a latch mode (" latch " state).This preset condition is generally the initial or preset value that this state returns dominoes circuit 205.Under this preset condition, this state recurrence dominoes circuit 205 can preset it and preset I/O end PSET, so node 202 is this second logic state.In addition, under this preset condition, state returns this reset signal of dominoes circuit 205 initial settings RST for this first logic state and set this state and return enable signal RTSE and be this second logic state.This state returns reset circuit 203 and has an isolation (isolation state) and a Reset Status (reset state), by the state decision that applies said input signal IN thereon.Be in separately or return this first logic state when putting on said input signal IN that this state returns reset circuit 203, it is its Reset Status that this state returns reset circuit 203.Otherwise this state returns reset circuit 203 and is in its isolation.What must specify is that when collective's state symbol of said input signal IN closed any of one or more estimated state, it was to be positioned at its isolation that state returns reset circuit 203.When this state recurrence enable signal RTSE was in this second logic state, this state returned enable circuit 207 and is in its initial preset state; When this state recurrence enable signal RSTE was in this first logic state, this state returned enable circuit 207 transition to activation states.

The operation that no clock status returns domino logic gate 200 below is discussed.One estimation incident occur in said input signal IN transition be in one or more estimated state any the time; At this moment, this state returns estimation circuit 201 and gets into its estimated state and this state recurrence reset circuit 203 its isolations of entering.In above-mentioned estimated state; This state returns the signal that estimation circuit 201 changes node 202; Therefore, what state returned dominoes circuit 205 presets input/output terminal PSET transition to this first logic state, causes this state to return dominoes circuit 205 and switches to latch mode from its preset condition.This state returns dominoes circuit 205 and when switching to its latch mode, switches output signal OUT to this second logic state, and switching state recurrence enable signal RTSE to the first logic state, and no longer influences this reset signal RST.State returns enable circuit 207 and gets into its enabled status, couples node 210 to power supply potential VSRC1, returns enable signal RTSE with the state of responding first logic state.Be in its isolation because state returns reset circuit 203 response input signal IN, therefore, be enabled, still do not influence this reset signal RST even state returns enable circuit 207.For these reasons, this reset signal RST still maintains first logic state.

When returning input signal IN, the state that is supplied to state to return reset circuit 203 gets back to its preset state according to state recurrence operation; State returns reset circuit 203 and gets into its Reset Status; Replacement node 210 is coupled in 206, reset signal RST is pulled to this second logic state through circuit 203 and 207.The transition meeting of reset signal RST to the second logic state causes a resetting event, makes state return dominoes circuit 205 and returns its preset condition.Illustrate that as follows state returns the 205 meeting changes of dominoes circuit, and it presets the current potential of input/output terminal PSET, makes node 202 get back to second logic state.In addition, state returns dominoes circuit 205 can switch back first logic state with output signal OUT, and switching state recurrence enable signal RTSE returns this second logic state.This state returns the transition of enable circuit 207 meeting corresponding statess recurrence enable signal RTSE to the second logic states and closes effectively, and state recurrence dominoes circuit 205 can retract first logic state with reset signal RST.

Generally speaking, when input signal IN together transition in one or more estimated state any the time, state returns estimation circuit 201 transitions to an estimated state, produces an estimation incident, and this state returns reset circuit 203 and gets into an isolation.Respond above-mentioned estimation incident, state return dominoes circuit 205 from its preset condition transition to latch mode, switch output signal OUT and switch this state and return enable signal RTSE with this state recurrence enable circuit 207 of activation.When these states that return input signal IN or be supplied to this state to return reset circuit 203 at least when each state returned input signal IN and return operation and get back to first logic state according to state, state returned estimation circuit 201 and gets back to its preset state and this state and return reset circuit 203 and get into its Reset Status and move this reset signal RST to this second logic state to produce a resetting event.Respond this resetting event, this state returns dominoes circuit 205 and gets back to its preset condition, makes this state return enable signal RSTE and returns this second logic state with this state recurrence enable circuit 207 of decapacitation.In case this state returns enable circuit 207 decapacitation, state returns the just no longer influence operation of state of reset circuit 203, after another estimation incident takes place.This state returns dominoes circuit 205 and subsequently reset signal RST is retracted first logic state, makes this no clock status return domino logic gate 200 and prepares the next estimation incident of meeting.Thus, it is a self-reset circuit that no clock status returns domino logic gate 200, need not clock signal promptly realize logic situation estimation.

Recurrence logic ' 0 ' (RT0) gate design and recurrence logic ' 1 ' (RT1) gate design that no clock status returns domino logic gate 200 below more are discussed.Said recurrence logic ' 0 ' gate design is to be used for responding recurrence logic ' 0 ' input signal.Said recurrence logic ' 1 ' gate design is to be used for responding recurrence logic ' 1 ' input signal.In some embodiments, state returns estimation circuit 201 and state recurrence reset circuit 203 is two configurations (dual configurations) designs, returns input signal IN in order to respond same state.In such execution mode (for example; The 10th and 17 figure illustrated embodiment); State returns reset circuit 203 and is simplified; Wherein, These states that are supplied to this state to return estimation circuit 201 return input signal IN and also can be supplied to state to return reset circuit 203; Simultaneously, returning estimation circuit 201 same logical operation meetings with state is implemented on selected this state recurrence input signal IN subclass by state recurrence reset circuit 203.In other embodiments, circuit 201 and 203 is not two configuration designs, and among the said input signal IN of supplying to circuit 201 only a subclass be to be supplied to this state to return reset circuit 203.The said input signal IN that is supplied to this state to return reset circuit 203 is that state returns signal, and no matter remaining input signal IN is a state returns (RTS) or non-state recurrence (non-RTS) signal.In said arbitrary execution mode, estimated state is a true time, and Reset Status just is false.State returns estimation circuit and shows that estimated state was invalid when estimated state did not meet.Be false but state returns the replacement condition of reset circuit when setting up in estimated state, said Reset Status is set up.

Fig. 3 is a calcspar, and diagram one no clock returns logic ' 0 ' domino logic gate 300, returns a kind of recurrence logic ' 0 ' execution mode of domino logic gate 200 for no clock status.Output signal OUT and at least one input signal IN are designed to return logic ' 0 ' signal, are the logic of propositions state with logic ' 0 '.Based on present technique field prior art, with power supply potential VSRC1 as a power supply current potential VDD, and with power supply potential VSRC2 as a reference potential VSS.This state recurrence estimation circuit 201, state recurrence dominoes circuit 205 and state recurrence reset circuit 203 are realized as a recurrence logic ' 0 ' estimation circuit 301, respectively and return logic ' 0 ' dominoes circuit 305 and a recurrence logic ' 0 ' reset circuit 303, design in order to operate according to recurrence logic ' 0 '.Should be noted that; Though in circuit 301 and 303 any possibly to isolate other circuit be one to return logic ' 1 ' circuit (seeing with its output), but still be to patrol with recurrence and the viewpoint of ' 0 ' domino logic gate 300 allomeric functions is looked serve as recurrence logic ' 0 ' technology with its input.The aforementioned input/output terminal PSET that presets is implemented as a preliminary filling input/output terminal PCHG.This preliminary filling input/output terminal PCHG couples a precharged node 302; This precharged node 302 is realized the aforementioned node 202 that presets.No clock returns logic ' 0 ' domino logic gate 300 and sets a recurrence logic ' 0 ' output signal OUT in an output node 308, and reset signal RST then is created in replacement node 306.Aforesaid state returns activation node 204 and is implemented as a recurrence logic ' 0 ' activation node 304, couples the grid of P lane device P1.Said P lane device P1 realizes that aforesaid state returns enable circuit 207.It is that VDD and its drain electrode couple recurrence logic ' 0 ' reset circuit 303 via one second replacement node 310 that the source electrode of P lane device P1 couples the power supply electricity.Return logic ' 0 ' reset circuit 303 and also couple replacement node 306.

Fig. 4 diagram one returns logic ' 0 ' dominoes circuit 400, for returning a kind of execution mode of logic ' 0 ' dominoes circuit 305.Precharged node 302 couples the input of an inverter 401, and couples the drain electrode of P lane device P2 and P3.The output of inverter 401 couples output node 308 said recurrence logic ' 0 ' output signal OUT (RT0) is provided, and it is supplied to the grid of P lane device P3 and the input of another inverter 403.The output of inverter 403 couples node 304 returns logic ' 0 ' enable signal RT0E to N lane device N1 with the supply shape grid.The source electrode of N lane device N1 couples reference potential VSS, and its drain electrode couples replacement node 306 with supply reset signal RST.Reset signal RST is supplied to the input of an inverter 405.The output of inverter 405 is supplied an anti-phase reset signal RSTB.Anti-phase reset signal RSTB is supplied to the grid of P lane device P2, and its source electrode couples power supply current potential VDD.Inverter 401 is together formed half with P lane device P3 and is kept (half-keeper) circuit 402, it is dragged down until returning logic ' 0 ' estimation circuit 301 with the level of keeping preliminary filling input/output terminal PCHG.The initial preliminary filling of preliminary filling input/output terminal PCHG is a high level, and therefore, inverter 401 order output signal OUT are low level, with conducting P lane device P3.P lane device P3 is pulled to power supply current potential VDD with preliminary filling input/output terminal PCHG, to keep the high level logic state of preliminary filling input/output terminal PCHG.Because output signal OUT is initially low level, inverter 403 orders return logic ' 0 ' enable signal RT0E conducting N lane device N1, to drag down the level of reset signal RST.The inverter 405 thereby anti-phase reset signal RSTB of high level can be provided makes not conducting of P lane device P2.

With reference to figure 3 and Fig. 4; An estimation incident that is produced when responding single or a plurality of transitions among the input signal IN for one or more estimated state wherein a kind of; Returning logic ' 0 ' estimation circuit 301 can drag down preliminary filling input/output terminal PCHG level, causes to return 400 transitions of logic ' 0 ' dominoes circuit to its latch mode.Therefore, inverter 401 is drawn high the level of output signal OUT, makes not conducting of P lane device P3.Inverter 403 can drag down the level that returns logic ' 0 ' enable signal RT0E, makes the P1 conducting of P lane device and makes not conducting of N lane device N1.The conducting meeting of P lane device P1 makes node 310 be couple to power supply current potential VDD.The not conducting meeting of N lane device N1 makes reset signal RST no longer be restricted to low level.The estimated state of input signal IN can make and return 303 transitions of logic ' 0 ' reset circuit to its isolation, makes node 306 isolate node 310.Thus, replacement node 306 can be isolated by temporary transient, is not any state so reset signal RST can painstakingly not drive.Owing to have no other device effects, reset signal RST still maintains low level.In another embodiment, other has a N lane device N2 (indicating with dotted line) supply in Fig. 4 circuit, forms second half holding circuit with inverter 405, to keep the low level state of reset signal RST.N lane device N2 has a grid and receives anti-phase reset signal RSTB, and a drain electrode couples node 306, and one source pole couples reference potential VSS.Because anti-phase reset signal RSTB is initially high level, N lane device N2 makes node 306 under the state of not conducting of N lane device N1, still be low level.N lane device N2 be used to guarantee or guarantee reset signal RST under aforesaid state still for low level.IN is in estimated state when input signal, returns logic ' 0 ' reset circuit 303 and keeps its isolation.

When each recurrence logic ' 0 ' the input signal IN that is supplied to this recurrence logic ' 0 ' reset circuit 303 revert to its preset state; Return 303 transitions of logic ' 0 ' reset circuit to its Reset Status; Produce a resetting event; Wherein, P lane device P1 and recurrence logic ' 0 ' reset circuit 303 together draw high reset signal RST and are high level.Note that if said circuit has N lane device N2 returning logic ' 0 ' reset circuit 303 needs design to resist N lane device N2 to draw high the level of reset signal RST.Inverter 405 thereby can drag down the level of anti-phase reset signal RSTB makes P lane device P2 conducting.The P lane device P2 of conducting can be pulled up to its preset state with the current potential of preliminary filling input/output terminal PCHG.Please note; When each recurrence logic ' 0 ' the input signal IN that is supplied to this recurrence logic ' 0 ' reset circuit 303 gets back to preset state; Input signal IN no longer is in an estimated state, so return the level that logic ' 0 ' estimation circuit 301 no longer drags down preset input/output terminal PCHG.Thus, P lane device P2 draws high back its precharging state with the level of preliminary filling input/output terminal PCHG.When the level of preliminary filling input/output terminal PCHG is a high level, inverter 401 order output signal OUT are low level once more, and with conducting P lane device P3, keeping preliminary filling input/output terminal PCHG is high level.Inverter 403 will return logic ' 0 ' enable signal RT0E draw high for high level with conducting N lane device N1 and make not conducting of P lane device P1.Because not conducting of P lane device P1 returns logic ' 0 ' reset circuit and isolates with power supply current potential VDD, and no longer draws high reset signal RST.In addition; The N lane device N1 of conducting can move reset signal RST to low level; And it is high level that inverter 405 can draw high anti-phase reset signal RSTB, to make not conducting of P lane device P2 (and in the example that supply N lane device N2 is arranged, also comprising making N lane device N2 conducting).Though not conducting of P lane device P2, it is high level that half holding circuit 402 can be kept preliminary filling input/output terminal PCHG.Thus, return logic ' 0 ' dominoes circuit 400 its preset condition of resetting back, be ready to meet next estimation incident.

Fig. 5 does not have the operation that clock returns logic ' 0 ' domino logic gate 300 with the sequential chart diagram, wherein will return logic ' 0 ' dominoes circuit 400 according to a kind of execution mode and be used for realizing returning logic ' 0 ' dominoes circuit 305.The first status signal EVAL shows an estimated state that should return logic ' 0 ' estimation circuit 301, and the generation of an estimation incident is represented in the establishment of this estimated state.The first status signal EVAL is high level when this estimated state is set up and is low level when this estimated state is false.The quantity of the estimated state of input signal IN is decided by to return the logic function design of logic ' 0 ' dominoes circuit 305.For example, be designed to a logic OR function if return logic ' 0 ' dominoes circuit 305, then among these input signals IN any or a plurality ofly can distinguish a corresponding estimated state for the situation of high level.If return logic ' 0 ' dominoes circuit 305 is that design realizes a logical AND function, and then input signal IN only has an estimated state; Under this estimated state, each input signal IN is a high level.The second status signal RESET shows a Reset Status that returns logic ' 0 ' reset circuit 303; When this Reset Status was set up, this second status signal RESET was a high level; When this Reset Status was false, this second status signal RESET was a low level.The state that said Reset Status is decided by to return the design of logic ' 0 ' reset circuit 303 and is supplied to these input signals IN that returns logic ' 0 ' reset circuit 303.Whenever input signal IN is any of a kind of or multiple estimated state, Reset Status is false and is returned logic ' 0 ' reset circuit 303 and is in its isolation.When being supplied to each that return logic ' 0 ' reset circuit 303 to return logic ' 0 ' input signal IN to get back to logic ' 0 ', returning logic ' 0 ' reset circuit 303 and be in its Reset Status.Said resetting event only betides recurrence logic ' 0 ' enable signal RT0E and makes the low level of P lane device P1 conducting and return logic ' 0 ' reset circuit 303 when its Reset Status.Minority is used and is relied on estimation and reset circuit design to each other.No matter be two configurations or non-two configuration design, when all input signal IN returned logic ' 0 ', Reset Status was set up, and estimated state is false.Under two configurations and non-two configuration design, when estimated state is set up, the neither establishment of Reset Status.Non-two configuration design down, only the subclass of input signal IN is to be supplied to this recurrence logic ' 0 ' reset circuit 303, Reset Status possibly also is false when estimated state is false, and possibly change into still to keep after being false in estimated state and be false.

Fig. 5 comprises the sequential chart of signal EVAL, RESET, PCHG, OUT, RT0E, RST and RSTB.Shown in the transition of signal postpone only to be the signal effect, be not that intention is to the particular design bounded delay time.At initial time T0, the first status signal EVAL is a low level, and expression input signal IN is not in estimated state.The second status signal RESET then is a junk at sequential T0.Note that according to returning logic ' 0 ' operation input signal IN (these are for returning the signal of logic ' 0 ' at least) returns and is logic ' 0 ' before interval back of an estimation and the interval effect of next estimation.Yet each input signal possibly have different time to postpone.When input signal IN all is set at preset state, the first status signal EVAL is that the low level and the second status signal RESET are high level.If some or a plurality ofly convert high level into but still do not meet the condition (before estimation next time is interval) of estimated state in the input signal, then the second status signal RESET maybe be between bifurcation conversion one or repeatedly and the while first status signal EVAL keep low level.Therefore, the second status signal RESET is not a particular state as shown in the figure, in addition, does not act on because state returns enable circuit 207 (in returning logic ' 0 ' example, being realized by P lane device P1), and said any bifurcation early than the estimation incident changes unimportant.Signal PCHG, OUT, RT0E, RST and RSTB are initially set logic ' 1 ', ' 0 ', ' 1 ', ' 0 ' and ' 1 ' respectively in time T 0.

The time point T1 that continues, input signal IN together gets into an estimated state, so the first status signal EVAL draws high and the second status signal RESET drags down.Respond the first status signal EVAL of high level, return logic ' 0 ' estimation circuit 301 and drag down preliminary filling input/output terminal PCHG current potential, to cause an estimation incident through the connecting time point T2 after short delay.Because the second status signal RESET is a low level, returns logic ' 0 ' reset circuit 303 and be in its isolation.Response is pulled to low level preliminary filling input/output signal PCHG, and the connecting time point T3 of inverter 401 after short delay draws high the level of output signal OUT.Along with drawing high of output signal OUT, the connecting time point T4 of inverter 403 after short delay drags down the level of this recurrence logic ' 0 ' enable signal RT0E, with conducting P lane device P1 and not conducting N lane device N1.Be not conducting because return logic ' 0 ' reset circuit 303, reset signal RST is not influenced by any device, and maintains low level (or maintain low level by N lane device N2).The state of no clock recurrence logic ' 0 ' domino logic gate 300 remains unchanged and the first status signal EVAL is a high level.At the time point T5 that continues, its state of one or more signal change causes estimated state to be false among the input signal IN, corresponding it, the first status signal EVAL transition is a low level.If be supplied to return logic ' 0 ' reset circuit 303 input signal each also get back to logic ' 0 ', the second status signal RESET draws high like dotted line 501 at time point T5.If the embodiment of the two configuration designs of right and wrong, first status signal EVAL transition to the low level, with the second status signal RESET transition to there being a delay between the high level.Must be noted that estimated state is false and returns logic ' 0 ' estimation circuit 301 and behind time point T5, no longer drags down preliminary filling input/output signal PCHG because the first status signal EVAL is a low level.Preliminary filling input/output signal PCHG keeps low level, is pulled up to high level until follow-up by P lane device P2.Note that it is low level that another half holding circuit (not in graphic) can be used in above-mentioned condition, keep preliminary filling input/output signal PCHG.

At time point T5 or the time point T6 that continues, being supplied to the input signal IN transition that returns logic ' 0 ' reset circuit 303 is zero, and to start the Reset Status that should return logic ' 0 ' reset circuit 303, making the second status signal RESET is high level.Said recurrence logic ' 0 ' replacement current potential 303 associating P lane device P1, the time point T7 after short delay draws high the current potential of reset signal RST, to begin a resetting event.The time point T8 of inverter 405 after short delay drags down anti-phase reset signal RSTB to respond it.Anti-phase reset signal RSTB transition is a low level, and with conducting P lane device P2, the time point T9 after a short delay draws high back preset state with preliminary filling input/output signal PCGH.When preliminary filling input/output signal PCHG is a high level, the time point T10 of inverter 401 after short delay will export signal OUT and be set at low level once more.Transition is that low level output signal OUT understands conducting P lane device P3, and making half holding circuit 402 keep this preliminary filling input/output signal PCHG is that high level draws under the interval general of next one estimation.The time point T11 of inverter 403 after short delay will return logic ' 0 ' enable signal RT0E and move high level to.The high level state that returns logic ' 0 ' enable signal RT0E can make the N1 conducting of N lane device and make not conducting of P lane device P1.Because not conducting of P lane device P1 returns logic ' 0 ' reset circuit 303 and no longer draws high reset signal RST.The conducting meeting of N lane device N1 makes the time point T12 of reset signal RST after short delay retract low level.Inverter 405 can draw high anti-phase reset signal RSTB to high level by the time point T13 after short delay, and therefore, P lane device P2 no longer draws high preliminary filling input/output signal PCHG.At this moment, keeping preliminary filling input and output PCHG by half holding circuit 402 is high level.At time point T13 time point T14 after a while; Signal recovers its preset state; Return logic ' 0 ' estimation circuit 301 and P lane device P1 all in its preset state; Return logic ' 0 ' dominoes circuit 305 and get back to its preset condition; In addition; Suppose that each signal all is a low level in the input signal IN, return logic ' 0 ' reset circuit 303 and be in its Reset Status.Generally speaking, the estimated state of input signal IN causes an estimation incident, and causing exporting signal OUT is high level, and the resetting event that continues of activation.The Reset Status of input signal IN causes returning logic ' 0 ' reset circuit 303 and causes a resetting event, and does not have clock recurrence logic ' 0 ' domino logic gate 300 and get back to its initial condition, prepares to meet next estimation interval.

As shown in the figure, the second status signal RESET is that high level is until time point T11.During time point T11, returning logic ' 0 ' enable signal RT0E transition is that high level is got back to its initial condition to confirm this no clock recurrence logic ' 0 ' domino logic gate, and so far, the second status signal RESET is meaningless.Note that reset signal RST when time point T7 moves high level to, even Reset Status is false and is dragged down the second status signal RESET, reset signal RST still maintains high level, and reason is that N lane device N1 still is not conducting, can't influence reset signal RST.Therefore; Though it is high level until returning logic ' 0 ' enable signal RT0E transition that Reset Status should be maintained in upright; Input signal can be behind time point T7 with time point T11 before drag down the level of the second status signal RESET and do not exert an influence, therefore, can keep suitable circuit operation.In case returning logic ' 0 ' enable signal RT0E is high level, not conducting of P lane device P1, and the meaningless transition of any input signal IN does not all have effect behind time point T11.The situation of non-above-mentioned meaningless transition then possibly cause an estimated state in addition.The state that note that returns signal RTS possibly not exist meaningless transition.Yet some input signal possibly return signal and possibly have meaningless transition for non-state.Being supplied to the input signal IN that returns logic ' 0 ' estimation circuit 301 is that the estimated state that is selected to avoid potential takes place.

Fig. 6 is a block schematic diagram, and diagram one no clock returns logic ' 0 ' domino logic gate 600, in order to realize a logic sum gate, M input signal I1...IM that returns logic ' 0 ' is done the logic OR computing, and wherein, M is the positive integer greater than 1.In such execution mode, input signal I1...IM returns logic ' 0 ' signal.No clock returns logic ' 0 ' domino logic gate 600 and comprises recurrence logic ' 0 ' dominoes circuit 305.These recurrence logic ' 0 ' dominoes circuit 305 couple one and return logic ' 0 ' estimation circuit 601 (in order to realize returning logic ' 0 ' estimation circuit 301), and couple a recurrence logic ' 0 ' reset circuit 603 (in order to realize returning logic ' 0 ' reset circuit 303).Return logic ' 0 ' estimation circuit 601 and comprise M N lane device NA...NM, couple node 302 with drain electrode separately, and couple reference potential VSS with source electrode separately.N lane device NA...NM has a grid separately, corresponding as shown in the figure receiving inputted signal I1...IM.Similarly, return logic ' 0 reset circuit 603 and comprise M P lane device PA...PM, be serially connected with between the second replacement node 310 and the replacement node 306.As shown in the figure, wherein the drain electrode of first P lane device PA and P lane device P1 is coupled in node 310, then couples the source electrode of next P lane device as for the drain electrode of P lane device PA.According to this serial connection rule, wherein last P lane device PM couples node 306 with its drain electrode.P lane device PA...PM separately as shown in the figure with grid receiving inputted signal I1...IM one of them.Install two signal I1 and IM among PA and PM, a plurality of input signal I1...IM though only draw among among a plurality of N lane device NA...NM two device NA and NM, a plurality of P lane device PA...PM two in the diagram; It must be appreciated; Any amount of said device and signal all possibly be its execution mode (for example, being supplied to the input signal I2... etc. of the grid of N lane device NB and P lane device PB).

No clock returns a kind of execution mode that logic ' 0 ' domino logic gate 600 is two configuration designs, wherein returns logic ' 0 ' reset circuit 603 for returning two configuration designs of logic ' 0 estimation circuit 601.Under two configuration designs, being supplied to and returning logic ' 0 ' estimation circuit 601 all is input signal I1...IM with the signal that returns logic ' 0 ' reset circuit 603.The operation that no clock returns logic ' 0 ' domino logic gate 600 meets sequential chart shown in Figure 5 usually.Under such state, ' 0 ' operation is logic ' 0 ' according to the recurrence logic as input signal I1...IM, and the first status signal EVAL is that the low level and the second status signal RESET are high level.Any is a high level in input signal I1...IM, and estimated state is set up, and Reset Status is false; Therefore, the first status signal EVAL is that the high level state and the second status signal RESET are low level state.Because circuit 601 and 603 is two configuration designs, along with the transition of input signal IN is switched, the first status signal EVAL and the second status signal RESET can and then switch and be maintained anti-phase each other.Along with any transition among the input signal IN is a logic ' 1 '; Preliminary filling input/output signal PCHG transition is a low level; Output signal OUT transition after short delay is a high level, and recurrence logic ' 0 ' enable signal RT0E transition after another section short delay is that low level is with activation one resetting event.When input signal I1...IM each when returning logic ' 0 ' operation and get back to logic ' 0 '; Return logic ' 0 ' reset circuit 603 and cause this resetting event; It is high level that ream weight is put signal RST transition; Anti-phase reset signal RSTB transition is a low level, and preliminary filling input/output signal PCHG draws high to high level and exports signal OUT and get back to low level as previously mentioned.

In some design, the limited amount that returns the P lane device that is connected in series in logic ' 0 ' reset circuit 603 is a specific quantity, to guarantee proper handling.For example, in a certain execution mode, the maximum quantity that allows to be serially connected with the P lane device of 306 of power supply current potential VDD and replacement nodes is 4, the quantity of input signal thereby be restricted to 3 (M is 3).For a large amount of input signals is carried out the logic OR computing, a plurality of no clocks can be returned logic ' 0 ' domino logic gate 600 and combine or go here and there to stack togather, through a large amount of gates any amount of input signal is carried out the logic OR computing, below describe in detail.

Fig. 7 is a simplification calcspar, and three no clock status of diagram return the associating gate design 700 that domino logic gates 701,703 and 705 are formed, in order to realize a logical operation.Associating gate design 700 as shown is state and returns pattern, and can be applicable to any recurrence logic ' 0 ' or return logic ' 1 ' use.In one embodiment, six input signal I1...I6 produce a state and return output signal OUT after logical operation.Among the input signal I1...I3 at least one or go up to all being that state returns signal totally, and among the input signal I4...I6 at least one or go up to all being that state returns signal totally.Associating gate design 700 comprises that two three the no clock status of input return domino logic gates 701 and 703 and another dual input state recurrence domino logic gate 705.State returns domino logic gate 701 receiving inputted signal I1...I3 and the state of supplying returns output signal O1 (RTS), returns an input signal of domino logic gate 705 as state.Likewise, state returns domino logic gate 703 receiving inputted signal I4...I6 and the state of supplying returns output signal O2 (RTS), returns another input signal of domino logic gate 705 as state.State returns domino logic gate 705 and returns defeated signal OUT (RTS) at its output supply status.Thus, a plurality of no clock status return domino logic gates can be combined or string stack togather, to deal with a large amount of input signals, accomplish a certain logic computing.In addition, still there are other designs can accomplish same computing.For example, realize first order structure, receive two signals in six input signals separately, and produce an output signal separately, to unite input signal as one three input logic gate with three dual input gates.Perhaps, said technology also can be used for realizing the logical operation of the input signal of other quantity, above-mentioned for several 6 input signals only be that explanation is used.

Gates 701,703 in the said associating gate design 700 respectively can be according to different logical computing demand-for example with 705, logical AND (AND), logic OR (OR), logical AND non-(NAND), logic NOT or (NOR), logic XOR (XOR) ... wait or the suitable or available input signal realization of set-cooperation of any said logical operation.For example, about logical difference exclusive disjunction-XOR of signal A and signal B (A, B)-a logic XOR gate, state return input signal A and B with and inversion signal A ' and B ' (label " ' " be represented as inversion signal) need be supplied.Gate 701,703 in the associating gate design 700 can be carried out different computings with 705.Though only show three gates among the figure, what must state is, the technology series, parallel that any amount of gate all can be known based on present technique field person or otherwise combine.For example, gate 701,703 and 705 can be embodied as a logic sum gate according to no clock recurrence logic ' 0 ' dominoes logical circuits 600 separately.In such execution mode, gate 701 is designed to a logic sum gate, and input signal I1...I3 is done the logic OR computing, with supply output signal O1; Gate 703 is designed to a logic sum gate, and input signal I4...I6 is done the logic OR computing, with supply output signal O2; And gate 705 is designed to a logic sum gate, and signal O1 and O2 are done the logic OR computing, to produce output signal OUT.Thus, a large amount of no clocks return logic ' 0 ' domino logic gate can be combined or string stack togather, deal with the logical operation of a large amount of input signals, for example, realize a logic OR computing.

Fig. 8 is a calcspar, and diagram one no clock returns logic ' 0 ' domino logic gate 800, wherein the logical operation that realization mixes according to another embodiment of the present invention.No clock returns logic ' 0 ' domino logic gate 800 and comprises above-mentioned recurrence logic ' 0 ' dominoes circuit 305.These recurrence logic ' 0 ' dominoes circuit 305 couple one and return logic ' 0 ' estimation circuit 801 (in order to realize this recurrence logic ' 0 ' estimation circuit 301) and a recurrence logic ' 0 ' reset circuit 803 (in order to realize this recurrence logic ' 0 ' reset circuit 303).Return logic ' 0 ' estimation circuit 801 and comprise three N lane device NA, NB and NC, couple node 302 with drain electrode separately, and couple a via node 802 with source electrode separately.Return logic ' 0 ' estimation circuit 801 and also comprise two N lane device ND and NE, couple node 802 with drain electrode separately, and couple reference potential VSS with source electrode separately.N lane device NA...NE receives five input signal I1...I5 with grid respectively.In this embodiment, return logic ' 0 ' estimation circuit 801 and carry out a logical operation, make OUT=(I1|I2|I3) & (I4|I5), wherein, what symbol " | " was represented is the logic OR computing, and symbol " & " representative is logic and operation.One estimated state betides among the input signal I1...I3 any when having at least one to be high level among high level and input signal I4 and the I5.Return logic ' 0 ' reset circuit 803 and comprise two P lane device PA and PB, be serially connected with between the drain electrode and replacement node 306 of P lane device P1, and be coupled to node 310 with the drain electrode of P lane device P1.What specify is, P lane device PA couples the drain electrode of P lane device P1 with source electrode, and couples the source electrode of P lane device PB with drain electrode, and P lane device PB couples this replacement node 306 with drain electrode.Input signal I4 is supplied to the grid of P lane device PA to use, and input signal I5 is supplied to the grid of P lane device PB to use.In this embodiment, Reset Status only takes place when input signal I4 and I5 are all low level.Input signal I4 and I5 are for returning logic ' 0 ' signal; Then can be to return logic ' 0 ' signal but need not one as for input signal I1...I3 and be decided to be and return logic ' 0 ' signal.Though state recurrence signal is that expection is set, in some design, possibly be quite useful design in conjunction with non-state recurrence signal and state recurrence signal.Said non-state returns signal possibly meet some returns signal with respect to these states time conditions.For example, in one embodiment, it possibly be that corresponding states returns signal and sets or keep that non-state returns signal.

The operation that no clock returns logic ' 0 ' domino logic gate 800 generally meets sequential chart shown in Figure 5.In such embodiment, estimated state input signal I1...I3 eventually at least one at least one is set up during for high level for high level and input signal I4 and I5, said estimated state is in time point T1 initiation estimation incident.With reference to previous narration, respond said estimation incident, preliminary filling input/output signal PCHG transition is a low level, and then, output signal OUT transition is a high level, comes again, and returning logic ' 0 ' enable signal RT0E transition is low level; Said transition is interval one short delay respectively.In the interval that said estimated state is set up, the first status signal EVAL keeps high level.Reset Status is only set up when input signal I4 and I5 all are set at low level.Because this second status signal RESET will maintain low level when having any to be high level among input signal I4 and the I5, therefore, the second status signal RESET maintains low level during for high level at the first status signal EVAL.When the first status signal EVAL when time point T5 transition is low level, if input signal I4 and I5 are low level simultaneously, it is high level that the second status signal RESET just understands transition.At time point T5, if input signal I4 and I5 all transition be low level, but then the second status signal RESET transition is a high level, but the second status signal RESET also might maintain the low level time more of a specified duration.For example, if input signal I1...I3 all transition be low level and input signal I4 and I5 any be maintained high level, then the second status signal RESET when the first status signal EVAL transition is low level still not transition to high level.Treat input signal I4 and I5 according to return logic ' 0 ' operation be low level (for example) with reference to figure 5 time point T6 then the second status signal RESET transition be high level and return logic ' 0 ' reset circuit 803 and get into its Reset Status, to cause resetting event.Like previous institute narrating content, respond said resetting event, reset signal RST transition is a high level; Anti-phase reset signal RSTB transition is a low level; High level is returned in preliminary filling input/output signal PCHG transition, and exports signal OUT transition and return low level, and above-mentioned transition is interval one short delay separately.

It is one non-pair of arrangement embodiments that no clock returns logic ' 0 ' domino logic gate 800, and wherein returning logic ' 0 ' reset circuit 803 is not the two configuration designs that return logic ' 0 ' estimation circuit 801.In this embodiment, only there are a son set-input signal I4 and I5-to be supplied to this recurrence logic ' 0 ' reset circuit 803 among the input signal I1...I5.Yet; Since estimated state only set up input signal I4 and I5 at least one during for high level, therefore, when recurrence logic ' 0 ' estimation circuit 801 is its estimated state; Return logic ' 0 ' reset circuit 803 and must be in its isolation, can guarantee suitable operation.Particularly, when said estimation incident begins, return logic ' 0 ' reset circuit 803 and be in its isolation, and should 305 transitions of recurrence logic ' 0 ' dominoes circuit be its latch mode conducting P lane device P1.Reset signal RST is not subjected to any device decision current potential under said estimation condition.When input signal I4 and I5 are low level according to returning the equal transition of logic ' 0 ' operation, return logic ' 0 ' estimation circuit 801 and break away from its estimated state and return logic ' 0 ' circuit 803 and get into its Reset Status and cause a resetting event.Said resetting event makes these recurrence logic ' 0 ' dominoes circuit 305 transitions return its preset condition, makes not conducting of P lane device P1, and then drags down the level of reset signal RST, to prepare to meet next estimation incident.

The logical operation of no clock recurrence logic ' 0 ' domino logic gate 800 can be used for the associating gate structure of similar associating gate design 700.For example, gate 701 can be realized by one three input logic or door, and receiving inputted signal I1...I3 is to supply an output signal O1.Gate 703 can be realized by a dual input logic sum gate, to receive two input signal I4 and I5 to supply an output signal O2.Gate 705 can be realized by a dual input logical AND gate, so that signal O1 and O2 are made logic and operation.Thus, co-ordinative construction will realize logical operation (I1|I2|I3) & (I4|I5).In another kind of framework, also can provide the 3rd P lane device (not showing in the drawings) to be serially connected between node 310 and 306.Three P lane devices of serial connection are used for receiving inputted signal I1, I2 and I3 respectively.Resulting operation is equivalent; Even if; With respect to the state (I4 and I5) of two input signals, the state of three input signals (I1, I2 and I3) may make recurrence logic ' 0 ' dominoes circuit 305 return the spent time of preset condition slightly for a long time by the latch mode transition.

Fig. 9 is a block schematic diagram, and diagram one no clock returns logic ' 0 ' domino logic gate 900, wherein realizes a logical AND gate, returns logic ' 0 ' input signal I1...IM to M and carries out logic and operation.In such logical AND embodiment, each is to return logic ' 0 ' signal for input signal I1...IM.No clock returns logic ' 0 ' domino logic gate 900 and comprises said recurrence logic ' 0 ' dominoes circuit 305, couples to return logic ' a 0 ' estimation circuit 901 (realizing said recurrence logic ' 0 ' estimation circuit 301) and recurrence logic ' a 0 ' reset circuit 903 (realizing said recurrence logic ' 0 ' estimation circuit 303).Return logic ' 0 ' estimation circuit 901 and comprise M N lane device NA...NM, be serially connected with between preliminary filling input and output node 302 and the reference potential VSS.As shown in the figure, the drain electrode of N lane device NA couples node 302, and its source electrode couples the drain electrode of next N lane device in the serial, and follows this rule until afterbody N lane device NM, and the source electrode of N lane device NM is coupled reference potential VSS.As shown in the figure, N lane device NA...NM provides grid receiving inputted signal I1...IM separately.Accordingly, return logic ' 0 ' reset circuit 903 and comprise that M P lane device PA...PM is parallel between node 310 and the replacement node 306.Particularly, the source electrode of P lane device PA...PM couples node 310, and drain electrode couples replacement node 306.

No clock returns the embodiment that logic ' 0 ' domino logic gate 900 is another kind of two configuration designs.The operation that no clock returns logic ' 0 ' domino logic gate 900 generally is to meet the disclosed sequential chart of Fig. 5.In such embodiment, estimated state is to set up during all for high level at all input signal I1...IM, and at this moment, the total conducting of N lane device NA...NM is together moved preliminary filling input/output terminal PCHG to reference potential VSS.When any was low level among the input signal I1...IM, Reset Status was set up.In this execution mode, returning logic ' 0 ' estimation is two configuration designs with reset circuit 901 and 903 each other.According to various application, said gate can be designed to receive the input signal of multiple quantity.Yet as before returned the discussion of logic ' 0 ' domino logic gate 600 about no clock, in order to ensure the operation correctness, being serially connected in the quantity that returns the N lane device in logic ' 0 ' estimation circuit 901 can be limited in the specific quantity.

Associating gate design 700 as discussed previously, no clock return logic ' 0 ' domino logic gate 900 can adopt repeatedly technology of string, realizes the logic and operation of any amount of input signal with multiple logic and door.Gate 701,703 and 705 each can return logic ' 0 ' domino logic gate 900 with reference to no clock and be embodied as a logical AND gate.In one embodiment, gate 701 is designed to a logical AND gate, in order to input signal I1...I3 is made logic and operation, to produce signal O1; Gate 703 is designed to a logical AND gate, and I4...I6 does logic and operation to input signal, to produce signal O2; Gate 705 is designed to a logical AND gate, and signal O1 and O2 are made logic and operation, to produce output signal OUT.Thus, a plurality of no clocks return logic ' 0 ' domino logic gates can be combined or string stack togather, realizing certain logic computing-for example, logic and operation-to the processing of number of input signals.

Figure 10 is a calcspar, and another no clock of diagram returns logic ' 0 ' domino logic gate 1000, is used to realize a logical AND gate, returns logic ' 0 ' input signal I1...IM to M and makes logic and operation, and comprise a reset circuit 1003 of simplifying.It is similar with no clock recurrence logic ' 0 ' domino logic gate 900 haply that no clock returns logic ' 0 ' domino logic gate 1000, and wherein same element adopts same numbering.Relatively two circuit return logic ' 0 ' reset circuit 903 and change by 1003 realizations of a recurrence logic ' 0 ' reset circuit.In general the operation that no clock returns logic ' 0 ' domino logic gate 1000 also meets the disclosed sequential chart of Fig. 5.Return logic ' 0 ' reset circuit 1003 and only comprise a P lane device PA, the drain electrode that couples P lane device P1 with source electrode is in node 310, and couples replacement node 306 with drain electrode.Any is denoted as signal IX among the input signal I1...IM among the figure, can be supplied to the grid of P lane device PA.

Return logic ' 0 ' domino logic gate 900 with no clock and compare, it is identical that no clock returns the 1000 performed computings of logic ' 0 ' domino logic gate, but is to be designed to non-pair of configuration structure.The substantially similar no clock of operation that no clock returns logic ' 0 ' domino logic gate 1000 returns logic ' 0 ' domino logic gate 900, and difference is in its Reset Status only to be set up during for low level in input signal IX.When input signal I1...IM-comprised signal IX-all transition is high level, Reset Status was false, and the estimation incident takes place.When signal IX transition is a logic ' 0 ', said estimated state is false and said Reset Status is set up, and a resetting event is initiated, and makes these no clock recurrence logic ' 0 ' dominoes circuit 305 get back to its preset condition.The advantage that no clock returns logic ' 0 ' domino logic gate 1000 is recurrence logic ' 0 ' reset circuit simplified, wherein only realizes with a P lane device; Yet,, have the certain speed loss occurrence if signal IX returns zero level with the mode slow than other input signals.The advantage that no clock returns logic ' 0 ' domino logic gate 900 possibly speed reaction speed, and reason is, after the estimation incident, immediately speed took place when resetting event can any transition be zero level in input signal; Yet, can need complicated recurrence logic ' 0 ' reset circuit design.If one of said input signal IN must be the fastest recurrence logic ' 0 ' signal, it can be chosen as signal IX, to solve the reaction speed problem that no clock returns logic ' 0 ' domino logic gate 1000.

Sequential chart with reference to figure 5; Look back and adopt the no clock that returns logic ' 0 ' dominoes circuit 400 to return logic ' 0 ' domino logic gate 300; Wherein, Selected a plurality of or all input signals (look its particular design and decide) are when returning logic ' 0 ' and be operating as (or transition to) logic ' 0 ', and no clock recurrence logic ' 0 ' domino logic gate 300 is its initial preset state.Set up when input signal makes estimated state, Reset Status is for being false, and estimation incident generation.Under the state that estimated state is set up, Reset Status is maintained is false.When recurrence logic ' 0 ' input signal that is supplied to reset circuit reverted to its logic of propositions ' 0 ' state, said estimated state transition was for being false, and said thereafter Reset Status is set up.Reset finally is to take place according to returning logic ' 0 ' operation.Return logic ' 0 ' domino logic gate 600 about no clock, each takes place when all transition is a logic ' 0 ' resetting event at input signal I1...IM.Return logic ' 0 ' domino logic gate 800 about no clock, generation when resetting event is a logic ' 0 ' in the subclass of input signal I1...I5-be input signal I4 and I5-transition.Return logic ' 0 ' domino logic gate 900 about no clock, resetting event takes place when wherein any transition is a logic ' 0 ' at input signal I1...IM.Return logic ' 0 ' domino logic gate 1000 about no clock, resetting event in input signal selected one-be that signal IX-transition takes place when being logic ' 0 '.

Figure 11 is a block schematic diagram, and diagram one no clock returns logic ' 1 ' domino logic gate 1100, and a kind of recurrence logic ' 1 ' execution mode that returns domino logic gate 200 according to no clock status is realized.One or more input signal is designed to return logic ' 1 ' signal with the output signal that is produced, and the logic of propositions state that has is a logic ' 1 '.Power supply potential VSRC1 is designed to reference potential VSS, and the power supply potential VSRC2 current potential VDD that is designed to supply power, and the design that returns logic ' 0 ' domino logic gate 300 with no clock is opposite.State returns estimation circuit 201, state recurrence dominoes circuit 205 and state recurrence reset circuit 203 and is returned logic ' 1 ' dominoes circuit 1105 and 1103 realizations of a recurrence logic ' 1 ' reset circuit with a recurrence logic ' 1 ' estimation circuit 1101, respectively, and it returns ' 1 ' operational design according to a state.Possibly return logic ' 0 ' circuit because of its operation of exporting signal is regarded as separately though note that circuit 1101 and 1103, be still according to its input signal and recurrence logic ' 1 ' domino logic gate 1100 mass actions it is considered as returning logic ' 1 ' circuit.Aforesaid preset import out end PSET change by couple one in advance an in advance clear input/output terminal PCLR of clear node 1102 replace.No clock returns the output of logic ' 1 ' domino logic gate 1100 and sets a recurrence logic ' 1 ' output signal OUT at an output node 1108, and produces a reset signal RST at a replacement node 1106.State returns activation node 204 and returns 1104 realizations of logic ' 1 ' activation node by one, couples the grid of N lane device N1, returns enable circuit 207 with the realization state.N lane device N1 couples reference potential VSS and couples the second replacement node 1110 with source electrode with source electrode, and recurrence logic ' 1 ' reset circuit 1103 is coupled between replacement node 1110 and 1106.

Figure 12 is a block schematic diagram, and diagram one returns logic ' 1 ' dominoes circuit 1200, for returning a kind of execution mode of logic ' 1 ' dominoes circuit 1105.Return logic ' 1 ' dominoes circuit 1200 for returning the anti-phase design of logic ' 0 ' dominoes circuit 300; Wherein replace the power supply current potential VDD in the circuit 300 with reference potential VSS; Replace the reference potential VSS in the circuit 300 for electric potential VDD; Replace the N lane device in the circuit 300 with the P lane device; Replace the P lane device in the circuit 300 with the N lane device; And the mode of operation that makes each node all is the rp state (logic ' 0 ' state replaces to logic ' 1 ' state, and logic ' 1 ' state replaces with logic ' 0 ' state) of corresponding node in the circuit 300.In addition, the design of P passage in each inverter and N lane device and power supply potential all is the anti-phase design of circuit 300; Among the figure because performed be similarly the anti-phase computing, so the symbolic representation that it employing is identical.In advance clear node 1102 couples the input of inverter 1201, and couples the drain electrode of N lane device N2 and N3.The output of inverter 1201 couples output node 1108 and returns logic ' 1 ' output signal with supply, and also couples the grid of N lane device N3 and the input of inverter 1203.The output of inverter 1203 is coupled to node 1104 and returns logic ' 1 ' enable signal RT1E with supply, to put on the grid of P lane device P1.P lane device P1 couples power supply current potential VDD and couples replacement node 1106 with supply reset signal RST with drain electrode with source electrode.Reset signal RST is supplied to the input of inverter 1205, and the output of inverter 1205 is supplied an anti-phase reset signal RSTB.Reversed-phase output signal RSTB is supplied to the grid of N lane device N2, and the source electrode of this N lane device N2 couples reference potential VSS.Inverter 1201 is together formed half holding circuit 1202 with N lane device N3, and keeping in advance clear input/output terminal PCLR current potential is that the current potential that low level will be somebody's turn to do in advance clear input/output terminal PCLR until recurrence logic ' 1 ' estimation circuit 1101 draws high.P lane device P2 (corresponding N lane device N2 that returns in logic ' 0 ' the dominoes circuit 300) shown in the figure dotted line receives anti-phase reset signal RSTB with its grid, and couples node 1106 with drain electrode, and couples power supply current potential VDD with source electrode.In advance clear input/output terminal PCLR is initial to be low level clearly in advance, is high level so inverter 1201 is set output signal OUT, makes N lane device N3 conducting.Therefore N lane device N3 keeps in advance clear input/output terminal PCLR is low level.Because the initial condition of output signal OUT is a high level, inverter 1203 can be set and return logic ' 1 ' enable signal RT1E is low level, makes P lane device P1 conducting, and the P lane device P1 of conducting will draw high reset signal RST.The initial state that therefore inverter 1205 drags down anti-phase reset signal RSTB and N lane device N2 is not conducting.

With reference to Figure 11 and Figure 12; An estimation incident that is taken place when responding one or more input signal IN transition for any of one or more estimated state; Return the level that logic ' 1 ' estimation circuit 1101 draws high in advance clear input/output terminal PCLR, causing and returning 1200 transitions of logic ' 1 ' dominoes circuit is its latch mode.Particularly, inverter 1201 can drag down output signal OUT and make not conducting of N lane device N3.Inverter 1203 draws high the level that returns logic ' 1 ' enable signal RT1E, makes N lane device N1 conducting, and makes not conducting of P lane device P1.The N lane device N1 of conducting can couple node 1110 to reference potential VSS.It is high level that the P lane device P1 of not conducting will no longer limit reset signal RST.The estimated state of input signal IN can cause returning 1103 transitions of logic ' 1 ' reset circuit and be its isolation, and node 1106 and 1110 is isolated from each other.Thus, replacement node 1106 is temporarily isolated, and reset signal RST no longer is limited in particular state.Yet owing to do not have other devices to attempt to change the state of reset signal RST, reset signal RST is maintained high level.When input signal IN is in an estimated state, return logic ' 1 ' reset circuit 1103 and maintain its isolation.

Each is replied and is its preset state as the input signal IN that is supplied to this recurrence logic ' 1 ' reset circuit 1103; Return 1103 transitions of logic ' 1 ' reset circuit to its Reset Status; Cause a resetting event; Wherein, N lane device N1 and return logic ' 1 ' reset circuit 1103 and unite and move reset signal RST to low level.Inverter 1205 can be moved anti-phase reset signal RSTB to high level with conducting N lane device N2 thereupon.The N lane device N2 of conducting can be pulled down to preset value with the current potential of in advance clear input/output terminal PCLR.Please note; When each the input signal IN that is supplied to this recurrence logic ' 1 ' reset circuit 1103 revert to preset state; These input signals IN will no longer be an estimated state, therefore, return logic ' 1 ' estimation circuit 1101 and no longer in advance clear input/output terminal PCLR will be pulled in high level.Thus, N lane device N2 is able to once more in advance clear input/output terminal PCLR dragged down in advance clear state.If in advance clear input/output terminal PCLR transition is a high level, it is high level once more that inverter 1201 can be set output signal OUT, makes N lane device N3 conducting, and keeping in advance clear input/output terminal PCLR is low level.Inverter 1103 can drag down recurrence logic ' 1 ' enable signal RT1E, with conducting P lane device P1 and make not conducting of N lane device N1.Because not conducting of N lane device N1 returns logic ' 1 ' reset circuit 1103 and isolates with reference potential VSS, no longer the level with reset signal RST drags down.In addition, the conducting meeting of P lane device P1 draws high high level with reset signal RST, and inverter 1105 can be moved anti-phase reset signal RSTB to low level, makes not conducting of N lane device N2.Though it is low level that not conducting of N lane device N2, half holding circuit 1202 can be kept in advance clear input/output terminal PCLR current potential.Thus, return logic ' 1 ' dominoes circuit 1200 its preset condition of resetting back, meet estimation incident next time with preparation.

Figure 13 describes the operation that no clock returns logic ' 1 ' domino logic gate 1100 with a sequential chart, and what return wherein that logic ' 1 ' dominoes circuit 1105 are adopted is a kind of execution mode of recurrence logic ' 1 ' dominoes circuit 1200.The sequential chart of Figure 13 is fundamentally similar with the sequential chart of Fig. 5, except the difference of minority signal name and the level adjustment (with it anti-phase) of circuit signal.Specify; Compared to Fig. 5; Figure 13 replaces preliminary filling input/output signal PCHG with in advance clear input/output signal PCLR; Return logic ' 0 ' output signal OUT (RT0) to return logic ' 1 ' output signal OUT (RT1) replacement, and replace recurrence logic ' 0 ' enable signal RT0E to return logic ' 1 ' enable signal RT1E.The signal PCLR of Figure 13, OUT (RT1), RT1E, RST and RSTB are respectively the anti-phase of Fig. 5 signal PCHR, OUT (RT0), RT0E, RST and RSTB.In addition, the transition time has short delay basically equally.Compare with Fig. 5, Figure 13 also comprises the waveform of the first status signal EVAL and the second status signal RESET, and response class seemingly.In this embodiment, the first status signal EVAL is used for indicating the estimated state that returns logic ' 1 ' estimation circuit 1101, when estimated state is set up, is high level, and when estimated state is false, is low level.The second status signal RESET is used for indicating the Reset Status that returns logic ' 1 ' reset circuit 1103, when Reset Status is set up, is high level, and is low level when Reset Status is false.Said Reset Status can cause a resetting event, occurs over just when this recurrence logic ' 1 ' enable signal RT1E is high level after the estimation incident.

Figure 13 presents said signal EVAL, RESET, PCRL, OUT (RT1), RT1E, RST and RSTB with sequential chart.It only is the signal purposes that the transition that exists between each signal postpones, and is not accurate demonstration actual state.With reference to initial time point T0, the initial condition of the first status signal EVAL is a low level, shows that input signal IN is not in estimated state.In addition, based on Fig. 5 institute content of the discussions, the second status signal RESET is meaningless in time point T0.At time point T0, signal PCLR, OUT (RT1), RT1E, RST and RSTB are initially set logic ' 0 ', ' 1 ', ' 0 ', ' 1 ' and ' 0 ' respectively.

At the time point T1 that continues, input signal IN together gets into estimated state, and causing the first status signal EVAL transition is high level, and the second status signal RESET transition is a low level.Respond the high level state of the first status signal EVAL, return the time point T2 of logic ' 1 ' estimation circuit 1101 after a short delay and draw high in advance clear input/output terminal PCLR current potential, cause an estimation incident.Because the second status signal RESET is a low level, returns logic ' 1 ' reset circuit 1103 and be in its isolation.Respond the action of the signal transition of in advance clear input/output terminal PCLR to high level, the level that the connecting time point T3 of inverter 1201 after a short delay will export signal OUT drags down.Response drags down the output signal OUT of level, and the connecting time point T4 of inverter 1203 after a short delay draws high the level that returns logic ' 1 ' enable signal RT1E, with conducting N lane device N1, and makes not conducting of P lane device P1.Do not act on owing to return logic ' 1 ' reset circuit 1103, reset signal RST is not influenced by any device and maintains high level (perhaps, in the execution mode that design P lane device P2 is arranged, P2 maintains high level by the P lane device).The state that no clock returns logic ' 1 ' dominoes circuit 1200 is constant for holding during for high level in the first status signal EVAL.At the time point T5 that continues, one or more input signal IN change state, cause said estimated state to be false, and the corresponding transition of the first status signal EVAL are a low level.If be supplied to return logic ' 1 ' reset circuit 1103 input signal IN each all reply and be logic ' 1 ', then to be shown in time point T5 transition as 501 in dotted line be high level to the second status signal RESET.Yet about non-two configuration designs, the first status signal EVAL transition is that the low level and the second status signal RESET transition are to have a delay between the high level.Note that said estimated state is false because the first status signal EVAL is a low level, so return logic ' 1 ' estimation circuit 1101 no longer draws high in advance clear input/output terminal PCLR behind time point T5 current potential.The current potential of in advance clear input/output terminal PCLR can maintain high level until N lane device N2 effect, and its level is dragged down.

At time point T5 or the time point T6 that continues, being supplied to the input signal IN transition that returns logic ' 1 ' reset circuit 1103 is high level, and to begin to return the Reset Status of logic ' 1 ' reset circuit 1103, making the second status signal RESET transition is high level.Recurrence logic ' 1 ' the reset circuit 1103 time point T7s of associating N lane device N1 after a short delay drag down the level of reset signal RST, with an initial resetting event.Inverter 1205 is responded aforesaid operations, and the time point T8 after a short delay draws high the level of anti-phase reset signal RSTB.Transition is the anti-phase reset signal RSTB meeting conducting N lane device N2 of high level, and the time point T9 after a short delay drags down the preparatory level of input/output terminal PCLR clearly.When the level reduction of in advance clear input/output terminal PCLR, it is high level that the time point T10 of inverter 1201 after a short delay sets output signal OUT.Transition is that the output signal OUT of high level can make N lane device N3 conducting, and the current potential that causes half holding circuit 1202 to be maintained in advance clear input/output terminal PCLR is that low level is drawn high its level until estimation interval after a while.The level that the time point T11 of inverter 1203 after a short delay will return logic ' 1 ' enable signal RT1E drags down.Recurrence logic ' 1 ' the enable signal RT1E of low level state makes P lane device P1 conducting, and makes not conducting of N lane device N1.Because not conducting of N lane device N1 returns the level that logic ' 1 ' reset circuit 1103 no longer drags down reset signal RST.The time point T12 of P lane device P1 after a short delay of conducting retracts high level with reset signal RST.The time point T13 of inverter 1205 after short delay drags down the level of anti-phase reset signal RSTB, makes N lane device N2 no longer drag down the level of in advance clear input/output terminal PCLR.At this moment, to be responsible for keeping level of this in advance clear input/output terminal PCLR be low level to half holding circuit 1202.At the time point T14 that follows after time point T13, said signal is got back to initial preset state.Therefore; Return logic ' 1 ' estimation circuit 1101 and N lane device N1 and all be in its preset state, return logic ' 1 ' dominoes circuit 1105 and return its preset condition, in addition; Suppose that each is high level into signal IN, return logic ' 1 ' reset circuit 1103 and be in its Reset Status.Generally speaking, the estimated state of input signal IN can cause an estimation incident, and causing output signal OUT transition is low level, and the resetting event that continues of activation.The Reset Status of input signal IN can cause and return logic ' 1 ' reset circuit 1103 initiations one resetting event, and makes no clock return logic ' 1 ' domino logic gate 1100 its initial conditions of recurrence, to meet next estimation interval.

Content of the discussions as Fig. 5; To be high level return logic ' 1 ' enable signal RTE1 transition until time point T11-to the second status signal RESET is low level-return logic ' 1 ' gate and return its initial condition to guarantee not have clock; Thereafter, the second status signal RESET as shown is meaningless.Please note; When reset signal RST is pulled to low level at time point T7, be low level if Reset Status is false the second status signal RESET dragged down, reset signal RST still maintains low level; Reason is that P lane device P1 still is not conducting, the unable reset signal RST that influences.Therefore; Though it is low level until returning logic ' 1 ' enable signal RT1E transition that Reset Status should be kept establishment; But, still can not influence correct circuit operation if input signal moves in this way after time point T7 and time point T11 drags down the second status signal RESET before.In case returning logic ' 1 ' enable signal RT1E is low level, P lane device P1 conducting, and any insignificant transition of input signal IN can not influence the integrated circuit state behind time point T11.

Figure 14 is a block schematic diagram, and diagram one no clock returns logic ' 1 ' domino logic gate 1400, is used to realize a logic OR computing, and M input signal I1...IM done the logic OR computing.No clock returns logic ' 1 ' domino logic gate 1400 and comprises recurrence logic ' 1 ' dominoes circuit 1105.Circuit 1105 couples one and returns logic ' a 1 ' estimation circuit 1401 (being used for realizing aforementioned recurrence logic ' 1 ' estimation circuit 1101) and recurrence logic ' a 1 ' reset circuit 1403 (being used for realizing aforementioned recurrence logic ' 1 ' reset circuit 1103).Return logic ' 1 ' estimation circuit 1401 and comprise M P lane device PA...PM, couple node 1102 with drain electrode separately, and couple power supply current potential VDD with source electrode separately.The P lane device PA...PM provide a grid separately, with receiving inputted signal I1...IM one of them.In similar fashion, return logic ' 1 ' reset circuit 1403 and comprise M N lane device NA...NM, be serially connected with between node 1110 and the replacement node 1106.As shown in the figure, the N lane device NA of the first order couples the node 1110 in the drain electrode of N lane device N1 with source electrode, and couples the source electrode of next stage N lane device with drain electrode; Follow said rule until the N of afterbody lane device NM.The drain electrode of afterbody N lane device NM couples node 1106.The N lane device NA...NM provide a grid separately, with mode receiving inputted signal I1...IM as shown in the figure one of them.Although only indicate wherein two device (NA of said N lane device among the figure; NM), wherein two device (PA of P lane device; PM) and only show input signal I1 and IM; In fact; According to disclosed rule; Omit the part of drawing and to comprise any amount of said device and coherent signal (for example, being supplied to the input signal I2 of the grid of N passage and P lane device NB and PB).

It is a kind of two configuration design that no clock returns logic ' 1 ' domino logic gate 1400, wherein, returns logic ' 1 ' reset circuit 1403 for returning two configuration designs of logic ' 1 ' estimation circuit 1401.In addition, in two configurations design, being supplied to what return logic ' 1 ' estimation circuit 1401 and recurrence logic ' 1 ' reset circuit 1403 all is identical input signal I1...IM.The operation that no clock returns logic ' 1 ' domino logic gate 1400 meets sequential shown in Figure 13 usually.In this embodiment, when input signal I1...IM all was in logic ' 1 ' according to the operation that returns logic ' 1 ', the first status signal EVAL was a low level, and the second status signal RESET is a high level.When any transition was low level among the input signal I1...IM, estimated state was set up, and Reset Status is false, so the first status signal EVAL is that the high level and the second status signal RESET are low level.Because circuit 1401 and 1403 is two configuration designs, along with the transition of input signal IN is switched, the state of the first status signal EVAL and the second status signal RESET and then switches, and is maintained the other side's anti-phase.Respond the estimation incident that the low level transition of any is caused among the input signal IN; In advance clear input/output terminal PCLR transition is a high level; And output signal OUT transition after short delay is a low level, and recurrence logic ' 1 ' enable signal RT1E transition after another section short delay is that high level is with activation one resetting event.When input signal I1...IM returns logic ' 1 ' according to returning logic ' 1 ' operation transition totally; Return logic ' 1 ' reset circuit 1403 and cause a resetting event; It is low level that ream weight is put signal RST transition; Anti-phase reset signal RSTB transition is a high level; In advance the level of clear input/output terminal PCLR retracts low level, and output signal OUT such as aforementioned content draw high back high level.

In some design, be serially connected in the quantity that returns the N lane device in logic ' 1 ' reset circuit 1403 and possibly be limited in below the specified quantitative, to guarantee the circuit normal operation.For example, in one embodiment, be serially connected on the quantity of N lane device of 1106 of reference potential VSS and replacement nodes and be limited to 4, therefore, the quantity of input signal can be restricted to 3 (being that M is 3).With reference to figure 7, gate 701,703 and 705 can return logic ' 1 ' logic sum gate by one respectively and realize, what each gate adopted is that no clock returns logic ' 1 ' domino logic gate 1400 technology.Among this embodiment, gate 701 is designed to a logic sum gate, carries out the logic OR computing to returning logic ' 1 ' input signal I1...I3, returns logic ' 1 ' signal O1 with supply.Gate 703 is designed to one and returns logic ' 1 ' logic sum gate, carries out the logic OR computing to returning logic ' 1 ' input signal I4...I6, returns logic ' 1 ' signal O2 to supply one.Gate 705 is designed to one and returns logic ' 1 ' logic sum gate, and signal O1 and O2 are carried out the logic OR computing, to be supplied as the output signal OUT that returns logic ' 1 ' signal.Thus, a plurality of no clocks return logic ' 1 ' domino logic gates can be combined or string stack togather so that a large amount of recurrence logic ' 1 ' input signals is carried out specific logical operation, for example, the logic OR computing.

Figure 15 is a block schematic diagram, and diagram one no clock returns logic ' 1 ' domino logic gate 1500, wherein realizes diversified logical operation according to another execution mode.No clock returns logic ' 1 ' domino logic gate 1500 and comprises recurrence logic ' 1 ' dominoes circuit 1105.Circuit 1105 couples and returns logic ' 1 ' estimation circuit 1501 (in order to realize returning logic ' 1 ' estimation circuit 1101) and a recurrence logic ' 1 ' reset circuit 1503 (in order to realize returning logic ' 1 ' reset circuit 1103).The identical basically no clock of design that no clock returns logic ' 1 ' domino logic gate 1500 returns logic ' 0 ' domino logic gate 800, and difference is specially to returning the anti-phase design that logic ' 1 ' operation is done.It is described; Compared to gate 800; Gate 1500 replaces reference potential VSS for electric potential VDD; Replace power supply current potential VDD with reference potential VSS; Replace the P lane device with the N lane device, replace the N lane device, make input signal I4 and I5 adopt and return logic ' 1 ' mode of operation but not recurrence logic ' 0 ' mode of operation with the P lane device; With signal condition anti-phase design, and make input signal I1...I3 for returning logic ' 1 ' or non-recurrence logic ' 1 ' signal.Aforementioned nodes 302,304,306,308 and 310 replaces with similar node 1102,1104,1106,1108 and 1110 respectively, and the mode of scheming with similar 11...14 realizes similar computing.The operation that no clock returns logic ' 1 ' domino logic gate 1500 generally meets the disclosed sequential chart of Figure 13.No clock return logic ' 1 ' domino logic gate 1500 carry out a logical operation OUT=～((& of～I1|～I2|～I3) (～I4|～I5)), wherein, symbol "～" representative be logical inversion.

Similar no clock returns logic ' 0 ' domino logic gate 800; No clock returns another execution mode that logic ' 1 ' domino logic gate 1500 is non-two configuration designs; Wherein, returning logic ' 1 ' reset circuit 1503 is not the two configuration designs that return logic ' 1 ' estimation circuit 1501.Only there are one subclass-input signal I4 and I5-to be supplied among the input signal I1...I5 and return logic ' 1 ' reset circuit 1503.Since when estimated state is set up input signal I4 and I5 one of them must be low level, so recurrence logic ' 1 ' reset circuit 1503 is its isolation.As long as returning logic ' 1 ' estimation circuit 1501 be estimated state, return logic ' 1 ' reset circuit 1503 and must be in of the aforementioned manner normal running of its isolation to guarantee with similar no clock recurrence logic ' 0 ' domino logic gate 800.In addition, no clock returns logic ' 1 ' domino logic gate 1500 and can adopt a string repeatedly gate of the technology realization that is similar to associating gate design 700.In one embodiment, the 3rd N lane device (show in the drawings) makes an addition to string between node 1110 and 1106 and changes in the device, N lane device receiving inputted signal I1, I2 and I3 that three strings are changed.What above-mentioned correction realized is the logical operation of equivalence; But; Return the spent time of preset condition about these recurrence logic ' 1 ' dominoes circuit 1105 from latching the state transition, the situation of three input signals (I1...I3) can be consuming time than the situation of two input signals (I4 and I5).

Figure 16 is a block schematic diagram, and diagram one no clock returns logic ' 1 ' domino logic gate 1600, is a logical AND gate, returns logic ' 1 ' input signal I1...IM to M and carries out logic and operation.No clock returns logic ' 1 ' domino logic gate 1600 and comprises that one returns logic ' 1 ' dominoes circuit 1105.Circuit 1105 couples one and returns logic ' a 1 ' estimation circuit 1601 (being used to realize aforementioned recurrence logic ' 1 ' estimation circuit 1101) and recurrence logic ' a 1 ' reset circuit 1603 (being used to realize aforementioned recurrence logic ' 1 ' reset circuit 1103).The substantially similar no clock of design that no clock returns logic ' 1 ' domino logic gate 1600 returns logic ' 0 ' domino logic gate 900, and difference is that domino logic gate 1600 is according to returning the distortion that logic ' 1 ' operation has been done.Be noted that; Compare with domino logic gate 900; Domino logic gate 1600 replaces reference potential VSS for electric potential VDD; And replace power supply current potential VDD with reference potential VSS; Replace the P lane device with the N lane device, replace the N lane device, make input signal I1...I5 adopt and return logic ' 1 ' design but not ' 0 ' design of recurrence logic with the P lane device; Order output signal OUT designs for recurrence logic ' 1 ' but not returns logic ' 0 ' design, and makes signal condition design for anti-phase.Node 302,304,306,308 and 310 can be replaced by similar node 1102,1104,1106,1108 and 1110 respectively, to be implemented in the equal computing that 11...14 figure is discussed.

No clock returns another execution mode that logic ' 1 ' domino logic gate 1600 is two configuration designs.The operation that no clock returns logic ' 1 ' domino logic gate 1600 generally meets sequential chart shown in Figure 13.In this embodiment, estimated state only is set at low level at input signal I1...IM totally and sets up, and makes the total conducting of P lane device PA...PM, makes a concerted effort to move the preparatory level of input/output terminal PCLR clearly to power supply current potential VDD.Set up when Reset Status can any be for high level in input signal I1...IM.In such execution mode, returning logic ' 1 ' estimation and reset circuit 1601 and 1603 is two configuration designs each other.According to various demands, institute's designed circuit can be accepted the input signal of requirement.Return the previous discussion of logic ' 1 ' domino logic gate 1400 with reference to no clock, similarly, be serially connected in the quantity that returns the interior P lane device of logic ' 1 ' estimation circuit 1601 and possibly be limited in the specific quantity, to guarantee the circuit normal running.Consult Fig. 7, gate 701,703 and 705 can adopt no clock to return one of logic ' 1 ' domino logic gate 1600 technology separately and return the realization of logic ' 1 ' logical AND gate.Thus, several can not had clock and return that logic ' 1 ' domino logic gate combines or string stacks togather, a large amount of input signals is carried out the logic and operation of specific logical operation-for example.

Figure 17 is a block schematic diagram, and diagram one no clock returns logic ' 1 ' domino logic gate 1700, is a logical AND gate, and M input signal I1...IM carried out logic and operation, wherein adopts the reset circuit of simplifying 1703.No clock returns logic ' 1 ' domino logic gate 1700 substantially similar no clocks and returns logic ' 1 ' domino logic gate 1600; Wherein, Same element adopts same numbering, changes by returning 1703 replacements of logic ' 1 ' reset circuit and return logic ' 1 ' reset circuit 1603.No clock returns logic ' 1 ' domino logic gate 1700 and generally meets sequential chart shown in Figure 13.Return logic ' 1 ' reset circuit 1703 and only have a N lane device NA, the drain electrode that couples N lane device N1 with source electrode is in node 1110, and couples replacement node 1106 with drain electrode.Input signal I1...IM wherein any-be generally denoted as the grid that IX-will be supplied to N lane device NA.

The computing that no clock returns logic ' 1 ' domino logic gate 1700 returns 1600 equivalences of logic ' 0 ' domino logic gate with no clock, and difference is that domino logic gate 1700 is non-two configuration design implementation modes.The substantially similar no clock of operation that no clock returns logic ' 1 ' domino logic gate 1700 returns logic ' 1 ' domino logic gate 1600, and it is that high level is just set up at input signal IX only that difference is in Reset Status.When input signal I1...IM-comprise input signal IX-each all transition be low level, Reset Status is false, and the estimation incident takes place.When input signal IX transition is a logic ' 0 ', estimated state is false, and Reset Status sets up, and causes a resetting event and makes no clock return logic ' 1 ' dominoes circuit 1105 its preset condition of recurrence.The advantage that no clock returns logic ' 1 ' domino logic gate 1700 is that it returns logic ' 1 ' reset circuit and simplifies; Only there is a N lane device to be contained in wherein; Yet, slow if the speed of logic ' 1 ' is returned in input signal IX transition than other input signals, have the reaction speed problem.The advantage that no clock returns logic ' 1 ' domino logic gate 1600 is to have reaction speed faster; After reason is the estimation incident; In case it is logic ' 1 ' that any transition is arranged in the input signal, promptly can cause resetting event, cost is that the design meeting of recurrence logic ' 1 ' reset circuit is complicated.The speed issue of domino logic gate 1700 can be avoided by following mode: make among the input signal IN, transition is that the input signal of logic ' 1 ' is said input signal IX the most fast.

Look back no clock and return logic ' 1 ' domino logic gate 1100; Recurrence logic ' 1 ' the dominoes circuit 1200 according to Figure 13 sequential chart operation are wherein adopted in order, and no clock returns logic ' 1 ' domino logic gate 1100 and is in (or transition is arrived) initially preset state at input signal when logic ' 1 ' operation is in (or transition to) logic ' 1 ' according to returning.Set up when input signal makes estimated state, Reset Status is false and an estimation incident is initiated.When estimated state was set up, Reset Status is kept was false.After estimated state was set up, if when being supplied to the input signal transition of reset circuit to return its logic of propositions ' 1 ' state, Reset Status was set up.Reset and finally take place according to returning logic ' 1 ' operation.Returning logic ' 1 ' domino logic gate 1400 with no clock is example, and resetting event betides the equal transition of each input signal I1...IM when returning logic ' 1 '.Returning logic ' 1 ' domino logic gate 1500 with no clock is example, when one subclass-input signal I4 and the I5-transition that resetting event betides input signal I1...I5 is logic ' 1 '.Returning logic ' 1 ' domino logic gate 1600 with no clock is example, and resetting event betides among the input signal I1...IM any transition when returning logic ' 1 '.Returning logic ' 1 ' domino logic gate 1700 with no clock be example, and resetting event betides this signal of selecting in the input signal-be referred to as input signal IX-transition when being logic ' 1 '.

Though several preferred implementations of the present invention below are detailed as possible, still have other execution modes or distortion existence.For example, foregoing circuit can anyly comprise that other suitable scheme of logic device or circuit and so on realize.Any amount of computing of the logical circuit of being introduced can be realized by similar techniques in software or firmware or the integrating device.Said circuit can comprise the anti-phase device, to carry out positive or inverted logic or other technology that signal can be reversed.The circuit computing that disclosed technology adopts can be numeral, binary bit byte or character, and those skilled in the art know, and uses about the numeral or the binary circuit of any bit quantity.Those skilled in the art perhaps can be the basis with disclosed notion of foregoing and embodiment, design or adjust all the other structures, under the prerequisite of spirit of the present invention, according to the defined scope of following request terms, realize the effect identical with the present invention.

Claims (60)

1. a no clock status returns domino logic gate, comprising:

A plurality of nodes; Be designed to separately switch at one first state and one second state; Preset node, an output node, an activation node and one first and one second replacement node comprising a plurality of input nodes; Wherein, Above-mentioned a plurality of input node comprises that separately a state returns node; After being set at above-mentioned first state, returning operation according to state and return above-mentioned second state;

One dominoes circuit; Have a preset condition and a latch mode; When this dominoes circuit is in this preset condition; This dominoes circuit is set this and is preset node and this activation node to above-mentioned first state and set this output node and this first replacement node above-mentioned second state extremely; When this presets node by transition to this second state; This dominoes circuit switches to this latch mode; Make this output node transition to above-mentioned first state and this activation node of transition to above-mentioned second state; When this first replacement node during by transition to above-mentioned first state, this dominoes circuit this preset condition of resetting back;

One estimation circuit, when said input node was in any of at least one estimated state, this preset node to above-mentioned second state transition, and when this input node is not above-mentioned estimated state, did not interfere this to preset the level of node;

One activation circuit, when this activation node is in this second state this second replacement node of transition to above-mentioned first state, otherwise, do not interfere the level of this second replacement node; And

One replacement current potential; When said input signal is not any of above-mentioned at least one estimated state; Couple this first replacement node and this second replacement node, and this first replacement node is isolated this second replacement node when being any of above-mentioned at least one estimated state in this input signal.

2. no clock status as claimed in claim 1 returns domino logic gate, and wherein this estimation circuit and this reset circuit are two configuration designs each other.

3. no clock status as claimed in claim 1 returns domino logic gate, and wherein this estimation circuit is carried out the logic OR computing to above-mentioned a plurality of input nodes.

4. no clock status as claimed in claim 1 returns domino logic gate, and wherein this estimation circuit is carried out logic and operation to above-mentioned a plurality of input nodes.

5. no clock status as claimed in claim 1 returns domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 0 ' nodes; Wherein, Above-mentioned a plurality of input node is designed to switch at a logic ' 0 ' state and a logic ' 1 ' state separately, and above-mentioned each leisure of a plurality of input signal is set to logic ' 1 ' back transition and returns logic ' 0 ';

This presets node and comprises a precharged node, and this dominoes circuit comprises that one returns logic ' 0 ' dominoes circuit;

When this dominoes circuit is this preset condition; This dominoes circuit set this precharged node and this activation node to logic ' 1 ' and set this output node and this first replacement node to logic ' 0 '; When this dominoes circuit is this latch mode; This this output node of dominoes circuit transition is that logic ' 1 ' and this activation node of transition are logic ' 0 '; When this first replacement node transition to logic during ' 1, this dominoes circuit this preset condition of resetting back;

When above-mentioned a plurality of input nodes are any one of above-mentioned at least one estimated state; This this precharged node of estimation circuit transition is to logic ' 0 '; When above-mentioned a plurality of input nodes were not any one of above-mentioned at least one estimated state, this estimation circuit did not influence this and presets node; And

When this activation node was logic ' 0, this second replacement node of this enable circuit transition was to logic ' 1 ', otherwise this enable circuit does not influence this second replacement node.

6. no clock status as claimed in claim 1 returns domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 1 ' nodes, has a logic ' 1 ' state and a logic ' 0 ' state separately, and wherein, above-mentioned a plurality of each leisure of input node are set at logic ' 0 ' back recurrence and are logic ' 1 ';

This presets node and comprises an in advance clear node, and this dominoes circuit comprises that one returns logic ' 1 ' dominoes circuit;

When this dominoes circuit is in this preset condition; This dominoes circuit set should in advance clear node and this activation node to logic ' 0 ' and set this output node and this first replacement node to logic ' 1 '; When this dominoes circuit is in this latch mode; This this output node of dominoes circuit transition to logic ' 0 ' and this activation node to logic ' 1 ' of transition; When this first replacement node transition is logic ' 0 ', this dominoes circuit this preset condition of resetting back;

When above-mentioned a plurality of input nodes form any of above-mentioned at least one estimated state; In advance clear node to logic ' 1 ' is somebody's turn to do in this estimation circuit transition; And when above-mentioned a plurality of input nodes did not form any of above-mentioned at least one estimated state, this estimation circuit did not influence this and presets node; And

When this activation node was logic ' 1 ', this second replacement node of this enable circuit transition was to logic ' 0 ', otherwise this enable circuit does not influence this second replacement node.

7. no clock status as claimed in claim 1 returns domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 0 ' input nodes;

Should comprise a precharged node by preset node;

This estimation circuit comprises a plurality of N lane devices, couples this precharged node, couples a reference potential and couple this corresponding in above-mentioned a plurality of input node input node with grid with source electrode with drain electrode separately;

This enable circuit comprises one the one P lane device, couples this power supply current potential with source electrode, couples this second replacement node with drain electrode, and couples this activation node with grid; And

This reset circuit comprises a plurality of the 2nd P lane devices, be serially connected with this first and this second replacement node between, couple in above-mentioned a plurality of input node this corresponding input node with grid separately.

8. no clock status as claimed in claim 1 returns domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 0 ' input nodes;

This presets node and comprises a precharged node;

This estimation circuit comprises a plurality of N lane devices, is serially connected with between this precharged node and this reference potential, couples this corresponding in above-mentioned a plurality of input node input node with grid separately;

This enable circuit comprises one the one P lane device, couples this power supply potential with source electrode, couples this second replacement node with drain electrode, and couples this activation node with grid; And

This reset circuit comprises a plurality of the 2nd P lane devices, couples this second replacement node, couples this first replacement node and couple this corresponding in above-mentioned a plurality of input node input node with grid with drain electrode with source electrode separately.

9. no clock status as claimed in claim 1 returns domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 0 ' input nodes;

This presets node and comprises a precharged node;

This estimation circuit comprises a plurality of N lane devices, is serially connected with between this precharged node and this reference potential, couples this corresponding in above-mentioned a plurality of input node input node with grid separately;

This activation node comprises one the one P lane device, couples this power supply current potential with source electrode, couples this second replacement node with drain electrode, and couples this activation node with grid; And

This reset circuit comprises one the 2nd P lane device, couples this second replacement node with source electrode, couples this first replacement node with drain electrode, and couples one of them input node of above-mentioned a plurality of input node with grid.

10. no clock status as claimed in claim 1 returns domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 1 ' input nodes;

This presets node and comprises an in advance clear node;

This estimation circuit comprises a plurality of P lane devices, couples this in advance clear node, couples this power supply current potential and couple this corresponding in above-mentioned a plurality of input node input node with grid with source electrode with drain electrode separately;

This enable circuit comprises one the one N lane device, couples this reference potential with source electrode, couples this second replacement node with drain electrode, and couples this activation node with grid; And

This reset circuit comprises a plurality of the 2nd N lane devices, be serially connected with this first and this second replacement node between, couple in above-mentioned a plurality of input node this corresponding input node with grid separately.

11. no clock status as claimed in claim 1 returns domino logic gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 1 ' input nodes;

Should comprise an in advance clear node by preset node;

This estimation circuit comprises a plurality of P lane devices, is serially connected with between this in advance clear node and this power supply current potential, couples this corresponding in above-mentioned a plurality of input node input node with grid separately;

This enable circuit comprises one the one N lane device, couples this reference potential with source electrode, couples this second replacement node with drain electrode, and couples this activation node with grid; And

This reset circuit comprises a plurality of the 2nd N lane devices, couples this second replacement node with source electrode separately, couples this first replacement node with drain electrode, and couples this corresponding in above-mentioned a plurality of input node input node with grid.

12. no clock status as claimed in claim 1 returns gate, wherein:

Above-mentioned a plurality of input node comprises a plurality of recurrence logic ' 1 ' input nodes;

Should comprise an in advance clear node by preset node;

This estimation circuit comprises a plurality of P lane devices, is serially connected with between this in advance clear node and this power supply current potential, couples this corresponding in above-mentioned a plurality of input node input node with grid separately;

This enable circuit comprises one the one N lane device, couples this reference potential with source electrode, couples this second replacement node with drain electrode, and couples this activation node with grid; And

This replacement current potential comprises one the 2nd N lane device, couples this second replacement node with source electrode, couples this first replacement node with drain electrode, and couples one of them input node of above-mentioned a plurality of input nodes with grid.

13. an integrated circuit comprises:

One first logic; Supply a plurality of states and return signal; Each above-mentioned state returns Design of Signal and switches at one first state and one second state; Above-mentioned a plurality of state returns signal, and each can return operation according to state and be set at above-mentioned second state by this first logic after be set at above-mentioned first state;

One no clock status returns domino logic gate, receive above-mentioned a plurality of state and return signal, and this no clock status recurrence domino logic gate comprises:

One presets node, an activation node, an output node and one first and one second replacement node, is designed to separately switch at above-mentioned first and second state;

One dominoes circuit; Have a preset condition and a latch mode; Wherein, When this dominoes circuit is in this preset condition; This dominoes circuit is set this and is preset node and this activation node to above-mentioned first state; And set this output node and this first replacement node to above-mentioned second state; When this presets node by transition to this second state; This dominoes circuit switches to this latch mode; Make this output node transition to above-mentioned first state; And this activation node of transition to above-mentioned second state; When this first replacement node transition to above-mentioned first state, this dominoes circuit this preset condition of resetting back;

One estimation circuit; Above-mentioned a plurality of states return signals be at least one estimated state any the time; This presets node to above-mentioned second state transition, and in above-mentioned a plurality of states return signals be not in above-mentioned at least one estimated state any the time, do not influence this and preset node;

One activation circuit, when this activation node is above-mentioned second state, this second replacement node of transition to above-mentioned first state, otherwise, do not influence this second replacement node; And

One reset circuit; When above-mentioned a plurality of states recurrence signals are not any of above-mentioned at least one estimated state; Couple this first replacement node to this second replacement node; And when above-mentioned a plurality of states recurrence signals are any of above-mentioned at least one estimated state, this first replacement node is isolated this second replacement node.

14. integrated circuit as claimed in claim 13; Wherein this first logic is supplied a plurality of recurrence logic ' 0 ' signals; Above-mentioned first state is that logic ' 1 ' and above-mentioned second state are logic ' 0 ', and this no clock status recurrence domino logic gate comprises that a no clock returns logic ' 0 ' domino logic gate.

15. integrated circuit as claimed in claim 13; Wherein this first logic is supplied a plurality of persistent state ' 1 ' signals; Above-mentioned first state is that logic ' 0 ' and above-mentioned second state are logic ' 1 ', and this no clock status recurrence domino logic gate comprises that a no clock returns logic ' 1 ' domino logic gate.

16. integrated circuit as claimed in claim 13, wherein this no clock status recurrence domino logic gate comprises that string stacks a plurality of no clock status recurrence domino logic gate of meter.

17. the method for estimation one logical operation comprises:

Receive a plurality of states and return input signal, said state returns input signal and is designed to separately after setting one first state for, return operation recurrence one second state according to state;

Supply has a dominoes circuit of a preset condition and a latch mode; When this dominoes circuit is this preset condition; Node is preset in this dominoes circuit setting one and an activation node is above-mentioned first state; And setting an output node and a replacement node is above-mentioned second state; When this presets node by transition to above-mentioned second state; This dominoes circuit switches to this this output node of latch mode transition to above-mentioned first state and this activation node of transition to above-mentioned second state; When this replacement node transition to above-mentioned first state, this dominoes circuit this preset condition of resetting back;

Estimate that above-mentioned a plurality of state returns input signal, wherein in above-mentioned a plurality of states return input signals at least one estimated state any the time transition this preset node to above-mentioned second state, to switch this dominoes circuit to this latch mode; And

This enable signal be above-mentioned second state and above-mentioned a plurality of state return input signal in above-mentioned a plurality of estimated state any the time, transition should replacement node to this first state, with this dominoes circuit of resetting to this preset condition.

18. method as claimed in claim 17, wherein, on switch this dominoes circuit when being set forth in this preset node transition to above-mentioned second state and comprise for the step of this latch mode with this activation node of transition to this second state:

One replacement condition of this dominoes circuit of activation.

19. method as claimed in claim 17; The step that the above-mentioned a plurality of states of wherein above-mentioned estimation return input signals comprise carry out a logic OR computing when returning in the input signals at least one transition to above-mentioned first state in above-mentioned a plurality of states transition this preset node to above-mentioned second state, and the method for wherein above-mentioned this dominoes circuit of replacement be included in this activation node when being in this second state and above-mentioned a plurality of state and returning input signal and be above-mentioned second state transition should the replacement node to this first state.

20. method as claimed in claim 17; The step that the above-mentioned a plurality of states of wherein above-mentioned estimation return input signals comprise carry out a logic and operation when returning the total transition of input signal to above-mentioned first state in above-mentioned a plurality of states transition this preset node to above-mentioned second state, and the step of wherein above-mentioned this dominoes circuit of replacement be included in this activation node be above-mentioned second state and above-mentioned a plurality of state when returning in the input signal at least one input signal and returning above-mentioned second state transition should the replacement node to this first state.

21. a no clock status returns gate, comprising:

A plurality of nodes; Switch on one first state and one second state separately; Preset node, an output node, an activation node and one first and one second replacement node comprising a plurality of input nodes; At least one comprises that a state returns node in above-mentioned a plurality of input node, after setting above-mentioned first state for, returns the operation transition according to state and returns above-mentioned second state;

One dominoes circuit; Have a preset condition and a latch mode; When this dominoes circuit is this preset condition; This dominoes circuit is set this and is preset node and this activation node is above-mentioned first state; And set this output node and this first replacement node is above-mentioned second state; When this when to preset the node transition be above-mentioned second state; This dominoes circuit switches to this latch mode; With this output node of transition is above-mentioned first state; And this activation node of transition is above-mentioned first state; When above-mentioned first state is returned in this first replacement node transition, this dominoes circuit this preset condition of resetting back;

One estimation circuit; When above-mentioned a plurality of input nodes are any of at least one estimated state; Transition this to preset node be above-mentioned second state, and when above-mentioned a plurality of input nodes are not any of above-mentioned at least one estimated state, do not influence this and preset node;

One activation circuit, this activation node when being above-mentioned second state this second replacement node of transition be above-mentioned first state, and do not influence this second replacement node during for above-mentioned second state in this activation node; And

One reset circuit; Above-mentioned a plurality of input nodes for above-mentioned at least one estimated state any the time couple this first replacement node to this second replacement node, and in above-mentioned a plurality of input nodes be above-mentioned at least one estimated state any the time this first replacement node isolated this second replacement node.

22. no clock status as claimed in claim 21 returns domino logic gate, wherein this estimation circuit and this reset circuit are non-two configuration design each other.

23. no clock status as claimed in claim 21 returns domino logic gate; Wherein this reset circuit couples a subclass of above-mentioned a plurality of input nodes; This subclass comprises at least one; But non-total above-mentioned input node; The input node that belongs to this subclass comprises that separately a state returns node; Above-mentioned at least one estimated state each only at least one takes place when the above-mentioned second state transition in this subclass of above-mentioned a plurality of input nodes, and this dominoes circuit this preset condition of only when this subclass of above-mentioned a plurality of input nodes is above-mentioned second state totally, resetting back.

24. no clock status as claimed in claim 21 returns domino logic gate, wherein:

Above-mentioned a plurality of input node comprises that at least one returns logic ' 0 ' node; Each is designed to above-mentioned at least one recurrence logic ' 0 ' node switch at a logic ' 0 ' state and a logic ' 1 ' state, and above-mentioned at least one each leisure of recurrence logic ' 0 ' node is set at logic, and logic ' 0 ' is returned in ' 1 back transition;

This presets node and comprises a precharged node, and this dominoes circuit comprises that one returns logic ' 0 ' dominoes circuit;

When this dominoes circuit is this preset condition; This dominoes circuit set this precharged node and this activation node to logic ' 1 ' and set this output node and this first replacement node to logic ' 0 '; When this dominoes circuit is this latch mode; This this output node of dominoes circuit transition to logic ' 1 ' and this activation node of transition are logic ' 0 '; And; When logic ' 1 ' is returned in this first replacement node transition, this dominoes circuit this preset condition of resetting back;

When above-mentioned a plurality of input nodes be in above-mentioned at least one estimated state any the time; This this precharged node of estimation circuit transition is to logic ' 0 '; When above-mentioned a plurality of input nodes be not in above-mentioned at least one estimated state any the time, this estimation circuit does not influence this and presets node; And

When this activation node was logic ' 0 ', this second replacement node of this enable circuit transition was to logic ' 1 ', and when this activation node was not logic ' 0 ', this enable circuit did not influence this second replacement node.

25. no clock status as claimed in claim 24 returns gate; Wherein this reset circuit couples a subclass of above-mentioned a plurality of input nodes; This subclass comprises at least one but non-total above-mentioned input node; Each comprises that one returns logic ' 0 ' node input node in this subclass of above-mentioned a plurality of input nodes; Above-mentioned at least one estimated state each when occurring over just at least one input node in above-mentioned a plurality of this subclass of input node and switching to logic ' 1 ' by logic ' 0 ', and this dominoes circuit this preset condition of resetting back when only the input of all in this subclass of above-mentioned a plurality of input nodes node is logic ' 0 '.

26. no clock status as claimed in claim 21 returns gate, wherein:

Above-mentioned a plurality of input node comprises that at least one returns logic ' 1 ' node; Each is designed to above-mentioned at least one recurrence logic ' 1 ' node between logic ' 1 ' state and logic ' 0 ' state, switch, and each returns logic ' 1 ' in being set at logic ' 0 ' back above-mentioned at least one recurrence logic ' 1 ' node;

This presets node and comprises an in advance clear node, and this dominoes circuit comprises that one returns logic ' 1 ' dominoes circuit;

When this dominoes circuit is this preset condition; This dominoes circuit set should in advance clear node and this activation node be logic ' 0 ' and set this output node and this first replacement node is a logic ' 1 '; When the dominoes circuit is this latch mode; This this output node of dominoes circuit transition is that logic ' 0 ' and this activation node of transition are logic ' 1 '; When logic ' 0 ' is returned in this first replacement node transition, this dominoes circuit this preset condition of resetting back;

When above-mentioned a plurality of input nodes be in above-mentioned at least one estimated state any the time; This estimation circuit transition should in advance clear node be a logic ' 1 '; And when above-mentioned a plurality of input nodes be not in above-mentioned at least one estimated state any the time, this estimation circuit does not influence this and presets node; And

When this activation node was logic ' 1 ', this second replacement node of this enable circuit transition was a logic ' 0 ', and when this activation node was not logic ' 1 ', this enable circuit did not influence this second replacement node.

27. no clock status as claimed in claim 26 returns domino logic gate; Wherein this reset circuit couples a subclass of above-mentioned a plurality of input nodes; This subclass comprises at least one but non-whole above-mentioned input node; Each comprises that one returns logic ' 1 ' node input node in this subclass of above-mentioned a plurality of input nodes; Each only betides above-mentioned at least one estimated state and has an input node in this subclass of above-mentioned a plurality of input nodes at least when logic ' 1 ' transition is logic ' 0 ', and this dominoes circuit this preset condition of resetting back when only total input node is a logic ' 0 ' in this subclass of above-mentioned a plurality of input nodes.

28. no clock status as claimed in claim 21 returns domino logic gate, wherein:

At least one comprises that one returns logic ' 0 ' input node in above-mentioned a plurality of input node;

This presets node and comprises an in advance clear node; And

This dominoes circuit comprises:

One first inverter has an input and couples this precharged node and have an output and couple this output node;

One the one P lane device has a grid and couples this output node, has one source pole and couples a power supply current potential, and have a drain electrode and couple this precharged node;

One second inverter has an input and couples this output node, and has an output and couple this activation node;

One the one N lane device has one source pole and couples a reference potential, and a grid couples this activation node, and a drain electrode couples this replacement node;

One the 3rd inverter has an input and couples this replacement node, and has an output; And

One the 2nd P lane device has one source pole and couples this power supply current potential, has this output that a grid couples the 3rd inverter, and has a drain electrode and couple this precharged node.

29. no clock status as claimed in claim 28 returns domino logic gate, wherein this estimation circuit comprises a plurality of the 2nd N lane devices, and this reset circuit comprises at least one the 3rd P lane device.

30. no clock status as claimed in claim 21 returns domino logic gate, wherein:

At least one comprises that one returns logic ' 1 ' input node in above-mentioned a plurality of input node;

This presets node and comprises an in advance clear node; And

This dominoes circuit comprises:

One the 5th inverter has an input and couples this in advance clear node, and has an output and couple this output node;

One the one N lane device has a grid and couples this output node, has one source pole and couples a reference potential, and have a drain electrode and couple this in advance clear node;

One second inverter has an input and couples this output node, and has an output and couple this activation node;

One the one P lane device has one source pole and couples a power supply current potential, and a grid couples this activation node, and a drain electrode couples this replacement node;

One the 3rd inverter has an input and couples this replacement node, and has an output; And

One the 2nd N lane device has one source pole and couples this reference potential, has this output that a grid couples the 3rd inverter, and has a drain electrode and couple this in advance clear node.

31. no clock status as claimed in claim 30 returns domino logic gate, wherein this estimation circuit comprises a plurality of the 2nd P lane devices, and this reset circuit comprises at least one the 3rd N lane device.

32. an integrated circuit comprises:

One first logic; Supply at least one state and return signal; Wherein above-mentioned at least one state returns Design of Signal and switches at one first state and one second state, and this first logic can return according to state and operates in above-mentioned at least one state to return signal sets be above-mentioned first state to be returned in it setting behind above-mentioned first state; And

One no clock status returns domino logic gate, has a plurality of input nodes and receives above-mentioned at least one state recurrence signal, and this no clock status returns domino logic gate and comprises:

One presets node, an activation node, an output node and first and second replacement node, designs separately at above-mentioned first and second state to switch;

One dominoes circuit; Have a preset condition and a latch mode; Wherein, When this dominoes circuit is this preset condition; This dominoes circuit is set this and is preset node and this activation node is above-mentioned first state; And set this output node and this first replacement node is above-mentioned second state; When this presets the node transition for this second state; This dominoes circuit switches to this latch mode; With this output node of transition to above-mentioned first state; And this activation node of transition to above-mentioned second state; When this first state is returned in this first replacement node transition, this dominoes circuit this preset condition of resetting back;

One estimation circuit; Above-mentioned a plurality of input nodes be at least one estimated state any the time; This presets node to above-mentioned second state transition, and in above-mentioned a plurality of input nodes be not in above-mentioned at least one estimated state any time, do not influence this and preset node;

One activation circuit, this second replacement node of transition and does not influence this second replacement node when this second state in this activation node to this first state when this activation node is this second state; And

One reset circuit; Above-mentioned a plurality of input nodes be not in above-mentioned at least one estimated state any the time; Couple this first replacement node to this second replacement node; And in above-mentioned a plurality of input nodes be in above-mentioned at least one estimated state any the time, this first replacement node is isolated this second replacement node.

33. integrated circuit as claimed in claim 32, wherein this estimation circuit and this reset circuit are non-two configuration design each other.

34. integrated circuit as claimed in claim 32; Wherein this reset circuit couples a subclass of above-mentioned a plurality of input nodes; This subclass comprises at least one but non-whole above-mentioned input node; Each returns node for state input node in this subclass of above-mentioned a plurality of input nodes; Each occurs over just at least one input node in this subclass of above-mentioned a plurality of input nodes when the above-mentioned second state transition above-mentioned a plurality of estimated state, and the input node of this dominoes circuit in this subclass of above-mentioned a plurality of input nodes this preset condition of resetting back when totally being above-mentioned second state.

35. integrated circuit as claimed in claim 34; Wherein this first logic is supplied at least one and is returned logic ' 0 ' signal; Above-mentioned first state is that logic ' 1 ' and above-mentioned second state are logic ' 0 '; This no clock status returns domino logic gate and comprises that a no clock returns logic ' 0 ' domino logic gate, and the input node in this subclass of above-mentioned a plurality of input nodes comprises that separately one returns logic ' 0 ' node.

36. integrated circuit as claimed in claim 34; Wherein this first logic is supplied at least one and is returned logic ' 1 ' signal; Wherein, Above-mentioned first state is that logic ' 0 ' and above-mentioned second state are logic ' 1 '; This no clock status returns domino logic gate and comprises that a no clock returns logic ' 1 ' domino logic gate, and the input node in this subclass of above-mentioned a plurality of input nodes comprises that separately one returns logic ' 1 ' node.

37. the method for estimation one logical operation comprises:

Receive a plurality of input signals; Design separately at one first state and one second state and switch; Wherein, Above-mentioned a plurality of input signal comprises that at least one state returns signal, and above-mentioned at least one state returns signal can return above-mentioned second state of resetting back of operating according to state after being set at above-mentioned first state;

Supply has a dominoes circuit of a preset condition and a latch mode; When this dominoes circuit is this preset condition; This dominoes circuit is set one and is preset node and an activation node to one first state and set an output node and a replacement node to one second state; When this presets node transition to this second state; This dominoes circuit switches to this latch mode; With this output node of transition to this first state and this activation node of transition to this second state; When this first state is put in this replacement node transition, this dominoes circuit this preset condition of resetting back;

Estimate above-mentioned a plurality of input signal, wherein, above-mentioned a plurality of input signals be at least one estimated state any the time, this presets node to this second state transition, makes this dominoes circuit switch to this latch mode; And

This activation node be this second state and above-mentioned a plurality of input signal in above-mentioned at least one estimated state any the time, transition should replacement node to this first state, with this dominoes circuit of resetting to this preset condition.

Transition should replacement node to above-mentioned first state when returning signal above-mentioned second state is returned in transition after switching to above-mentioned first state separately for this second state and above-mentioned at least one state 38. method as claimed in claim 37, wherein above-mentioned replacement step are included in this activation node.

39. method as claimed in claim 37, wherein:

Above-mentioned estimation steps is included in above-mentioned at least one state and returns when having a transition to above-mentioned first state in signal at least transition this presets node to above-mentioned second state; And

It is that transition should replacement node to above-mentioned first state when returning the equal transition of signal and returning above-mentioned second state for above-mentioned second state and above-mentioned at least one state that above-mentioned replacement step is included in this activation node.

40. method as claimed in claim 37, wherein:

Above-mentioned estimation steps be included in above-mentioned at least one state when returning the total transition of signal and returning above-mentioned first state transition this preset node to this second state; And

Above-mentioned replacement step is included in this activation node, and transition should replacement node to above-mentioned first state when returning above-mentioned second state for this second state and above-mentioned at least one state return the total transition of signal.

41. a no clock status returns domino logic gate, responds a plurality of input logic signals, each switches on one first and one second logic state above-mentioned input logic signal, and above-mentioned no clock status recurrence gate comprises:

One dominoes circuit comprises:

A plurality of nodes switch on above-mentioned first and second logic state, and above-mentioned node comprises and presets node, an output node, an activation node and one first replacement node;

One first inverter has an input and couples this and preset node, and has an output and couple this output node;

One first device of one first conductive form has a control end and couples this output node, has one first current terminal and couples the one first power supply potential node relevant with this first logic state, and have one second current terminal and couple this and preset node;

One second inverter has an input and couples this output node, and has an output and couple this activation node;

One first device of one second conductive form has one first current terminal and is coupled with the second source potential nodes about this second logic state, has a control end and couples this activation node, and have one second current terminal and couple this first replacement node;

One the 3rd inverter has an input and couples this first replacement node, and has an output; And

One second device of this first conductive form has one first current terminal and couples this first power supply potential node, has this output that a control end couples the 3rd inverter, and has one second current terminal and couple this and preset node; And

Couple the input circuit that this presets node, this replacement node and this activation node; Above-mentioned a plurality of input logic signal is responded in design; Wherein, When above-mentioned a plurality of input logic signals are any of at least one estimated state; This presets node to this second logic state this input circuit transition; When any of above-mentioned at least one estimated state left in above-mentioned a plurality of input logic signal transitions, this first replacement node of the temporary transient transition of this input circuit was to this first logic state.

42. no clock status as claimed in claim 41 returns domino logic gate, wherein this input circuit comprises:

One estimation circuit, above-mentioned a plurality of input logic signal is responded in design, wherein, when above-mentioned a plurality of input logic signals be in above-mentioned at least one estimated state any the time, this presets node for this second logic state this estimation circuit transition;

One activation circuit, transition one second replacement node is this first logic state when this activation node is this second logic state; And

One reset circuit; At least one input logic signal in above-mentioned a plurality of input logic signal is responded in design; Wherein, when above-mentioned a plurality of input logic signals be not in above-mentioned at least one estimated state any the time, this reset circuit couples this first replacement node to this second replacement node.

43. no clock status as claimed in claim 42 returns domino logic gate, at least one comprises that a state returns signal in wherein above-mentioned a plurality of input signals, is supplied to a state of this estimation circuit and this reset circuit to return signal.

44. no clock status as claimed in claim 41 returns domino logic gate; One second device that also comprises this second conductive form; Have a control end and couple this output of the 3rd inverter; Have one first current terminal and couple this first replacement node, and have one second current terminal and couple this second source potential nodes.

45. no clock status as claimed in claim 41 returns domino logic gate; Wherein this first power supply potential node has one on the occasion of power supply potential; This second source potential nodes has a reference potential; This first conductive form comprises semiconductor P form, and this second conductive form comprises the semiconductor N form.

46. no clock status as claimed in claim 41 returns domino logic gate; Wherein this first power supply potential node has a reference potential; This second source potential nodes has one on the occasion of power supply potential; This first conductive form comprises the semiconductor N form, and this second conductive form comprises semiconductor P form.

47. no clock status as claimed in claim 41 returns domino logic gate; Wherein above-mentioned first and second power supply potential node has one respectively on the occasion of a power supply potential and a reference potential; At least one comprises that one returns logic ' 0 ' signal in above-mentioned a plurality of input logic signal, wherein:

This presets node and comprises a precharged node;

This first device of this first conductive form comprises one the one P lane device, has a grid and couples this output node, has one source pole and receives above-mentionedly on the occasion of power supply potential, and has a drain electrode and couples this precharged node;

This first device of this second conductive form comprises one the one N lane device, has one source pole and receives this reference potential, has a grid and couples this activation node, and have a drain electrode and couple this replacement node; And

This second device of this first conductive form comprises one the 2nd P lane device, has one source pole and receives and should have this output node that a grid couples the 3rd inverter on the occasion of power supply potential, and have a drain electrode and couple this precharged node.

48. no clock status as claimed in claim 41 returns domino logic gate; Wherein this first and this second source potential nodes comprise that respectively a reference potential and is on the occasion of power supply potential; At least one comprises that one returns logic ' 1 ' signal in wherein above-mentioned a plurality of input logic signals, wherein:

This presets node and comprises an in advance clear node;

This first device of this first conductive form comprises one the one N lane device, has a grid and couples this output node, has one source pole and receives this reference potential, and have a drain electrode and couple this in advance clear node;

This first device of this second conductive form comprises one the one P lane device, has one source pole and receives and should have a grid and couple this activation node on the occasion of power supply potential, and have a drain electrode and couple this replacement node; And

This second device of this first conductive form comprises one the 2nd N lane device, has one source pole and receives this reference potential, has this output that a grid couples the 3rd inverter, and has a drain electrode and couple this in advance clear node.

49. an integrated circuit comprises:

One first circuit; Supply at least one state and return signal; Wherein above-mentioned at least one state returns signal, and each switches on one first state and one second state, and this first circuit returns operation according to state above-mentioned second state is returned in it setting after above-mentioned state returns signal sets to be above-mentioned first state;

A plurality of nodes; Switch on above-mentioned first and second logic state; Above-mentioned a plurality of node comprises and presets node, an output node, an activation node, a replacement node and a plurality of input node, has at least one to receive above-mentioned at least one state and return one of signal in above-mentioned a plurality of input nodes;

One first inverter has an input and couples this and preset node, and has an output and couple this output node;

One first device of one first conducted state has a control end and couples this output node, has one first current terminal and receives and to be relevant to one first power supply potential of above-mentioned first logic state, and have one second current terminal and couple this and preset node;

One second inverter has an input and couples this output node and have an output and couple this activation node;

One first device of one second conductive form has one first current terminal and receives the second source current potential about above-mentioned second logic state, has a control end and couples this activation node, and have one second current terminal and couple this replacement node;

One the 3rd inverter has an input and couples this replacement node, and has an output;

One second device of one first conductive form has one first current terminal and receives this first power supply potential, has this output that a control end couples the 3rd inverter, and has one second current terminal and couple this and preset node; And

One input circuit; Couple this and preset node, this replacement node, this activation node and above-mentioned a plurality of input node; Wherein, When above-mentioned a plurality of input nodes are any of at least one estimated state; This presets node to this second logic state this input circuit transition; When the transition of above-mentioned a plurality of input node be not in above-mentioned at least one estimated state any the time, the temporary transient transition of this input circuit should the replacement node to this first logic state.

50. integrated circuit as claimed in claim 49; One second device that also comprises this second conductive form; Have a control end and couple this output of the 3rd inverter, have one first current terminal and couple this replacement node, and have one second current terminal and receive this second source current potential.

51. integrated circuit as claimed in claim 49; Wherein this first power supply potential comprises one on the occasion of power supply potential; This second source current potential comprises a reference potential, and this first conductive form comprises semiconductor P type technology, and this second conductive form comprises semiconductor N type technology.

52. integrated circuit as claimed in claim 49; Wherein this first power supply potential comprises a reference potential; This second source current potential comprises one on the occasion of power supply potential, and this first conductive form comprises semiconductor N type technology, and this second conductive form comprises semiconductor P type technology.

53. integrated circuit as claimed in claim 49, wherein above-mentioned first and the second source current potential comprise one respectively on the occasion of a power supply potential and a reference potential, and wherein:

This presets node and comprises a precharged node;

This first device of this first conductive form comprises one the one P lane device, has a grid and couples this output node, has one source pole and couples this on the occasion of power supply potential, and have a drain electrode and couple this precharged node;

This first device of this second conductive form comprises one the one N lane device, has one source pole and receives this reference potential, has a grid and couples this activation node, and have a drain electrode and couple this replacement node; And

This second device of this first conductive form comprises one the 2nd P lane device, has one source pole and receives and should have this output that a grid couples the 3rd inverter on the occasion of power supply potential, and have a drain electrode and couple this precharged node.

54. integrated circuit as claimed in claim 49, wherein this first and this second source current potential comprise a reference potential and respectively on the occasion of power supply potential, and wherein:

This presets node and comprises an in advance clear node;

This first device of this first conductive form comprises one the one N lane device, has a grid and couples this output node, has one source pole and receives this reference potential, and have a drain electrode and couple this in advance clear node;

This first device of this second conductive form comprises one the one P lane device, has one source pole and receives and should have a grid and couple this activation node on the occasion of power supply potential, and have a drain electrode and couple this replacement node; And

This second device of this first conductive form comprises one the 2nd N lane device, has one source pole and receives this reference potential, has this output that a grid couples the 3rd inverter, and has a drain electrode and couple this in advance clear node.

55. the method for a plurality of logical signals of estimation, wherein, above-mentioned a plurality of logical signals comprise that at least one state returns input signal, comprising:

Set one and preset node to one first logic state, this first logic is the anti-phase of one second logic state;

This presets node to define the logic state of an output node anti-phase;

This output node of anti-phase is to define the logic state of an activation node;

When this activation node is this first logic state transition should the replacement node to this second logic state;

Anti-phase should the replacement node to determine the logic state of an anti-phase replacement node;

When this anti-phase replacement node was this second logic state, this preset node to this first logic state transition;

Only in above-mentioned a plurality of input signals be at least one estimated state any the time; Force this to preset node and be this second logic state; Above-mentioned a plurality of input signal comprises that at least one state returns input signal, and above-mentioned state returns logical signal and after transition is first logic state, returns second logic state;

When to be this second logic state and above-mentioned a plurality of input signal according to state returned operation and break away from an estimated state, pressure should the replacement node be this first logic state at this activation node; And

When this replacement node is forced to this first logic state; This anti-phase replacement node transition is this second logic state; Then, this presets transition node and returns this first logic state, then; This output node of transition returns this second logic state; Then, this activation node of transition returns this first logic state, and then transition should be returned this second logic state by the replacement node; Then, this anti-phase replacement node of transition returns this first logic state.

56. method as claimed in claim 55; Wherein, This step that presets node to this second logic state of above-mentioned pressure comprises at least one state returned at least one transition in the input signal to this first logic state, and the step of this replacement node of above-mentioned pressure to this first logic state comprises that above-mentioned at least one state is returned in input signal at least one transition returns this second logic state.

57. method as claimed in claim 55 comprises that also using half holding circuit to keep this replacement node is this first logic state.

58. method as claimed in claim 55 comprises that also using half holding circuit to keep this replacement node is this second logic state.

59. method as claimed in claim 55; Wherein, Above-mentioned this step that presets node to this first logic state that is provided with comprises on preliminary filling one precharged node to logic ' 1 '; Above-mentioned transition should replacement node to this second logic state step comprise that transition should make it to reduce to logic ' 0 ' by the replacement node; This step that presets node to this first logic state of above-mentioned transition comprises on this precharged node of transition to logic ' 1 '; This step that presets node to this second logic state of above-mentioned pressure comprises forces this precharged node to reduce to logic ' 0 ', and the step of this replacement node of above-mentioned pressure to this first logic state comprises on this replacement node of pressure to logic ' 1 '.

60. method as claimed in claim 55; This step that presets node to the first logic state of wherein above-mentioned setting comprises that setting an in advance clear node reduces to logic ' 0 '; Above-mentioned transition should replacement node to this second logic state step comprise transition should the replacement node on to logic ' 1 '; This step that presets node to this first logic state of above-mentioned transition comprises that transition should reduce to logic ' 0 ' by in advance clear node; This step that presets node to this second logic state of above-mentioned pressure comprise pressure should in advance clear node on to logic ' 1 ', and this replacement node of above-mentioned pressure step that is first logic state comprises and forces this replacement node to reduce to logic ' 0 '.

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