CN1553453A - Non-inverting domino register - Google Patents
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- CN1553453A CN1553453A CNA2004100476531A CN200410047653A CN1553453A CN 1553453 A CN1553453 A CN 1553453A CN A2004100476531 A CNA2004100476531 A CN A2004100476531A CN 200410047653 A CN200410047653 A CN 200410047653A CN 1553453 A CN1553453 A CN 1553453A
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Abstract
A non-inverting domino register including a domino stage, a storage stage, a keeper circuit and an output stage. The domino stage includes evaluation logic, coupled between evaluation devices at a pre-charged node, which evaluates a logic function. The storage stage drives a first preliminary output node and includes a pull-up device and a pull-down device both responsive to the pre-charged node, and a second pull-down device responsive to the clock signal. The keeper circuit is a cross-coupled pair of inverters coupled between the first preliminary output node and a second preliminary output node. The output stage includes a pair of pull-up and pull-down devices for driving an output node. The first pull-up device and the first pull-down device are both responsive to the pre-charged node, and the second pull-up device and the second pull-down device are both responsive to the second preliminary output node.
Description
Technical field
The present invention relates to the field of dynamic logic and buffer function, relate in particular to a kind of noninverting dominoes (domino) buffer, it can solve apparent velocity and the output buffers problem of size for the complex logic circuit of important factor.
Background technology
Integrated circuit has used a large amount of buffers, and especially those have the buffer of a synchronous pipeline architecture.The cache logic device is used for making the output of element and circuit to keep a period of time, so that these outputs can be received by other element and circuit.In a frequency system, such as a pipeline microprocessor, buffer is used for the output signal of the given pipeline stages of breech lock (latch), and keep this simultaneously and export a band frequency cycle period, so that the input circuit in the back level can receive last output signal when this given pipeline stages side by side produces a new output.
In the past, logic executive circuit in complexity, such as the front and back of multiple input multiplexer (muxes), multidigit scrambler etc., often utilize buffer to keep and desire to enter the input signal of computing circuit (evaluation circuits) and the signal of exporting from computing circuit.In general, the requirement that these buffers all have related setting-up time and hold time, and these two kinds of requirements all can limit the computing circuit in the prime.In addition, buffer also has the time response of data-output (data-to-output), and it can limit the computing circuit in the level of back.The speed of typical case's buffer is judged the time according to its data-output, also is the time that its setting-up time adds upper frequency-output.
Use traditional cache circuit to produce delay in a pipeline system in the front and back of a logical operation circuit, the result of its accumulation will cause operating speed obviously to be slowed down.More particularly, in these postponed, a significant source was for corresponding to the demand of the time of output terminal from data terminal, and it must satisfy logical operation circuit to guarantee stable buffer memory output.Therefore, the objective of the invention is to how to reduce these and postpone, so that increase the extra time in each grade, and then promote the speed of whole pipeline system.
Figure 1A is the Organization Chart of conventional inverter dominoes (domino) buffer 100.The logical designer combines the corresponding buffer of logical operation function and its, attempts making the some of anti-phase dominoes buffer 100 in addressing the above problem.This anti-phase dominoes buffer 100 comprises a logical operation input stage, or claims the dominoes level, and it is made of the P pass element of storehouse and N pass element P1, N1 and N2.P pass element P1 and N pass element N2 are a complementary pair of arithmetic element, and N pass element N1 then represents the arithmetic logic device.The source electrode of P pass element P1 is coupled to a voltage source V DD, and its drain electrode then is coupled to the node 105 that a signal TOP is provided.The drain electrode of N pass element N1 is coupled to node 105, and its source electrode then is coupled to the drain electrode of N pass element N2.The source electrode of N pass element N2 is coupled to earth terminal.One input clock signal CLK then offers the grid of P pass element P1 and N pass element N2 via node 101.One input data signal DATA then provides to the grid of N pass element N1 via node 103.
Followed a storage level, a weak sustain circuit 111 and at least one inverters/buffers 109 after the dominoes level, this inverters/buffers 109 is in order to reduce noise.Include P pass element P2, N pass element N3 and N4 in this storage level.Node 101 is coupled to the grid of N pass element N3, and 105 of nodes are coupled to the grid of P pass element P2 and N pass element N4.The source electrode of P pass element P2 is coupled to voltage source V DD, and its drain electrode then is coupled to the node 107 that an intermediate output signal QBI is provided.Node 107 is coupled to input end, and the drain electrode and the weak sustain circuit 111 of N pass element N3 of phase inverter 109.The source electrode of N pass element N3 is coupled to the drain electrode of N pass element N4, and the source electrode of N pass element N4 then is coupled to earth terminal.Holding circuit 111 has one first phase inverter 111A, the input end of this first phase inverter 111A is coupled to node 107 with received signal QBI, its output terminal then is coupled to the input end of one second phase inverter 111B, and wherein the output terminal of the second phase inverter 111B is coupled to node 107.Phase inverter 109 has an output that is coupled to node 113, and this output provides a reversed-phase output signal QB.Content as described below can increase by an extra inverters/buffers 115, and it is represented by dotted lines, and the input end of this inverters/buffers 115 is coupled to node 113, and its output terminal then is coupled to the node 117 that a noninverting output signal Q is provided.
Figure 1B is the time sequences synoptic diagram of anti-phase dominoes buffer 100, wherein is that transverse axis is drawn CLK, DATA, TOP, QBI, QB and Q signal with time.When time T 0, CLK is initially low level when signal, and this moment, N pass element N2 was for closing P pass element P1 for opening, thus this dominoes level to carry out preliminary filling (pre-charge) and make signal TOP be high level.Signal TOP preliminary filling is that high level is in order to be triggered to carry out the computing of signal DATA when the rising edge of signal CLK.Wherein signal DATA is initially high level.Because signal TOP is high level, so P pass element P2 is for closing, and owing to signal CLK is a low level, so P pass element N3 is a closed condition.Signal QBI and this input stage will be isolated, so signal QBI will make it remain on previous state by holding circuit 111.As shown in the figure, signal QBI is initially low level when time T 0, and signal QB then makes it be initially high level by inverters/buffers 109.Inverters/buffers 109 can protect the output of holding circuit 111 to avoid interference of noise, and can produce output signal QB, and this output signal QB is the rp state of signal DATA after via logical function operation.
In ensuing time T 1, signal CLK is pulled to high level, makes N pass element N2 open and P pass element P1 closes.Because signal DATA is high level when time T 1, so N pass element N1 will continue unlatching, make signal TOP in a short delay after be discharged to low level by N pass element N1 and N2.The delay of trace is left in the basket in sequential chart.Signal QBI also is pulled to high level when time T 1, and signal QB is pulled to low level because of the delay via inverters/buffers 109 when time T 2.Signal CLK then reduces to low level when time T 4, and signal TOP begins to carry out preliminary filling via P pass element P1 at this moment once more.Signal QBI then isolates with the input stage of P pass element P2 and N pass element N3 once more, so the state of signal QBI still maintains high level via the operation of holding circuit 111, and signal QB then maintains low level.In time T 5, signal CLK is pulled to high level once more subsequently, and this moment, signal DATA was a low level then, thereby caused N pass element N1 and P pass element P1 all to close.Signal TOP keeps high level, so N pass element N3 and N pass element N4 all open, and makes signal QBI be discharged to low level when time T 5.After signal QB then passes through the delay of inverters/buffers 109, when time T 6, rise to high level.In remaining this frequency circulation, when signal CLK reduced to low level when it was contained in time T 8, signal TOP, QBI will remain unchanged with the corresponding state of QB.Unique being restricted to, when signal CLK was high level, signal DATA will remain unchanged.The CLK signal is generally a pulse signal, and the time of its high level state is very short.
Be noted that anti-phase dominoes buffer 100 utilizes a simple D type flip-flop to implement, wherein N pass element N1 is as the individual component that is used in the computing circuit of computing signal DATA (being the input end of D type flip-flop).Yet the personage who is familiar with this skill can utilize than the complicated logical operation function and replaces N pass element N1 when understanding it.This dominoes buffer can be considered anti-phase reason, is the rp state that is all input signal DATA because of the operation result of output signal QB when trigger each rising edge of signal CLK.If inverters/buffers 115 exists, then the state of signal Q will be via the delay heel of phase inverter 109 and 115 with signal QBI.As shown in the figure, output signal QB is low level when time T 2, and it is high level when time T 6, and after the delay via inverters/buffers 115, corresponding signal Q transfers high level to during respectively at time T 3, when time T 7, gets back to low level once more.
Is under the crucial condition with time, another solution on this path is that to get output signal QBI placed in the middle be buffer memory output.Only this second mode will expose weak sustain circuit 111 in noise, and so the stability of output signal QBI will be greatly affected.Therefore in order to produce a noninverting output, the deviser be not accept extra time delay, must bear the unsettled danger of output exactly.
Summary of the invention
The present invention discloses a kind of non-anti-phase dominoes bumper, and its a complementary paired arithmetic element, arithmetic logic device, storage level, that includes response one clock signal is kept a circuit and an output stage.The arithmetic logic device is coupled on the interelement precharged node of this complementation paired arithmetic, and comes computing one logical function according at least one input data signal.Storage level can drive one first preparation output node, and it includes and draw (pull-up) element and one first drop-down (pull-down) element on one first, and this two elements is all in response to precharged node.This storage level also includes one second drop down element of response clock signal.Holding circuit then has an input end, and it can drive one second preparation output node to be coupled to the first preparation output node and an output terminal.Output stage includes and draws element and one the 3rd drop down element on one second, this two elements all in response to precharged node to drive an output node.Output node also includes and draws element and one the 4th drop down element on one the 3rd, and this two elements then all prepares output node to drive output node in response to second.
Non-anti-phase dominoes bumper can utilize P pass element and N pass element to implement.For instance, this complementation paired arithmetic element, this storage level and this output stage all can utilize P pass element and N pass element to implement.The arithmetic logic device can be very simple, also can be very complicated, and it can be a complex logic circuit for instance.In one embodiment, holding circuit is a pair of phase inverter that couples alternately, and it is between first and second preparation output node.This phase inverter can be undersized relatively element to dwindle delay.The feedback inverter of holding circuit can utilize an activation phase inverter to replace.
According to the non-anti-phase dominoes bumper of above-mentioned conception, wherein should also include by complementation paired arithmetic element: a P pass element, it has a grid that receives this frequency signal, is coupled to the one source pole of a voltage source and is coupled to a drain electrode of this precharged node; And a N pass element, it has a grid that receives this frequency signal, is coupled to the one source pole of an earth terminal and is coupled to a drain electrode of this arithmetic logic device.
According to the non-anti-phase dominoes bumper of above-mentioned conception, wherein this storage level comprises: a P pass element, and it has a grid that is coupled to this precharged node, and the one source pole and a drain electrode that is coupled to this first preparation output node that are coupled to a voltage source; One the one N pass element, its have in order to a grid that receives this clock signal, be coupled to this first the preparation output node one the drain electrode and one source pole; And one the 2nd N pass element, a drain electrode of this source electrode that it has the grid that is coupled to this precharged node, be coupled to a N pass element and the one source pole that is coupled to earth terminal.
According to the non-anti-phase dominoes bumper of above-mentioned conception, wherein this holding circuit comprises and is coupled to this first and second pair of phase inverters of preparation between the output node alternately.
According to the non-anti-phase dominoes bumper of above-mentioned conception, wherein this output stage comprises: one the one P pass element, and it has a grid, an one source pole that is coupled to a voltage source and a drain electrode that is coupled to this output node that is coupled to this precharged node; One the 2nd P pass element, it has a grid that is coupled to this second preparation output node, a drain electrode that is coupled to the one source pole of this voltage source and is coupled to this output node; One the one N pass element, it has a grid that is coupled to this second preparation output node, a drain electrode and an one source pole that is coupled to this output node; And one the 2nd N pass element, a drain electrode of this source electrode that it has the grid that is coupled to precharged node, be coupled to a N pass element and the one source pole that is coupled to earth terminal.
The present invention also discloses a kind of buffer, and it includes a computing circuit, a storage circuit, is kept a circuit and an output circuit.Computing circuit can carry out preliminary filling to a first node when a clock signal is low level, and when clock signal was high level, computing one logical function was with the state of control first node.Storage circuit is coupled to first node and receive clock signal.This storage circuit can drive a Section Point to high level when first node is low level, and when clock signal and first node are high level, drives Section Point to low level.Holding circuit can be kept the state of Section Point under situation about not driven by prime, and drives one the 3rd node to a logic state anti-phase with Section Point.It is high level that output circuit can drive an output node at first node or the 3rd node during for low level, and when first node and the 3rd node were high level, driving this output node was low level.Buffer can utilize P pass element and N pass element to implement.
According to the buffer of above-mentioned conception, wherein this computing circuit comprises: a P pass element, and it is coupled to this first node and can receives this clock signal, and this P pass element carries out preliminary filling to this first node when this clock signal is low level; One logical circuit, it is coupled to this first node, and this logical circuit can carry out the computing of logical function according at least one input data signal; And a N pass element, it is coupled to this logical circuit and can receives this clock signal, and this N pass element can order about this logical circuit when this clock signal is high level, carry out the computing of logical function.
According to the buffer of above-mentioned conception, wherein this storage circuit comprises: a P pass element, and it is coupled to this first and second node, and this P pass element is pulled to high level with this Section Point when this first node is reduced to low level; One the one N pass element, it is coupled to this Section Point and can receives this clock signal; And one the 2nd N pass element, it is coupled to a N pass element and this first node; Wherein this first and second N pass element is pulled to low level with this Section Point together when this first node rises to high level and is pulled to high level because of responding this clock signal.
According to the buffer of above-mentioned conception, wherein this holding circuit comprises a pair of phase inverter that couples alternately that is coupled between this second and the 3rd node.
According to the buffer of above-mentioned conception, wherein this output circuit comprises: one the one P pass element, and it can be pulled to high level with this output node when this first node is low level; One the 2nd P pass element, it can be pulled to high level with this output node when the 3rd node is low level; And first and second N pass element, it can be pulled to low level with this output node together when this first and the 3rd node is high level.
The present invention also discloses a kind of with a logical function buffer memory and produce the method for a noninverting output signal, and it comprises when a clock signal presets a first node during in one first logic state; When this clock signal switched to one second logic state, computing one logical function was to control the logic state of this first node; Drive a Section Point to switching to its second logic state with response clock signal with the anti-phase logic state of first node; Keep this Section Point in its previous driven logic state; Drive one the 3rd node to the logic state anti-phase with Section Point; And drive an output node according to the state of first node and the 3rd node.
Method of the present invention according to above-mentioned conception, wherein preset and to comprise: first node is carried out preliminary filling to high logic state what this first node carried out, and keep this Section Point and comprise that in its previous logic state that drives keeping circuit with one is coupled to this Section Point, and the content that drives the 3rd node comprises the state of this Section Point anti-phase in addition; The step that wherein drives this Section Point can comprise: when first node is low level, Section Point is pulled to high level, and when clock signal and first node are high level, Section Point is pulled to low level; The step that wherein drives this output node can comprise: arbitrary when the low level at first node and the 3rd node is pulled to high level with output node, and when first node and the 3rd node are high level, output node is pulled to low level.
Description of drawings
Figure 1A is the Organization Chart of conventional inverter dominoes (domino) buffer.
Figure 1B is the time sequences synoptic diagram of the anti-phase dominoes buffer among Figure 1A, wherein is that transverse axis is drawn selected signal with time.
Fig. 2 A is the structural representation of the non-anti-phase dominoes bumper in the preferred embodiment of the present invention.
Fig. 2 B is the time sequences synoptic diagram of the non-anti-phase dominoes bumper among Fig. 2 A, wherein is that transverse axis is drawn selected signal with time.
Fig. 3 is the demonstrative structure figure of the logic device AND that can be implemented in the arithmetic logic device among embodiment of the invention Fig. 2 A; And
Fig. 4 is the demonstrative structure figure of the logic device OR that can be implemented in the arithmetic logic device among embodiment of the invention Fig. 2 A.
100: anti-phase dominoes buffer
101,103,105,107,113,117,201,205,207,301,303,401,403: node
109,115: inverters/buffers
111: the weak sustain circuit
111A: first phase inverter
111B: second phase inverter
200: non-anti-phase dominoes bumper
203:N node set
204: the arithmetic logic device
209: the weak sustain circuit
209A, 209B: phase inverter
211,213: output node
300: logic device AND
400: logic device OR
Embodiment
The following description is under the train of thought of a specific embodiment and necessary condition thereof and provide, and can make the personage who generally has the knack of this technology can utilize the present invention.Yet the various modifications that this preferred embodiment is done are apparent for the personage who has the knack of this technology, and, in this General Principle of discussing, also can be applied to other embodiment.Therefore, the present invention is not limited to this place and shows specific embodiment with narration, but has the maximum magnitude that the principle that place therewith discloses conforms to novel feature.
At the demand of the buffer memory of logical circuit output for key factors such as speed, size and degree of stability, therefore one anti-phase dominoes buffer is proposed, do not needing under the situation that output stability is compromised, can have than classic method and also want fast data-output time, its detailed description will be arranged in pairs or groups Fig. 2 A to Fig. 4 in explanation down.Highly be dependent on buffer when transmitting the pipelined architecture of data at different levels when being used in one, non-anti-phase dominoes bumper provided by the present invention can make the operating speed of all elements that tangible lifting is arranged.
Fig. 2 A is the structural representation of the non-anti-phase dominoes bumper 200 in the preferred embodiment of the present invention.Non-anti-phase dominoes bumper 200 comprises a logical operation input stage (or claim dominoes level), and it is made up of the P pass element of storehouse and N pass element P1 and N2 and arithmetic logic device 204.The logical operation input stage of non-anti-phase dominoes bumper 200 is similar to the logical operation input stage of anti-phase dominoes buffer 100, and the P pass element P1 of wherein anti-phase dominoes buffer 100 and N pass element N2 are the both sides that a complementary paired arithmetic element is positioned at arithmetic logic device 204.Arithmetic element N1 is then replaced by arithmetic logic device 204, the structure that it can be simple as N pass element N1, also can be one the structure of complexity with any required logical function of computing.The source electrode of P pass element P1 is coupled to a voltage source V DD, and its drain electrode then is coupled to node 205 so that a signal TOP to be provided.Arithmetic logic device 204 is coupled between the drain electrode of node 205 and N pass element N2.The source electrode of N pass element N2 then is coupled to earth terminal.One input clock signal CLK provides to the grid of P pass element P1 and N pass element N2 via node 201.An one N node set 203 then provides N input data signal DATA to arithmetic logic device 204, and wherein N is a positive integer.
The dominoes level of non-anti-phase dominoes bumper 200 is followed a storage level thereafter, and it includes P pass element P2, N pass element N3 and N4.Node 201 is coupled to the grid of N3, and node 205 then is coupled to the grid of P pass element P2 and N pass element N4.The source electrode of P pass element P2 is coupled to voltage source V DD, and its drain electrode then is coupled to one first intermediate output node 207 that one first intermediate output signal QII can be provided.Node 207 is coupled to the drain electrode of N pass element N3, the input end of phase inverter 209A and the output terminal of another phase inverter 209B.The output terminal of phase inverter 209A is coupled to one can provide one second intermediate output node, 211, the second intermediate output nodes 211 of one second intermediate output signal QI then to be coupled to the input end of phase inverter 209B.Phase inverter 209A and 209B couple alternately in node 207 and 211, and it forms a weak sustain circuit 209 mutually.The source electrode of N pass element N3 is coupled to the drain electrode of N pass element N4, and the source electrode of N pass element N4 is coupled to earth terminal.
The storage level of non-anti-phase dominoes bumper 200 is followed an extra output stage thereafter, and it comprises P pass element P3 and P4 and N pass element N5 and N6.Node 205 is coupled to the grid of P pass element P4 and N pass element N6, and node 211 is coupled to the grid of P pass element P3 and N pass element N5.The source electrode of P pass element P3 and P4 is coupled to voltage source V DD, and its drain electrode then is coupled to an output node 213 together so that an output signal Q to be provided.Output node 213 is coupled to the drain electrode of N pass element N5, and the source electrode of N pass element N5 is coupled to the drain electrode of N pass element N6, and the source electrode of N pass element N6 then is coupled to earth terminal.In general the P pass element plays the part of the role who draws element, and in general the N pass element then plays the part of the role of drop down element, and its detailed situation is as described below.
Fig. 2 B is the time sequences synoptic diagram of non-anti-phase dominoes bumper 200, wherein is that transverse axis is drawn CLK, DATAN, TOP, QII, signals such as QI, Q with time.Signal DATAN is a single signal of expression N group signal DATA set.When the Set Status of data-signal caused arithmetic logic device 204 to carry out computing, single signal DATAN such as figure were shown as high level, itself thereby make signal TOP be pulled to low level.And when arithmetic logic device 204 did not carry out computing, signal DATAN then was shown as low level, and it will keep signal TOP in high level.When time T 10, signal CLK is initially low level, and this moment, N pass element N2 closed and P pass element P1 unlatching, and making the dominoes level carry out preliminary filling signal TOP is high level.Signal TOP preliminary filling is that high level is in order to be triggered to carry out the computing of signal DATAN when the rising edge of signal CLK.The signal TOP of preliminary filling can open N pass element N4 and N6.The initial value of signal DATAN is a high level.Signal QII maintains its original state (its original state shown in the figure is a low level) by holding circuit 209.The initial value of signal QI is a high level, thereby can open N pass element N5, and it makes output signal Q via N pass element N5 and N6 and be initially low level.
When time T 11, signal CLK rises to high level, because signal DATAN is a high level, it causes signal TOP to be discharged to low level.More particularly, N pass element N2 is unlocked, and arithmetic logic device 204 carries out computing and makes signal TOP be pulled to low level.But after through the negligible delay behind P pass element P2 and the P4, big when same time T 11, signal QII and signal Q all are pulled to high level.Signal QI is pulled to low level when time T 12 after the delay through phase inverter 209A.Rp state in the signal QI of holding circuit 209 output terminals can drive P pass element P3 and N pass element N5.If signal QI is a high level, then P pass element P3 closes and N pass element N5 unlatching; If signal QI is a low level, then P pass element P3 unlatching and N pass element N5 close.When time T 13, signal CLK reduces to low level subsequently, signal TOP then once more preliminary filling to high level.And the state of signal QII and signal QI remains unchanged by the running of holding circuit 209 respectively, so signal Q will keep high level in this remaining half frequency circulation of signal CLK.
Signal CLK then is pulled to high level when time T 14, this moment, signal DATAN was a low level.Arithmetic logic device 204 does not carry out computing, to such an extent as to signal TOP will keep high level.Signal CLK and signal TOP will open element N pass element N3 and N4, make signal QII be pulled to low level when time T 14.After the delay of signal QI through phase inverter 209A, when T15, be pulled to high level.Signal QI can open N pass element N5 and P pass element P3 is closed, and therefore after an insignificant delay, signal Q reduces to low level when time T 15.And again, when signal CLK reduced to low level during in time T 16, the state of signal QII and signal QI remained unchanged by the running of holding circuit 209 respectively, so signal Q will keep low level in this remaining half frequency circulation of signal CLK.
Hence one can see that, when arithmetic logic device 204 carries out computing and makes that signal TOP is discharged to low level, the rising edge that signal Q will respond a signal CLK trigger and very apace from low transition to high level.At this, cause exporting instantaneous delay through N pass element N2 and P pass element P4, can ignore basically and not remember.In addition, when arithmetic logic device 204 does not carry out computing and makes signal TOP continue as high level, after the relative less delayed through N pass element N3, N5 and phase inverter 209A, signal Q triggers the rising edge of response signal CLK and reduces to low level from high level.Owing to do not need to have the function that an impact damper does not need to carry out impact damper yet, therefore component size can be dwindled (it has minimum capacitance), dwindled and can make thus, and then time T 14 to the time delay relativity of time T 15 ground is dwindled via the delay of phase inverter 209A.
The personage who is familiar with this skill is when understanding, in contrast to that anti-phase dominoes buffer 100 utilizes that output terminal adds that an inverters/buffers 115 causes as output than slow-speed throw-over degree, the state exchange of the state exchange response signal CLK of the output signal Q of non-anti-phase dominoes bumper 200, its speed is very fast.If one noninverting be output as must or during demand, non-anti-phase dominoes bumper 200 is in that performance is excellent far and away on data-output speed and on other advantage described herein.Non-anti-phase dominoes bumper 200 desires to be converted to anti-phase dominoes buffer only to be needed add that at its output terminal an output inverters/buffers (not being shown among the figure) get final product simply, and the speed that its comparable anti-phase dominoes buffer 100 does not increase under the situation of inverters/buffers 115 is also wanted soon.Anti-phase dominoes buffer 100 still is acceptable selection when the anti-phase output of demand, supposes that it has used less elements under the situation of not using inverters/buffers 115, and its size is less and can consume small electric power.
Fig. 3 is the demonstrative structure figure of the logic device AND 300 in the arithmetic logic device 204 that may be implemented in the embodiment of the invention.Logic device AND 300 comprises by a N pass element N1, N2 ... the storehouse that NN formed, it is in node 301 and 303 coupled in series.In this embodiment, node 301 is coupled to node 205, and node 303 then is coupled to the drain electrode of N pass element N2, so that logic device AND 300 is replaced arithmetic logic device 204.Each N pass element N1 to NN all has a grid, and each grid all can receive a corresponding data sequence signal D1, D2 ... one of them of DN.Logic device AND 300 carries out computing at all signals of data sequence signal D1 to DN during for high level, does not then carry out computing when the arbitrary signal between data sequence signal D1 to DN is low level.
Fig. 4 is the demonstrative structure figure of the logic device OR 400 in the arithmetic logic device 204 that may be implemented in the embodiment of the invention.Logic device OR 400 comprises by a N pass element N1, N2 ... the parallel tandem that NN formed, it couples side by side in node 401 and 404.In this embodiment, node 401 is coupled to node 205, and node 403 then is coupled to the drain electrode of N pass element N2, so that logic device OR 400 is replaced arithmetic logic device 204.Each N pass element N1 to NN all has a grid, and each grid all can receive a corresponding data sequence signal D1, D2 ... one of them of DN.The arbitrary signal of logic device OR 400 in data sequence signal D1 to DN carries out computing during for high level, then do not carry out computing when all sequences data-signal D1 to DN signal is low level.
The personage who is familiar with this skill only provides explanation arithmetic logic device 204 and can be any complicated logical operation circuit when understanding shown in logic device AND 300 and the logic device OR 400.Any suitable logic device AND combines all and can expect with logic device OR logic gate circuit, for instance, and multiple input multiplexer (muxes), multidigit scrambler or the like.Any desired simple to complex calculations logic device all applicable to arithmetic logic device 204, and can not have influence on the speed and the electrical source consumption of non-anti-phase dominoes bumper 200.No matter the structure of arithmetic logic device 204 why, and non-anti-phase dominoes bumper 200 shows a significantly short data-output time, and do not need output signal Q anti-phasely, the degree of stability of output signal Q do not compromised.
Though the present invention and purpose thereof, characteristic and advantage are described in detail, the present invention also may also include other embodiment and variation.In addition, though disclosed embodiment utilizes the element of metal-oxide semiconductor (MOS) kenel, it has comprised complementary metal oxide semiconductor and similar elements such as NMOS and PMOS transistor etc., it still can utilize the technology kenel and the framework of similar aspect or simulation to implement, such as dual-polarity elements or the like.
At last, though the present invention is for realizing the optimal mode of the object of the invention, what have the knack of that the personage of this technology should recognize is, it is not breaking away from as claims under the defined spirit of the present invention and scope, it can use the idea and the particular specific embodiment that are disclosed to be used as the basis immediately, carries out the design identical with purpose of the present invention or revises other structure.
Claims (14)
1. non-anti-phase dominoes bumper, it comprises:
The complementary paired arithmetic element of one response, one clock signal;
One arithmetic logic device, it is coupled on the interelement precharged node of this complementation paired arithmetic, and comes computing one logical function according at least one input data signal;
One storage level, it drives one first preparation output node, and this storage level includes and draws element and one first drop down element on one first, and this two elements is all in response to this precharged node, and this storage level also includes one second drop down element of this clock signal of response;
One keeps circuit, and it has an input end and is coupled to this first preparation output node, and an output terminal, and it drives one second preparation output node; And
One output stage, driving an output node, this output stage include all in response to this precharged node one second on draw element and one the 3rd drop down element, its also include all in response to the second preparation output node one the 3rd on draw element and one the 4th drop down element.
2. non-anti-phase dominoes bumper as claimed in claim 1 is characterized in that this complementation paired arithmetic element also includes:
One P pass element, it has a grid that receives this frequency signal, is coupled to the one source pole of a voltage source and is coupled to a drain electrode of this precharged node; And
One N pass element, it has a grid that receives this frequency signal, is coupled to the one source pole of an earth terminal and is coupled to a drain electrode of this arithmetic logic device.
3. non-anti-phase dominoes bumper as claimed in claim 1 is characterized in that this storage level comprises:
One P pass element, it has a grid that is coupled to this precharged node, and the one source pole and a drain electrode that is coupled to this first preparation output node that are coupled to a voltage source;
One the one N pass element, its have in order to a grid that receives this clock signal, be coupled to this first the preparation output node one the drain electrode and one source pole; And
One the 2nd N pass element, a drain electrode of this source electrode that it has the grid that is coupled to this precharged node, be coupled to a N pass element and the one source pole that is coupled to earth terminal.
4. non-anti-phase dominoes bumper as claimed in claim 1 is characterized in that this holding circuit comprises to be coupled to this first and second pair of phase inverters of preparation between the output node alternately.
5. as 1 described non-anti-phase dominoes bumper of claim the, it is characterized in that this output stage comprises:
One the one P pass element, it has a grid, an one source pole that is coupled to a voltage source and a drain electrode that is coupled to this output node that is coupled to this precharged node;
One the 2nd P pass element, it has a grid that is coupled to this second preparation output node, a drain electrode that is coupled to the one source pole of this voltage source and is coupled to this output node;
One the one N pass element, it has a grid that is coupled to this second preparation output node, a drain electrode and an one source pole that is coupled to this output node; And
One the 2nd N pass element, a drain electrode of this source electrode that it has the grid that is coupled to precharged node, be coupled to a N pass element and the one source pole that is coupled to earth terminal.
6. a buffer, it comprises:
One computing circuit, it can carry out preliminary filling to a first node when a clock signal is low level, and when this clock signal was high level, computing one logical function was in order to control the state of this first node;
One storage circuit, it is coupled to this first node and receives this clock signal, and this storage circuit can drive a Section Point to high level when this first node is low level, and when this first node and clock signal are high level, drive this Section Point to low level;
One keeps circuit, is coupled to this Section Point, and it can drive one the 3rd node to one and the anti-phase logic state of this Section Point; And
One output circuit is coupled to this first node and the 3rd node, and it can drive an output node to high level when this first or the 3rd node is low level, and when this first or the 3rd node is high level, drives this output node to low level.
7. buffer as claimed in claim 6 is characterized in that this computing circuit comprises:
One P pass element, it is coupled to this first node and can receives this clock signal, and this P pass element carries out preliminary filling to this first node when this clock signal is low level;
One logical circuit, it is coupled to this first node, and this logical circuit can carry out the computing of logical function according at least one input data signal; And
One N pass element, it is coupled to this logical circuit and can receives this clock signal, and this N pass element can order about this logical circuit when this clock signal is high level, carry out the computing of logical function.
8. buffer as claimed in claim 6 is characterized in that this storage circuit comprises:
One P pass element, it is coupled to this first and second node, and this P pass element is pulled to high level with this Section Point when this first node is reduced to low level;
One the one N pass element, it is coupled to this Section Point and can receives this clock signal; And
One the 2nd N pass element, it is coupled to a N pass element and this first node;
Wherein this first and second N pass element is pulled to low level with this Section Point together when this first node rises to high level and is pulled to high level because of responding this clock signal.
9. buffer as claimed in claim 6 is characterized in that this holding circuit comprises a pair of phase inverter that couples alternately that is coupled between this second and the 3rd node.
10. as 6 described buffers of claim the, wherein this output circuit comprises:
One the one P pass element, it can be pulled to high level with this output node when this first node is low level;
One the 2nd P pass element, it can be pulled to high level with this output node when the 3rd node is low level; And
First and second N pass element, it can be pulled to low level with this output node together when this first and the 3rd node is high level.
11. buffer memory one logical function and the method that produces a noninverting output signal, it comprises:
When a clock signal during, a first node is preset in one first logic state;
When this clock signal switches to one second logic state, a logical function is carried out computing to control the logic state of this first node;
Drive a Section Point to switching to its second logic state to respond this clock signal with the anti-phase logic state of this first node;
Keep this Section Point in its previous logic state that drives;
Drive one the 3rd node to a logic state anti-phase with this Section Point; And
State according to this first and the 3rd node drives an output node.
12. method as claimed in claim 11, it is characterized in that the default logic state that this first node is charged in advance a high level that comprises that this first node is carried out, and keep this Section Point and comprise that in its previous logic state that drives keeping circuit with one is coupled to this Section Point, and the content that drives the 3rd node comprises the state of this Section Point anti-phase in addition.
13. method as claimed in claim 11 is characterized in that the step that drives this Section Point comprises:
If this first node is a low level, then this Section Point is pulled to high level; And
If the state of clock signal and this first node is all high level, then this Section Point is pulled to low level.
14. method as claimed in claim 11 is characterized in that the step that drives this output node comprises:
When this first and the 3rd node arbitrary is low level, this output node is pulled to high level; And
When this first and the 3rd node is high level, this output node is pulled to low level.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/640,369 | 2003-08-13 | ||
| US10/640,369 US7193445B2 (en) | 2002-08-14 | 2003-08-13 | Non-inverting domino register |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1553453A true CN1553453A (en) | 2004-12-08 |
| CN100395698C CN100395698C (en) | 2008-06-18 |
Family
ID=34375727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100476531A Expired - Lifetime CN100395698C (en) | 2003-08-13 | 2004-05-27 | Non-inverting domino register |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100395698C (en) |
| TW (1) | TWI237265B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101001082B (en) * | 2006-01-14 | 2011-09-21 | 威盛电子股份有限公司 | Inverting dynamic register with data-dependent hold time reduction mechanism |
| CN102355254A (en) * | 2010-07-20 | 2012-02-15 | 威盛电子股份有限公司 | Non-clock-state regression domino logic gate and related integrated circuit and estimation method |
| CN102144263B (en) * | 2008-09-09 | 2014-10-22 | 高通股份有限公司 | Self reset clock buffer in memory devices |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6265899B1 (en) * | 1999-06-04 | 2001-07-24 | S3 Incorporated | Single rail domino logic for four-phase clocking scheme |
| US6191618B1 (en) * | 1999-07-23 | 2001-02-20 | Intel Corporation | Contention-free, low clock load domino circuit topology |
| US6560737B1 (en) * | 2000-02-16 | 2003-05-06 | Hewlett-Packard Development Company, L.P. | Method for adding scan controllability and observability to domino CMOS with low area and delay overhead |
| US6496038B1 (en) * | 2000-06-30 | 2002-12-17 | Intel Corporation | Pulsed circuit topology including a pulsed, domino flip-flop |
-
2004
- 2004-05-18 TW TW93113894A patent/TWI237265B/en not_active IP Right Cessation
- 2004-05-27 CN CNB2004100476531A patent/CN100395698C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101001082B (en) * | 2006-01-14 | 2011-09-21 | 威盛电子股份有限公司 | Inverting dynamic register with data-dependent hold time reduction mechanism |
| CN102144263B (en) * | 2008-09-09 | 2014-10-22 | 高通股份有限公司 | Self reset clock buffer in memory devices |
| CN102355254A (en) * | 2010-07-20 | 2012-02-15 | 威盛电子股份有限公司 | Non-clock-state regression domino logic gate and related integrated circuit and estimation method |
| CN102355254B (en) * | 2010-07-20 | 2014-02-12 | 威盛电子股份有限公司 | Non-clock-state regression domino logic gate and related integrated circuit and estimation method |
| CN103152031B (en) * | 2010-07-20 | 2015-12-02 | 威盛电子股份有限公司 | Without clock-state regression domino logic gate and relevant integrated circuit and evaluation method |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200506941A (en) | 2005-02-16 |
| CN100395698C (en) | 2008-06-18 |
| TWI237265B (en) | 2005-08-01 |
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