CN1198395C - Threephase half-track differential logic gate circuit - Google Patents
Threephase half-track differential logic gate circuit Download PDFInfo
- Publication number
- CN1198395C CN1198395C CN 01120654 CN01120654A CN1198395C CN 1198395 C CN1198395 C CN 1198395C CN 01120654 CN01120654 CN 01120654 CN 01120654 A CN01120654 A CN 01120654A CN 1198395 C CN1198395 C CN 1198395C
- Authority
- CN
- China
- Prior art keywords
- channel mos
- electric crystal
- output node
- phase
- sequential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The present invention discloses a three-phase half-rail passing gate differential logic circuit (HRPGDL). The present invention uses structures which are similar to a pair of intercoupling inverters for recirculating charges, and is matched with two electric crystals which are controlled by a first time sequence and an inverse first time sequence, and another two electric crystals which are controlled by an inverse second time sequence, so data transmission is controlled by multiple phases, and a passing gate is used for decreasing electric crystals and enhancing operating speed. The present invention has the advantage of high speed, and is suitable for voltage with low power supply; the power-delay product performance of the present invention is superior to other dynamic logic circuits.
Description
Technical field
The present invention relates to a kind of logical circuit, particularly about a kind of low-power and be three-phase (3-phase) half rail by the door a differential logic (Half-rail pass-gate differential logic, HRPGDL).
Background of invention
At present, for reaching low-power and high-speed purpose, have now and proposed multiple different sequential dynamic logic, as has a differential tandem voltage switch (differential cascadevoltage switch with pass-gate logic by gate logic, DVCSPG), the differential logic of electric charge recirculation (charger recycling differential logic, CRDL), half rail dynamic logic (halfrail dynamic logic, HRDL), and CMOS by door do not have a hypervelocity electric charge recirculation logic (CMOSPass-gate no-race charge-recycling logic, CPNCL) etc.The advantage of above-mentioned dynamic logic is high-speed, and has less latch (Latch) number.
In addition, CRDL, HRDL and CPNCL are to use the idea of electric charge recirculation so that power dissipation reaches minimum.But essential P channel mos (PMOS) electric crystal that uses high critical value of CRDL compares V so the voltage of n well will be raised to
DdTaller a lot; HRDL is because the skew of signal, thus bear the problem of assessment in advance, and then cause longer signal delay, and higher power--postpone product; Dynamically HRDL once was suggested to solve the problem of signal bias, but it not have to use by gate logic so that the number of electric crystal reaches minimum, and slightly was inferior to the present invention on the speed; CPNCL then can overcome this problem, but needed supply voltage 3V at least
Th(critical voltage) is not suitable for low voltage operating, and employed by gate logic, and design concept is different with the present invention, thus actuating force a little less than.
As shown in Figure 1, it has different sequential " clk " to reach " ein " for basic structure and the sequencing control figure thereof of existing HRDRDL in this structure, wherein " ein " produces from the gate of previous stage, so the gate for previous stage produces extra load, so that increase delay; And input signal may just reach input after sequential " clk " reaches " ein " signal, and the problem of assessment too early takes place.Another kind of dynamic logic is the differential tandem voltage switch (DVCSPG) that has by gate logic, the timely sequential mode of its basic structure as shown in Figure 2, this logic is earlier output node to be charged, and makes its voltage near V
Dd, but not 1/2V
Dd, cause it to have higher power dissipation and longer delay.
Summary of the invention
By above-mentioned analysis as can be seen, main purpose of the present invention is to provide a kind of three-phase half rail by the differential logical circuit of door, and it uses complementary metal oxide semiconductor (CMOS) processing procedure of standard, to avoid producing the problem of signal bias; And pass through the electric crystal number that the tree-shaped framework of gate logic can be saved its required use in this differential logical circuit.
Differential logical circuit between another object of the present invention is to provide a kind of speed three-phase half rail passing through faster makes it under identical supply voltage, with other logical circuit that uses identical CMOS processing procedure relatively down, of the present invention fastest; And be applicable to the low supply voltage that 2V is following simultaneously.
A further object of the present invention is to provide a kind of three-phase half rail by the differential logical circuit of door, its power--and the performance that postpones product is better than other dynamic logic circuit.
For achieving the above object, the invention provides a kind of three-phase half rail by the differential logical circuit of door, comprising:
First output node (Out) and second output node (Out);
The inverter that a pair of mutual coupling is closed is connected to this first and second output node;
Comprise a N channel mos (NMOS) electric crystal (18) in the inverter, this first and second output node of its source electrode and drain coupled;
N channel mos electric crystal 12 and P channel mos (PMOS) electric crystal 14 are connected to this with its drain electrode respectively mutual coupling are closed two pairs of source terminals of inverter and is connected to power supply or earth terminal with its source electrode; It is characterized in that:
N channel mos (NMOS) electric crystal 18 of this first and second output node of being coupled is subjected to anti-phase first sequencing control; Be connected to this respectively and the two pairs of source terminals of inverter closed in mutual coupling and the N channel mos electric crystal 12 and P channel mos (PMOS) electric crystal 14 of power supply or earth terminal is subjected to first sequential and anti-phase first sequencing control respectively;
Two N channel mos electric crystals 16,16 ' by anti-phase second sequencing control, its source electrode and drain electrode are coupled two groups respectively by gate logic tree and this first and second output node; These the two groups logics of being carried out according to institute's desire by N channel mos electric crystal by the gate logic tree are formed, and are to be responsible for transmitting the low level signal to give this first and second output node.
Described logical circuit is characterized in that: this is subjected to the N channel mos electric crystal 18 of anti-phase first sequencing control to can be P channel mos electric crystal, and by first sequencing control.
Described logical circuit, it is characterized in that: this is subjected to the N channel mos electric crystal 16,16 ' of anti-phase second sequencing control to can be P channel mos electric crystal, and by second sequencing control, simultaneously, these the two groups logics of being carried out according to institute's desire by P channel mos electric crystal by the gate logic tree are formed, and are to be responsible for transmitting the high levle signal to give this first and second output node.
Described logical circuit, it is characterized in that: this first sequential and anti-phase second sequential are all when hanging down logic level, electric charge recirculation at this output node, and be pre-charged to about 1/2 supply voltage, this is for the step of pre-charge, at this moment, input data arrival before first sequential and anti-phase second sequential uprise.
Described logical circuit is characterized in that: when this first sequential and anti-phase second sequential were high logic level, the input data can be closed the computing of inverter to carry out this mutual coupling by the N channel mos electric crystal by reverse second sequencing control.
Described logical circuit is characterized in that: this first sequential is high logic level, and this anti-phase second sequential is during for low logic level, with this output node locking, and at the state of this output node of input any change all can not the change.
The present invention is that a kind of new three-phase half rail is by door differential logical circuit (HRPGDL), the structure that it uses similar mutual coupling for electric charge recirculation to close inverter, and use leggy to come the control data transmission and use by gate logic to reduce the electric crystal number and to increase service speed.This heterogeneous method can be removed the problem of assessing too early among the HRDL effectively; With DVCSPG comparatively speaking owing to utilize the relation of half rail and electric charge recirculation, the power that HRPGDL consumed is still less.
Description of drawings
Fig. 1 is dual input NAND door and the sequential chart thereof that uses HRDL in the prior art.
Fig. 2 is for using dual input NAND door and the sequential chart thereof of dynamic DVCSPG.
Fig. 3 is for using dual input NAND door of the present invention and sequential chart thereof.
Fig. 4 passes through the algorithm of door tree for the HRPGDL of NAND door of the present invention.
Fig. 5 (a) is graph of a relation between the sequential of the present invention in the tandem logic.
Fig. 5 (b) is the three alternate graphs of a relation of the present invention in the tandem logic.
Fig. 5 (c) is that the present invention is with several dual inputs NAND door tandem output waveform and sequential schematic diagram together.
Fig. 6 (a) is HRDL, dynamically DVCSPG and HRPGDL be at V
DdDelay during=3V is for the graph of a relation of load capacitance.
Fig. 6 (b) is HRDL, dynamically DVCSPG and HRPGDL be at V
DdPower under the=3V--postpone the graph of a relation of product with respect to load capacitance.
Fig. 7 (a) is HRDL, dynamically DVCSPG and HRPGDL postpone the graph of a relation for supply voltage when the output capacitance of 50fF.
Fig. 7 (b) be HRDL, dynamically DVCSPG and HMGDL when the output capacitance of 50fF, power--postpone the graph of a relation of product with respect to supply voltage.
Fig. 8 (a) is cut apart for circuit and phase place that the present invention is applied to 4 radix-2 adders of pipeline.
Fig. 8 (b) is the output waveform of the 1110+0001 of Fig. 8 (a).
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
As shown in Figure 3, it is used for the logical circuit and the sequential chart of dual input and non-(NAND) door for the present invention uses HRPGDL, this logical circuit comprises first output node (Out) and second output node (Out), the inverter 10 that a pair of mutual coupling is closed is connected to this first and second output node, other has one to be subjected to N channel mos (NMOS) electric crystal 18 of anti-phase first sequential (φ 1) control to be coupled to first and second output node, and two NMOS electric crystals 12 that are subjected to first sequential (φ 1) and anti-phase first sequential (φ 1) control and PMOS electric crystal 14 are connected to this closes inverter 10 to mutual coupling the two pairs of source terminals and power end and earth terminal respectively, the existing HRDL of this similar, but the present invention need " clk " not reach the different sequential of " ein " and so in HRDL, so can therefore reduce load effect.Another difference is that the present invention (HRPGDL) uses NMOS by gate logic, but not the tree of the NMOS complementary logic in HRDL, and institute is so that the number of electric crystal reaches minimum, and increases the speed of circuit simultaneously.In order to reduce first previous stage owing to the relation by gate logic is affected signal, at this first and second output node and this mutual coupling is closed and respectively to add a NMOS electric crystal 16,16 ' by anti-phase second sequential (φ 2) control between the inverter 10, it is coupled two groups respectively by gate logic tree and first and second output node.
The mode of operation of this logical circuit can be divided into three steps: first step is the action of pre-charge, and at this moment when section, φ 1 and φ 2 are low logic level, therefore in the electric charge recirculation at output node place, and is pre-charged to about 1/2V
Dd, simultaneously, the input data uprise (becoming one by zero) and arrive before at φ 1.When φ 1 and φ 2 become high logic level, these data can by by the NMOS electric crystal 16,16 ' controlled of φ 2, and therefore carry out the computing that inverter 10 is closed in mutual coupling.Third step then is called " keeping " computing, when φ 1 is high logic level, and φ 2 during for low logic level, with the output node locking, and at the state of input any change all can not change output node.
For HRDL, the input data are to arrive in sequential and enable signal action back, and therefore the problem of assessment too early will take place.But HRPGDL of the present invention or dynamically data arrival earlier before assessment of HRDL then can be avoided this problem.As for the logic between HRPGDL and the dynamic HRDL is not the difference of logic tree shape architecture logic, and comprises the difference of phase place, and HRPGDL uses 3 phase places but not 4 phase places, therefore can accelerate its service speed.
Existing DVCSPG and HRPGDL of the present invention design are by the method difference of gate logic, the gate logic that passes through of DVCSPG may be by low or high voltage level, yet HRPGDL only need pass through low-voltage position standard, first output node and second output node are pulled to when hanging down logic level if it is former, inverter 10 is closed in this mutual coupling will be amplified to high levels to another, therefore can reduce the number of employed electric crystal.As the algorithm of the logic tree of the one dual input NAND door of display design among Fig. 4 and utilize principle of the present invention, also can use any other the logic of similar method design.
For tandem (cascade) logic, use three each stage given pipelineization, Fig. 5 (a) is the sequential of each switch in each stage, and the method for this stage connection, phase I is output as the input of second stage, second stage is output as the input of phase III, by that analogy to the n stage, Fig. 5 (b) is its three alternate graph of a relation, wherein φ 1, φ 2 and φ 3 are the main sequential in control stage 1 to 3, allow input signal by then being subjected to φ 2 respectively with the NMOS electric crystal that arrives output node, and the inversion signal of φ 3 and φ 1 is controlled; Each cycle can be divided into three parts " P ", " E " reaches " H ", and it is represented precharge respectively, assesses and keeps.In addition, since φ 2, φ 3 and φ 1 in stage 1,2 and 3, can't make each NMOS conducting simultaneously, needn't worry in the stage formerly incoherent signal will influence output waveform, in other words, can effectively overcome the shortcoming of transmitted in both directions in by door.
For the existing really different sequential dynamic logic of proof the present invention has preferable effect, use the execution of the dual input NAND door of HRDL as shown in Figure 1 to Figure 3, dynamic DVCSPG and HRPGDL to compare at this, its result is presented among Fig. 6 and Fig. 7, as shown in the figure, under the sequential of the CMOS technology of 0.35 micron (μ m) and 60MHz, use to have 0.75 micron NMOS and PMOS electric crystal with 2 microns channel widths respectively, simulate above-mentioned three kinds logical circuit; Wherein there is no two kinds of logical circuits of comparison CRDL and CPNCL, because the former needs quite high n well bias voltage, and the latter needs higher supply voltage, to produce good actuating force, so do not compare at this.Being to compare under the supply voltage of 3V among Fig. 6, postponing and power--the delay product is the function of output capacitance, wherein is defined as sequential or the rising of input data time of delay and holds and output arrival V
Dd90% or V
Dd10% between time; Be presented among Fig. 7 under the 50fF load, postpone and power--the product of delay is the function of supply voltage, via finding the delay of HRPGDL and power behind comparison two accompanying drawings--postpone product and be all the shortest or reckling, therefore, performance of the present invention is the dynamic logic circuit that obviously is better than other.
In addition, for the operation that proves three-phase HRPGDL is correct, simulation four tandem dual input NAND doors among the present invention, wherein input A and B link together (A=B), the input of the output feed-in second stage of phase I, and act in an identical manner second and third stage.Fig. 5 (c) shows the waveform of this sequential, in the input and output signal by stage 1 to the stage 3, can see that rising and fall delay are less than 0.3ns, are illustrated in V
DdUnder the situation under the=3V, when using 0.35 micron CMOS, frequency of operation may be higher than 1GHz.
The application of the differential logic of 42 radixes of display tube linearize (radix) adders (adder) among Fig. 8, shown in Fig. 8 (a), it shows the phase division of 4 adders, X0 wherein, Y0, Z0, S0, bit0 is a highest order, and when bits number increased, the transmission gate between φ 2 and φ 3 may essentially be adjusted.Fig. 8 (b) is the correct simulation output waveform of X=1110 and Y=0111 under the 0.75ns sequential cycle, and under this state, S3 must and reach bit0 by three transmission gates, and this is the longest propagation delay of expression.The example of lifting this adder is in order to illustrate that the present invention also can be applied in these adders.
Generally speaking, three-phase half rail of the present invention can be summarized down columns item advantage by the differential logical circuit of door:
(1) the CMOS processing procedure of use standard can avoid the problem of signal bias to produce.
(2) can save the electric crystal number of required use by the gate logic tree.
(3) under the supply voltage of 3V, use the logical circuit of identical CMOS processing procedure relatively more following, of the present invention fastest with other.
(4) the present invention also is applicable to the low supply voltage that is lower than 2V.
(5) power--the performance that postpones product is better than other dynamic logic.
The above only is several preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.
Claims (6)
1, a kind of three-phase half rail comprises by the differential logical circuit of door:
First output node (Out) and second output node (Out);
The inverter that a pair of mutual coupling is closed is connected to this first and second output node;
Comprise a N channel mos (NMOS) electric crystal (18) in the inverter, this first and second output node of its source electrode and drain coupled;
N channel mos electric crystal (12) and P channel mos (PMOS) electric crystal (14) are connected to this with its drain electrode respectively mutual coupling are closed two pairs of source terminals of inverter and is connected to power supply or earth terminal with its source electrode; It is characterized in that:
N channel mos (NMOS) electric crystal (18) of this first and second output node of being coupled is subjected to anti-phase first sequencing control; Be connected to this respectively and the two pairs of source terminals of inverter closed in mutual coupling and the N channel mos electric crystal (12) and P channel mos (PMOS) electric crystal (14) of power supply or earth terminal is subjected to first sequential and anti-phase first sequencing control respectively;
Two N channel mos electric crystals (16,16 ') by anti-phase second sequencing control, its source electrode and drain electrode are coupled two groups respectively by gate logic tree and this first and second output node; These the two groups logics of being carried out according to institute's desire by N channel mos electric crystal by the gate logic tree are formed, and are to be responsible for transmitting the low level signal to give this first and second output node.
2, logical circuit according to claim 1 is characterized in that: this is subjected to the N channel mos electric crystal (18) of anti-phase first sequencing control to can be P channel mos electric crystal, and by first sequencing control.
3, logical circuit according to claim 1, it is characterized in that: this is subjected to the N channel mos electric crystal (16,16 ') of anti-phase second sequencing control to can be P channel mos electric crystal, and by second sequencing control, simultaneously, these the two groups logics of being carried out according to institute's desire by P channel mos electric crystal by the gate logic tree are formed, and are to be responsible for transmitting the high levle signal to give this first and second output node.
4, logical circuit according to claim 1, it is characterized in that: this first sequential and anti-phase second sequential are all when hanging down logic level, electric charge recirculation at this output node, and be pre-charged to about 1/2 supply voltage, this is for the step of pre-charge, at this moment, input data arrival before first sequential and anti-phase second sequential uprise.
5, logical circuit according to claim 1, it is characterized in that: when this first sequential and anti-phase second sequential are high logic level, the input data can be closed the computing of inverter to carry out this mutual coupling by the N channel mos electric crystal by reverse second sequencing control.
6, logical circuit according to claim 1, it is characterized in that: this first sequential is high logic level, and this anti-phase second sequential is during for low logic level, with this output node locking, and at the state of this output node of input any change all can not the change.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01120654 CN1198395C (en) | 2001-07-23 | 2001-07-23 | Threephase half-track differential logic gate circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01120654 CN1198395C (en) | 2001-07-23 | 2001-07-23 | Threephase half-track differential logic gate circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1399406A CN1399406A (en) | 2003-02-26 |
| CN1198395C true CN1198395C (en) | 2005-04-20 |
Family
ID=4664292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01120654 Expired - Fee Related CN1198395C (en) | 2001-07-23 | 2001-07-23 | Threephase half-track differential logic gate circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1198395C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101951256B (en) * | 2010-09-19 | 2012-07-04 | 宁波大学 | Single-phase clock pass transistor adiabatic logic circuit, full adder and 5-2 compressor |
| CN104518779A (en) * | 2014-12-03 | 2015-04-15 | 宁波大学 | Pass transistor current mode mixed logic circuit |
-
2001
- 2001-07-23 CN CN 01120654 patent/CN1198395C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1399406A (en) | 2003-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1209875C (en) | Buffer capable of regulating work period and its operation method | |
| KR19980014135A (en) | Charge recycling differential logic (CRDL) circuits and devices using the circuits | |
| US6590425B2 (en) | Semiconductor integrated circuit apparatus | |
| CN105162438A (en) | TSPC (True Single Phase Clock) type data flip-flop (DFF) capable of reducing glitch | |
| US6359477B1 (en) | Low power driver design | |
| CN1707949A (en) | Semiconductor integrated circuit | |
| CN109039322A (en) | A method of reducing CMOS reverser short circuit current | |
| CN1198395C (en) | Threephase half-track differential logic gate circuit | |
| JP2000235479A (en) | Method and device for executing sum and comparison arithmetic operation | |
| Bahrami et al. | A new approximate sum of absolute differences unit for bioimages processing | |
| KR101967872B1 (en) | Ternary multiplier | |
| US7603398B2 (en) | Data converter and a delay threshold comparator | |
| Sotiriadis et al. | Analysis and implementation of charge recycling for deep sub-micron buses | |
| CN102394637B (en) | Anti-differential power attack ternary counter based on sense amplification logic | |
| Wang et al. | A high-speed single-phase-clocked CMOS priority encoder | |
| US6785703B2 (en) | Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology | |
| MOHAMMADZADEH et al. | State of art design of novel adder modules for future computing | |
| Bosco et al. | Fundamental Flip-Flop Design: Comparative Analysis | |
| JP3216409B2 (en) | Semiconductor integrated circuit device | |
| Cheng et al. | The improvement of conditional sum adder for low power applications | |
| CN1808904A (en) | Novel anti-noise high-speed domino circuit | |
| Upadhyay et al. | Investigation of power on silicon adiabatic for VLSI applications | |
| Ahmed et al. | Design, simulation, and investigation of basic logic gates by using NAND logic gate | |
| Raj et al. | High speed controllable inverter for adder-subtractor in QCA | |
| CN1953325A (en) | CMOS level shift semi-dynamic trigger of conditional discharge and pulse drive |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050420 Termination date: 20150723 |
|
| EXPY | Termination of patent right or utility model |