CN1953325A - CMOS level shift semi-dynamic trigger of conditional discharge and pulse drive - Google Patents

Abstract

The invention belongs to the technical field of flip-flops for CMOS level conversion, and is characterized in that the flip-flops include conditional switches, conditional discharge circuits, hold circuits, data latch circuits, clock pulse circuits and state signal output circuits, wherein The conditional switch controls the discharge of the internal node charge according to the output feedback signal and the input data signal, eliminating redundant inversion; the data latch circuit controls the charging and discharging conditions through state feedback, and latches the data at the same time; the clock pulse circuit controls the flip-flop only when the clock The instant opening of the rising edge of the clock eliminates the error inversion caused by data changes during the high level of the clock; due to the use of output feedback and the elimination of redundant inversion mechanisms, the present invention has the characteristics of low power consumption and low leakage current.

Description

Conditional discharge and pulse-driven CMOS level-shifting half-motion flip-flop

technical field

The technical field of direct application of the "conditional discharge and pulse-driven CMOS level shifting semi-dynamic flip-flop" is the design of integrated circuits with multiple power supply voltages. The proposed circuit is a kind of CMOS flip-flop circuit unit for low voltage to high voltage conversion suitable for low swing clock network and low swing data signal.

Background technique

With the progress of CMOS integrated circuit manufacturing process, the scale and complexity of integrated circuits are increasing day by day, and the power consumption and heat dissipation of integrated circuits have been paid more and more attention from industry and academia. The power consumption sources of CMOS integrated circuits mainly include dynamic power consumption, static power consumption, short-circuit current power consumption and leakage current power consumption. For now, the dynamic power consumption of integrated circuits still accounts for the main part. Under certain circuit performance constraints, the dynamic power consumption P _Dynamic of a CMOS integrated circuit can be expressed as:

${\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; Dynamic</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; f</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; dd</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

in $C_{\mathrm{eff}}=\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}{a}_i{k}_i{C}_i.$

Here, f is the operating frequency of the circuit, a _i is the flip probability of the signal at node i, k _i is the voltage swing coefficient at node i (if it is full swing, then k _i =1), and C _i is node i The total capacitance at , V _dd is the supply voltage. It can be seen from formula (1) that reducing a _i , C _i , V _dd and _ki can reduce the dynamic power consumption of the circuit. However, since the dynamic power consumption is quadratically dependent on the power supply voltage, reducing the power supply voltage can greatly reduce the dynamic power consumption. As a result, technologies have emerged that allow multiple supply voltages in one integrated circuit, for example, two supply voltages. Use VDDL to represent the low-swing power supply voltage. VDDH represents the high-swing supply voltage. Figure 1 shows a block diagram of a multiple supply voltage design.

In the design of integrated circuits with multiple supply voltages, the level shifter is an indispensable circuit unit. They are placed between the low power supply voltage part unit and the high power supply voltage part unit as an interface circuit. Without them, the PMOS transistors in the high supply voltage part of the unit cannot be completely turned off due to being directly driven by the signal of the low supply voltage, resulting in a large leakage current. In order to reduce the impact of inserting level converters, the clustered voltage scaling technology (clustered voltage scaling) was proposed by researchers to reduce the area and delay losses caused by level converters (see literature K.Usami and M. Horowitz, "Clustered voltage scaling technique for low-power design," in Proc. Int. Symp. Low Power Design, Dana Point, CA, Apr.1995, pp.3-8.). In this approach, the level shifter is integrated inside the flip-flop.

Figure 2 shows a schematic diagram of the flip-flop circuit unit. As shown in Figure 3, the basic circuit structure of the traditional flip-flop circuit unit widely used in the design of digital circuit standard cell library, here is the flip-flop circuit unit DFNRB1 with complementary output and rising edge trigger in Chartered 0.18μm process digital standard cell library As an example (see Manual of "Chartered0.18micron, 1.8volt Optimum Silicon SC Library CSM18OS120", Version 1.2 February 2003.). The main feature of this circuit structure is that the circuit structure is relatively simple, but it is not suitable for the design of a low clock signal swing clock network system. At the same time, because each clock signal inversion will cause the inversion of the internal nodes of the circuit, the power consumption of the circuit is relatively large. In the design of high-performance integrated circuits, dynamic or semi-dynamic flip-flops are widely used because of their high speed and other characteristics. Figure 4 is an implicit pulse-driven semi-dynamic flip-flop IP_DCO (see the literature James Tschanz et al.,"Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-llops for high-performancemicroprocessors,"in Proc. ISLPED'01, August 6-7, pp. 147-152.).

The biggest feature of this flip-flop circuit is its fast speed and negative settling time (thus having better clock borrowing ability). However, in the IP_DCO circuit, its internal nodes need to be driven by a PMOS whose gate is connected to the clock, so in the case of low clock swing in a multi-supply voltage design environment, a huge leakage current is prone to occur. Because the PMOS tube cannot be completely turned off at this time. Another problem with IP_DCO is redundant flipping of internal nodes. When the input data signal is always high, the internal nodes are prone to continuous high-low switching, wasting a lot of power consumption. In short, none of these circuits can work in the case where both the data signal and the clock signal are at low level, that is to say, none of them can be used as an interface circuit for level conversion. At present, there are few flip-flops that can be used as high-low level conversion functions. Fujio Ishihara et al. have proposed a dynamic precharge flip-flop PPR that can be used for level conversion (see the document Fujio Ishihara, Farhana Sheikh, and Borivoje Nikolic, "Level conversion for dual-supply systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 2, Feb. 2004). However, this circuit uses a lot of transistors, which is relatively complicated, and there are inevitably burrs in the internal nodes, which leads to a large waste of power consumption.

Contents of the invention

The object of the present invention is to propose a clock pulse-driven CMOS semi-dynamic flip-flop LH_IP_DCO_CD and LH_SDFF_CD with an integrated level conversion function. At the same time, the circuit adopts a new conditional discharge mechanism and a charging mechanism, which eliminates the internal redundancy of the flip-flop. The leakage current is reduced, and the power consumption of the circuit is reduced. The structure is shown in Fig. 6 and Fig. 7 . For LH_IP_DCO_CD, its explicit pulse driving circuit is shown in Figure 9 and Figure 10. Among them, FIG. 9 is a clock single-edge trigger, and FIG. 10 is a clock double-edge trigger.

The beneficial effects of the present invention are:

Compared with traditional digital standard unit flip-flop circuits DFNRB1 and PPR flip-flop circuits, the LH_IP_DCO_CD and LH_SDFF_CD flip-flops proposed by the present invention can be used as interface circuits in the environment of integrated circuits with multiple power supply voltages, and at the same time, the circuit eliminates internal redundant flip-flops , which reduces the dynamic power consumption, the proposed circuit technology is very suitable as a digital circuit standard unit and applied in the design of multi-supply voltage low-power integrated circuits.

Description of drawings

Figure 1. A block diagram of design ideas for modern multi-supply voltage integrated circuits.

Figure 2. Schematic diagram of the flip-flop circuit unit, D is the data signal input terminal, CLK is the clock signal input terminal, Q and Q _b are complementary signal output terminals;

Figure 3. The circuit structure diagram of the flip-flop circuit unit DFNRB1 with complementary output and rising edge trigger in Chartered 0.18um process digital standard cell library;

Figure 4. Traditional IP_DCO flip-flop circuit structure diagram;

Figure 5. Traditional SDFF flip-flop circuit structure diagram;

Fig. 6. Circuit structure diagram of LH_IP_DCO_CD flip-flop according to the present invention. Among them, the substrates of the PMOS transistors p1, p2, and p3 are connected to VDDH. The substrates of the NMOS transistors n1, n2, n3, n4, n5, n6, n7, and n8 are grounded. The power supply voltage of the inverters inv1, inv5 and inv6 is VDDH. The power supply voltage of the inverters inv2, inv3 and inv4 is VDDL.

Fig. 7. Circuit structure diagram of LH_SDFF_CD flip-flop according to the present invention. Among them, the substrates of the PMOS transistors p1, p2, and p3 are connected to VDDH. The substrates of the NMOS transistors n1, n2, n3, n4, n5, n6, n7, and n8 are grounded. The power supply voltage of the inverters inv1, inv5 and inv6 is VDDH. The power supply voltage of the inverters inv2, inv3 and inv4 is VDDL. The power supply voltage of the NAND gate NAND2 is VDDL.

Fig. 8. HSPICE simulation diagram of dual power supply voltages of the LH_IP_DCO_CD flip-flop according to the present invention.

Fig. 9. The structure diagram of the explicit clock pulse driving circuit of the LH_IP_DCO_CD flip-flop according to the present invention, which is triggered by a single edge of the clock. Among them, the substrates of the PMOS transistors p1, p2, and p3 are connected to VDDH. The substrates of the NMOS transistors n2, n3, n4, n5, n7, and n8 are grounded. The power supply voltage of the inverters inv1, inv5 and inv6 is VDDH. The power supply voltage of the inverters inv2, inv3, inv4 and inv9 is VDDL. The power supply voltage of the NAND gate NAND1 is VDDL.

Fig. 10. The structure diagram of the explicit clock pulse driving circuit of the LH_IP_DCO_CD flip-flop according to the present invention, which is triggered by both clock edges. Among them, the substrates of the PMOS transistors p1, p2, and p3 are connected to VDDH. The substrates of PMOS transistors p9 and p10 are connected to VDDL. The substrates of the NMOS transistors n2, n3, n4, n5, n7, n8, n9 and n10 are grounded. The power supply voltage of the inverters inv1, inv5 and inv6 is VDDH. The power supply voltage of the inverters inv2, inv3, inv4 and inv9 is VDDL.

Figure 11. Simulation waveform diagram of a single power supply voltage for a traditional IP_DCO circuit.

Figure 12. For the dual power supply voltage simulation waveform diagram of the traditional IP_DCO circuit, D and clk are low-swing power supply voltages, and the main circuit is high-swing power supply voltage.

Detailed ways

The technical solution of the present invention to solve the technical problem is: CMOS semi-dynamic flip-flops LH_IP_DCO_CD and LH_SDFF_CD driven by conditional discharge and clock pulse, as shown in FIG. 6 and FIG. 7 . They all have the characteristics of high-low level conversion and the use of conditional discharge technology to reduce the power consumption of the flip-flop circuit itself.

First analyze LH_IP_DCO_CD. Compared with IP_DCO, the charging here is realized by the p1 transistor. At the same time, because its gate is connected to the high-swing output feedback signal HQN, p1 can be completely turned off, thereby greatly reducing the leakage current. Different from the traditional IP_DCO circuit, the data signal input tube n3 here is connected to n4, and the conditional switch composed of n5 controls the discharge of internal node charges. When HQN is high and D is high, the first stage of the circuit is discharged, and the second stage is turned off because DN is low n8, so that HQN becomes low and HQ becomes high, realizing the function of flip-flop latching D. Since HQN is low at this time, the internal node X starts charging again until VDDH is high. When HQ is high and D is low, the internal node does not discharge, and the second stage starts to turn on to make HQN high and HQ low, realizing the function of flip-flop latching D. Since the internal node is often high, the holding circuit inside the circuit is composed of an inverter and a PMOS transistor, such as inv1 and p2. The conditional discharge function here means that compared with the traditional IP_DCO flip-flop, when the D input signal continues to be high, the internal nodes of IP_DCO will continue to charge and discharge, resulting in additional power loss. This charge and discharge is redundant, and the newly proposed LH_IP_DCO_CD can eliminate this redundant flip. When D is continuously high, HQ is continuously high, and HQN is continuously low, so that the n3 tube is always cut off, and the original discharge and recharge of the first stage circuit is not performed, eliminating the redundant flip of the left branch. The clock signal of this circuit is connected to NMOS transistors n1 and n6 through a VDDL driven inverter inv2, inv3, inv4. At the same time, the clock is directly connected to NMOS transistors n2 and n7. Therefore, the opening of the first-level branch and the second-level branch is only at the moment of the rising edge of the clock. This circuit prevents false flips caused by changes in D while the clock is high, ensuring proper functionality.

Another form of LH_IP_DCO_CD driven by an explicit clock pulse is shown in Figure 9, where the clock signal clk first passes through a VDDL-driven clock generation circuit to generate a corresponding clock pulse clk_pulse, and then clk_pulse is connected to the main flip-flop circuit. Since there may be many flip-flops on the chip, this clk_pulse can be used as a common clock pulse signal for local circuits, thereby further reducing power consumption. The principle of the pulse circuit is to let the clk signal and the clk delayed inversion signal pass through a NAND gate and an inverter to obtain the clk signal pulse.

In order to further increase the information transmission rate, improvements can be made to the clock pulse signal so that pulse signals can be generated on both edges of the clock clk. The pulse circuit is shown in Figure 10.

Since there is one less NMOS transistor in the discharge branch of the internal circuit, the internal discharge speed of the LH_IP_DCO_CD flip-flop driven by the explicit clock pulse is faster, and the delay from clk_pulse to D is reduced.

The same analysis can also be used for LH_SDFF_CD. Compared with SDFF, the charging here is realized by the p1 transistor, and because its gate is connected to a high-swing output signal, p1 can be completely turned off, thereby greatly reducing the leakage current. Different from the traditional SDFF circuit, the data signal input tube n2 here is connected to n4, and the conditional switch composed of n5 controls the discharge of internal node charges. When HQN is high and D is high, the first stage of the circuit is discharged, and the second stage is turned off because DN is low n8, so that HQN becomes low and HQ becomes high, realizing the function of flip-flop latching D. Due to the effect of the n3 tube and its gate control voltage, the n3 tube is turned off, and because HQN is low at this time, the internal node X starts charging again until VDDH is high. When HQ is high and D is low, the internal node does not discharge, and the second stage starts to turn on to make HQN high and HQ low, realizing the function of flip-flop latching D. Since the internal node is often high, the holding circuit inside the circuit is composed of an inverter and a PMOS transistor, such as inv1 and p2. The conditional discharge function here means that compared with the traditional SDFF flip-flop, when the D input signal continues to be high, the SDFF internal node will continue to charge and discharge, resulting in additional power loss. This charge and discharge is redundant, and the newly proposed LH_SDFF_CD can eliminate this redundant flip. When D is continuously high, HQ is continuously high, and HQN is continuously low, so that the n2 tube is always cut off, and the original discharge and recharge of the first-stage circuit is not carried out, eliminating the redundant flip of the left branch. The clock signal of this circuit is connected to the NMOS transistor n6 through a VDDL-driven inverter inv2, inv3, and inv4. At the same time, the clock signal is also directly connected to the NMOS transistor n7. Therefore, the opening of the second-level branch is only at the moment of the rising edge of the clock. This circuit prevents false flips caused by changes in D while the clock is high, ensuring proper functionality.

Essential technical feature of the present invention is:

1. The circuit can be driven by a low-swing clock signal and input by a low-swing data signal, while outputting a high-swing signal, which is suitable as an interface circuit in a multi-supply voltage ready-made circuit design.

2. The trigger circuit adopts the conditional discharge control circuit controlled by the input data signal D and the output HQ, HQN feedback to complete the control of the original input D signal node.

3. The internal charging of the flip-flop is controlled by the output feedback signal HQN, which eliminates unnecessary redundant flipping, thereby reducing dynamic power consumption. At the same time, because the gate of the charging PMOS transistor is HQN at this time. Its high level is a high-swing signal, thus reducing leakage current.

4. Since the internal node X of the flip-flop is always kept high, the internal level holding circuit is simplified as an inverter plus a PMOS transistor, thereby reducing power consumption.

5. The clock is linked to the gates of two series-connected NMOS transistors in the second stage of the circuit through an inverter composed of an odd number of inverters driven by VDDL. In the internal clock pulse window, the discharge of the internal node of the flip-flop is controlled.

In order to show the performance characteristics of the LH_IP_DCO_CD and LH_SDFF_CD flip-flops proposed by the present invention, we adopt the HJTC 1.8-V 0.18μm process, take LH_IP_DCO_CD as an example, and use the circuit simulation tool HSPICE to simulate the circuit structure. Figure 8 shows the waveform of the flip-flop when it is working properly. Here the high power supply voltage VDDH is 1.8V, and the low power supply voltage VDDL is set to 1V. The input clock signal is VDDL signal, the clock frequency is 100MHz, and the duty cycle is 50%. The input data signal is also a VDDL signal, the signal change frequency is 20MHz, and the duty cycle is 50%. It can be seen that the output HQ and HQN have successfully completed their functions, and the high level is VDDH. Likewise, for conventional circuit IP_DCO. When only one power supply voltage is used, as shown in Figure 11, it can be clearly seen that when the input data D is constant high, there is a redundant flip inside the circuit. When the traditional IP_DCO is used in a multi-supply voltage design, the function of the flip-flop is completely lost, as shown in Figure 12. However, the present invention does not have the above problems.

Claims (4)

1. A conditional discharge and pulse-driven CMOS level shift semi-dynamic flip-flop, characterized in that the flip-flop contains a conditional switch, a conditional discharge circuit, a hold circuit, a data latch circuit, a clock pulse circuit and a state signal output circuit, wherein : The conditional discharge circuit is composed of PMOS transistor p1, NMOS transistor n3, NMOS transistor n2, and NMOS transistor n1 in series. The source of the p1 tank is connected to the high-swing power supply voltage VDDH, the source of the n1 transistor is grounded, and the gate of the n2 The pole is connected to clk, the gate of n1 is connected to clkN, The conditional switch is composed of NMOS transistors n5 and n4. The source of the n5 transistor is connected to the source of the n4 transistor and connected to the gate of the n3 transistor. The drain of the n5 transistor is connected to the input signal D, and the gate of the n5 transistor is connected to The output feedback signal HQN, the drain of the n4 tube is connected to the input ground signal 0, the gate of the n4 tube is connected to the output feedback signal HQ, The holding circuit is composed of an inverter inv1 and a PMOS transistor p2. The input of the inverter is connected to the internal node X, and the output is connected to the gate of the p2 transistor. The source of the p2 transistor is connected to VDDH, and the drain of the p2 transistor is connected to X. The data latch circuit is composed of PMOS transistor p3, NMOS transistors n8, n7, and n6 in series in sequence, where the gate of p3 is connected to the internal node X, the drain of p3 is connected to the output signal HQ, and the source of p3 is connected to VDDH, the gate of n8 is connected to the inverted signal DN of the D signal, the gate of n7 is connected to the clock signal clk, the gate of n6 is connected to clkN, The clock pulse circuit is composed of inverters inv2, inv3, and inv4 connected in series in sequence, where the input of inv2 is clk, and the output of inv4 is clkN, The state signal output circuit is composed of inverters inv5 and inv6 connected in parallel in opposite directions. The output of inverter inv5 is connected to the input of inverter inv6 to form a signal HQN, and the input of inverter inv5 is connected to the output of inverter inv6. forming signal HQ, The substrates of all the above-mentioned PMOS transistors are connected to the power supply voltage VDDH, and the substrates of all the NMOS transistors are grounded. The power supply voltage of the inverters inv1, inv5, and inv6 is VDDH, and the power supply voltage of the inverters inv2, inv3, and inv4 is VDDL. 2. The conditional discharge and pulse-driven CMOS level shift semi-dynamic flip-flop according to claim 1, wherein the clock pulse signal forming circuit is powered by VDDL inverters inv2, inv3, inv4, and The non-gate NAND1 and inv9 are connected in series, where the input terminal of inv2 and the other input terminal of NAND1 are connected to Clk, the output terminal of inv9 is the Clk_Pulse signal, and the Clk_Pulse signal is connected to the gates of n2 and n7 respectively, and the source of n2 is short-circuited to n1 It is directly grounded, and the source of n7 is short-circuited to n6 and directly grounded. 3. The conditional discharge and pulse-driven CMOS level-shifted half-dynamic flip-flop according to claim 1, characterized in that, Connect in2, inv3, inv4 inverters in series, PMOS transistor p9 and NMOS transistor n9, the source and drain of the two are connected, the gate of n9 is connected to the input of inv4, and the gate of p9 is connected to the inverter The output terminal of inv4, the PMOS transistor p10 and the NMOS transistor n10, the source and the drain of the two are connected, the gate of the n10 transistor is connected to the output terminal of inv4, and the gate of p10 is connected to the input terminal of the inverter inv4, The input terminal of the inverter inv9 is connected to the sources of n9, p9, n10 and p10, the output of inv9 is the signal Clk_Pulse, the drains of n9 and p9 are connected to the clk signal, and the drains of n10 and p10 are connected to the output of inv2. The source of the n2 tube is directly grounded after shorting the n1 tube, the gate of the n2 tube is connected to the signal Clk_Pulse, the source of the n7 tube is directly grounded after the n6 tube is shorted, and the gate of the n7 tube is connected to the signal Clk_Pulse. 4. The conditional discharge and pulse-driven CMOS level-shifted half-dynamic flip-flop according to claim 1, characterized in that, In the conditional switch, the sources of n4 and n5 are connected to the gate of n2 to replace the signal clk input to the gate of n2, the gate of p1 is connected to HQN, and the gate of n1 is connected to the clk signal, The clock pulse circuit is composed of inv2, inv3, inv4 and NAND gate NAND2 connected in series in sequence. The output of the NAND gate NAND2 is connected to the gate of n3, one input terminal of NAND2 is connected to the internal node X, the other input terminal of NAND2 is connected to the output terminal of inv3, and the gate of n6 is connected to the output signal of inv4.

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