CN1953325A - CMOS level shift semi-dynamic trigger of conditional discharge and pulse drive - Google Patents

Abstract

The invention relates to a trigger used in CMOS voltage conversion. Wherein, it is characterized in that said trigger contains condition switch, condition discharge circuit, holding circuit, data latch circuit, time impulse circuit, and state signal output circuit; the condition switch based on output feedback signal and input data signal controls the discharge of internal node charge, to eliminate abundant turnover; the data latch circuit via state feedback controls the condition of charge and discharge, and latch data; the time impulse circuit controls the trigger to be opened at the ascending edge of time, to eliminate error turnover caused by data change at high voltage period; therefore, the invention has low power consumption and low leakage current.

Description

The CMOS level shift semi-dynamic trigger of condition discharge and pulsed drive

Technical field

" the CMOS level shift semi-dynamic trigger of condition discharge and pulsed drive " direct applied technical field is the integrated circuit (IC) design of multi-power source voltage.The circuit that proposes is that a class is applicable to low amplitude of oscillation clock network, low amplitude of oscillation data-signal be used for the CMOS flip-flop circuit unit of low-voltage to the high voltage conversion.

Background technology

Along with the progress of CMOS integrated circuit fabrication process, the scale and the complexity of integrated circuit increase day by day, and power consumption of integrated circuit and heat dissipation problem more and more obtain the attention from industrial quarters and academia.CMOS power consumption of integrated circuit source mainly contains dynamic power consumption, quiescent dissipation, short circuit current power consumption and leakage current power consumption.For now, the dynamic power consumption of integrated circuit still accounts for major part.Under certain circuit performance constraint, the dynamic power consumption P of CMOS integrated circuit _DynamicCan be expressed as:

$P_{\mathrm{Dynamic}}=f{C}_{\mathrm{eff}}{V}_{\mathrm{dd}}^2---\left(1\right)$

Wherein $C_{\mathrm{eff}}=\underset{i=1}{\overset{N}{\mathrm{\Σ}}}{a}_i{k}_i{C}_i.$

Here, f is the operating frequency of circuit, a _iBe the upset probability of the signal of i node, k _iBe node i place voltage swing coefficient (if full swing, then k _i=1), C _iBe the total capacitance at node i place, V _DdBe supply voltage.From formula (1), as seen, reduce a _i, C _i, V _DdAnd k _iAll can reduce the dynamic power consumption of circuit.Yet because dynamic power consumption and supply voltage are square dependences, therefore reducing supply voltage can reduce dynamic power consumption greatly.So, allow the technology of a plurality of supply voltages in the integrated circuit to arise at the historic moment, such as containing two supply voltages.Represent low amplitude of oscillation supply voltage with VDDL.VDDH represents high amplitude of oscillation supply voltage.Fig. 1 has shown a kind of block diagram of multi-power source voltage design.

In the integrated circuit (IC) design of multi-power source voltage, level translator is indispensable circuit unit.They are placed between low supply voltage part unit and the high power supply voltage part unit as interface circuit.If without them, then the PMOS transistor in the high power supply voltage part unit is owing to directly driven by the signal of low supply voltage, can not thoroughly turn-off and causes occurring big leakage current.Insert the influence that level translator brings in order to reduce, lumped voltage reduces that technology (the clustered voltage scaling) person of being studied puts forward to be used to reduce area that level translator brings and the loss of time-delay (is seen document K.Usami and M.Horowitz, " Clustered voltage scaling technique for low-power design; " in Proc.Int.Symp.LowPower Design, Dana Point, CA, Apr.1995, pp.3-8.).In this method, level translator has been integrated in trigger inside.

What Fig. 2 showed is the flip-flop circuit cell schematics.Be illustrated in figure 3 as the traditional flip-flop circuit unit basic circuit structure that is widely used in the design of digital circuit standard cell lib, here with complementary output in the Chartered 0.18 μ m technology digital standard cell library, the flip-flop circuit cells D FNRB1 that rising edge triggers is example explanation (seeing document Manual of " Chartered0.18micron; 1.8volt Optimum Silicon SC Library CSM18OS120 ", Version 1.2 February 2003.).The main feature of sort circuit structure is that circuit structure is fairly simple, but is not suitable for the design of low-clock signal excursion clock network system, because clock signal upset each time all can cause the upset of circuit internal node, circuit power consumption is bigger simultaneously.In high performance integrated circuit design, dynamically or semi-dynamic trigger be used widely because of its characteristic such as high-speed.As semi-dynamic trigger IP_DCO (see document James Tschanz et al., " the Comparative delayand energy of single edge-triggered ﹠amp of Fig. 4 for a kind of implicit expression pulsed drive; Dual edge-triggered pulsed tlip-llops for high-performancemicroprocessors, " in Proc.ISLPED ' 01, August 6-7, pp.147-152.).

The maximum characteristics of this flip-flop circuit are that speed is fast, have negative settling time (using ability thereby have better clock) simultaneously.But in the IP_DCO circuit, its internal node need drive by the PMOS of a grid connection clock, therefore under low clock swing range situation under the multi-power source voltage design environment, occurs huge leakage current easily.Because this moment, the PMOS pipe can not turn-off fully.Another problem of IP_DCO is the redundancy upset of internal node.When input data signal perseverance when being high, internal node continues easily does the height conversion, wastes a large amount of power consumptions.In a word, these circuit all can not be operated in data-signal and clock signal and be low level situation, that is to say that they all can not be as the interface circuit of level conversion.At present can be also seldom as the trigger of high-low level translation function.People such as Fujio Ishihara proposed a kind of dynamic preliminary filling trigger PPR that can be used for level conversion and (saw document Fujio Ishihara, Farhana Sheikh, and Borivoje Nikolic, " Level conversionfor dual-supply systems; " IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.12, No.2, Feb.2004).But a lot of transistors of this circuit, more complicated, and inevitably there is burr in internal node, thus have bigger power wastage.

Summary of the invention

The objective of the invention is to propose CMOS semi-dynamic trigger LH_IP_DCO_CD and LH_SDFF_CD that a kind of clock pulse of integrated level conversion function drives, simultaneously, circuit adopts new condition discharge mechanism and charging mechanism, eliminate the built-in redundancy upset of trigger and reduced leakage current, reduced the power consumption of circuit, structure as shown in Figure 6 and Figure 7.For LH_IP_DCO_CD, the circuit of its explicit pulse drive mode is Fig. 9 and shown in Figure 10.Wherein, Fig. 9 is that clock is monolateral along triggering, and Figure 10 is that clock is bilateral along triggering.

The invention has the beneficial effects as follows:

With traditional digital standard unit triggers device circuit DFNRB1, the PPR flip-flop circuit relatively, LH_IP_DCO_CD and LH_SDFF_CD trigger that the present invention proposes can be established in the environment as interface circuit at the integrated circuit of multi-power source voltage, simultaneously this circuit for eliminating the built-in redundancy upset, reduced dynamic power consumption, the circuit engineering that is proposed is suitable as the digital circuit standard cell and is applied in the design of multi-power source voltage low power consumption integrated circuit very much.

Description of drawings

Fig. 1. the design philosophy block diagram of modern multi-power source voltage integrated circuit.

Fig. 2. the flip-flop circuit cell schematics, D is the data-signal input, CLK is a clock signal input terminal, Q and Q _bBe the complementary signal output;

The flip-flop circuit cells D FNRB1 circuit structure diagram that complementary output and rising edge trigger in Fig. 3 .Chartered 0.18um technology digital standard cell library;

Fig. 4. traditional IP_DCO flip-flop circuit structure chart;

Fig. 5. traditional SDFF flip-flop circuit structure chart;

Fig. 6. LH_IP_DCO_CD flip-flop circuit structure chart of the present invention.PMOS transistor p1 wherein, p2, the substrate of p3 meets VDDH.Nmos pass transistor n1, n2, n3, n4, n5, n6, n7, the substrate ground connection of n8.Inverter inv1, inv5, the supply voltage of inv6 are VDDH.Inverter inv2, inv3, the supply voltage of inv4 are VDDL.

Fig. 7. LH_SDFF_CD flip-flop circuit structure chart of the present invention.PMOS transistor p1 wherein, p2, the substrate of p3 meets VDDH.Nmos pass transistor n1, n2, n3, n4, n5, n6, n7, the substrate ground connection of n8.Inverter inv1, the supply voltage of inv5 inv6 are VDDH.Inverter inv2, inv3, the supply voltage of inv4 are VDDL.The supply voltage of NAND gate NAND2 is VDDL.

Fig. 8. the HSPICE analogous diagram that the duplicate supply of LH_IP_DCO_CD trigger of the present invention is pressed.

Fig. 9. the explicit clock pulse driving circuit structure figure of LH_IP_DCO_CD trigger of the present invention, this is that clock is monolateral along triggering.PMOS transistor p1 wherein, p2, the substrate of p3 meets VDDH.Nmos pass transistor n2, n3, n4, n5, n7, the substrate ground connection of n8.Inverter inv1, inv5, the supply voltage of inv6 are VDDH.Inverter inv2, inv3, inv4, the supply voltage of inv9 are VDDL.The supply voltage of NAND gate NAND1 is VDDL.

Figure 10. the explicit clock pulse driving circuit structure figure of LH_IP_DCO_CD trigger of the present invention, this is that clock is bilateral along triggering.PMOS transistor p1 wherein, p2, the substrate of p3 meets VDDH.PMOS transistor p9, the substrate of p10 meets VDDL.Nmos pass transistor n2, n3, n4, n5, n7, n8, n9, the substrate ground connection of n10.Inverter inv1, inv5, the supply voltage of inv6 are VDDH.Inverter inv2, inv3, inv4, the supply voltage of inv9 are VDDL.

Figure 11. the single supply for traditional IP_DCO circuit is pressed simulation waveform figure.

Figure 12. the duplicate supply for traditional IP_DCO circuit is pressed simulation waveform figure, and wherein D and clk are low amplitude of oscillation supply voltage, and main circuit is high amplitude of oscillation supply voltage.

Embodiment

The technical scheme that the present invention solves its technical problem is: CMOS semi-dynamic trigger LH_IP_DCO_CD and LH_SDFF_CD that condition discharge and clock pulse drive, as shown in Figure 6 and Figure 7.They all have simultaneously can high-low level conversion and the condition of employing discharge technology reduce the characteristics of the power consumption of flip-flop circuit own.

At first analyze LH_IP_DCO_CD.With respect to IP_DCO, the charging here realizes by the p1 transistor, and simultaneously because its grid meets the output feedback signal HQN of the high amplitude of oscillation, so p1 can be turn-offed fully, thereby reduces leakage current greatly.Be different from traditional IP_DCO circuit, the data-signal input pipe n3 here meets n4, and the condition switch that n5 forms carries out the discharge control of internal node electric charge.When HQN is high, when D is high, the discharge of the circuit first order, the second level since DN turn-off for low n8, thereby the HQN step-down, HQ uprises, and realizes the function of flip/flops latch D.Because this moment, HQN was low, so internal node X restarts charging, until the VDDH high level.When HQ is high, D is when low, and internal node does not discharge, and the second level then begins conducting uprises HQN, and the HQ step-down is realized the function of flip/flops latch D.Because internal node often be high, so the holding circuit of circuit inside managed by an inverter and a PMOS respectively and forms, as inv1 and p2.The condition discharging function here is meant with respect to traditional IP_DCO trigger, when the D input signal is continuously when high, and the charging and discharging that the IP_DCO internal node can continue, thus cause extra power consumption penalty.This charging and discharging is redundant, and the new LH_IP_DCO_CD that proposes then can eliminate this redundant upset.When D is continuously when high, HQ is continuously height, and HQN is continuously low, thereby the n3 pipe always ends, first order circuit originally should discharge recharge and do not carry out, eliminated the redundancy upset of left branch road.The inverter inv2 that the clock signal of this circuit drives by a VDDL, inv3, inv4 is connected into NMOS pipe n1 and n6.Simultaneously, clock also directly is connected to NMOS pipe n2, and n7.Thereby only opening in a flash of first order branch road and second level branch road at rising edge clock.It is that D changes the mistake upset that causes between high period that sort circuit can prevent to work as clock, and assurance function is correct.

The another kind of form of the LH_IP_DCO_CD that drives for explicit clock pulse as shown in Figure 9, here clock signal clk produces corresponding clock pulse clk_pulse by the clock generating circuit of a VDDL driving earlier, and clk_pulse is connected into the master flip-flop circuit more then.Owing to have a lot of triggers on the sheet, so this clk_pulse can be used as the total clock pulse signal of local circuit, thereby further reduces power consumption.The principle of this impulse circuit is to allow clk signal and clk time-delay inversion signal through a NAND gate and inverter, thereby obtains the clk signal pulse.

In order further to improve the rate of information throughput, can also do improvement for clock pulse signal, make can both produce pulse signal on the bilateral edge of clock clk.This impulse circuit as shown in figure 10.

Because the discharge paths of internal circuit has been lacked a NMOS pipe, therefore, the LH_IP_DCO_CD trigger internal discharge speed that explicit clock pulse drives is faster, and the time-delay from clk_pulse to D reduces.

Same analysis also can be used for LH_SDFF_CD.With respect to SDFF, the charging here realizes by the p1 transistor, and simultaneously because its grid connects the output signal of the high amplitude of oscillation, so p1 can be turn-offed fully, thereby reduces leakage current greatly.Be different from traditional SDFF circuit, the data-signal input pipe n2 here meets n4, and the condition switch that n5 forms carries out the discharge control of internal node electric charge.When HQN is high, when D is high, the discharge of the circuit first order, the second level since DN turn-off for low n8, thereby the HQN step-down, HQ uprises, and realizes the function of flip/flops latch D.Because the effect of n3 pipe and grid-control voltage thereof, the n3 pipe ends, then because HQN this moment is low, so internal node X restarts charging, until the VDDH high level.When HQ is high, D is when low, and internal node does not discharge, and the second level then begins conducting uprises HQN, and the HQ step-down is realized the function of flip/flops latch D.Because internal node often be high, so the holding circuit of circuit inside managed by an inverter and a PMOS respectively and forms, as inv1 and p2.The condition discharging function here is meant with respect to traditional SDFF trigger, when the D input signal is continuously when high, and the charging and discharging that the SDFF internal node can continue, thus cause extra power consumption penalty.This charging and discharging is redundant, and the new LH_SDFF_CD that proposes then can eliminate this redundant upset.When D is continuously when high, HQ is continuously height, and HQN is continuously low, thereby the n2 pipe always ends, first order circuit originally should discharge recharge and do not carry out, eliminated the redundancy upset of left branch road.The inverter inv2 that the clock signal of this circuit drives by a VDDL, inv3, inv4 are connected into NMOS pipe n6.Clock signal also directly is connected to NMOS pipe n7 simultaneously.Thereby only opening in a flash of second level branch road at rising edge clock.It is that D changes the mistake upset that causes between high period that sort circuit can prevent to work as clock, and assurance function is correct.

Essential features of the present invention is:

1, circuit can adopt low amplitude of oscillation clock signal to drive and hang down the input of amplitude of oscillation data-signal, and the high amplitude of oscillation signal of carry-out bit is fit to simultaneously As multi-power source voltage the interface circuit in the circuit design.

2, flip-flop circuit adopts by input data signal D and output HQ, and the condition charge/discharge control circuit of HQN FEEDBACK CONTROL is finished Control to former input D signal node.

3, this trigger charge inside is eliminated the upset of unnecessary redundancy by output feedback signal HQN control, thereby reduces dynamically Power consumption. The grid of PMOS pipe are HQN because charge with this moment simultaneously. Its high level is high amplitude of oscillation signal, has therefore reduced and has revealed electricity Stream.

4, because trigger internal node X often remains height, therefore inner level holding circuit is reduced to an inverter and adds a PMOS pipe, thereby reduces power consumption.

5, the chain of inverters that the odd number inverter that clock drives by a VDDL is formed is received the grid of two series connection in second level NMOS pipe in the circuit, at the internal clock pulse window, and the discharge of control trigger internal node.

In order to show LH_IP_DCO_CD proposed by the invention and LH_SDFF_CD trigger performance characteristics, we adopt HJTC 1.8-V 0.18 μ m technology, are example with LH_IP_DCO_CD, use circuit simulation tools HSPICE that circuit structure has been carried out emulation.Oscillogram when Fig. 8 has shown this trigger operate as normal.Here high power supply voltage VDDH is 1.8V, and low supply voltage VDDL is set to 1V.Input clock signal is the VDDL signal, and clock frequency is 100MHz, and duty ratio is 50%.Input data signal also is the VDDL signal, signal change frequency 20MHz, and duty ratio is 50%.Can see that output HQ and HQN finish function smoothly, and high level is VDDH.Equally, for traditional circuit I P_DCO.When only with a supply voltage, as shown in figure 11, can see obviously that when input data D is permanent when high, circuit is inner to exist redundant the upset.When traditional IP_DCO was used to the multi-power source voltage design, the function of trigger was then lost fully, as shown in figure 12.The present invention does not then have the problems referred to above.

Claims (4)

1, the CMOS level shift semi-dynamic trigger of condition discharge and pulsed drive is characterized in that this trigger contains condition switch, the condition discharge circuit, and holding circuit, data-latching circuit, clock-pulse circuit and status signal output circuit, wherein:

The condition discharge circuit, by PMOS pipe p1, NMOS manages n3, and NMOS manages n2, and NMOS pipe n1 is in series successively, and the source electrode of this p1 jar meets the supply voltage VDDH of the high amplitude of oscillation, the source ground of n1 pipe, the grid of n2 meets clk, and the grid of n1 meets clkN,

Condition switch, by NMOS pipe n5, n4 forms, and the source electrode of this n5 pipe links to each other with the source electrode of n4 pipe, receive the grid of n3 pipe, the drain electrode of this n5 pipe meets input signal D, and the grid of n5 pipe meets output feedback signal HQN, the drain electrode of this n4 pipe connects input earth signal 0, and the grid of this n4 pipe meets output feedback signal HQ

Holding circuit is made up of inverter inv1 and PMOS pipe p2, and the input of this inverter meets internal node X, and output connects the grid of p2 pipe, and the source electrode of p2 pipe meets VDDH, and the drain electrode of p2 pipe meets X,

Data-latching circuit, by PMOS pipe p3, NMOS manages n8, n7, n6 is in series successively, and wherein, the grid that p3 closes meets internal node X, the drain electrode of p3 pipe meets output signal HQ, the source electrode of p3 pipe meets VDDH, and the grid of n8 meets the inversion signal DN of D signal, and the grid of n7 meets clock signal clk, the grid of n6 meets clkN

Clock-pulse circuit, by inverter inv2, inv3, inv4 is in series successively, wherein inv2 be input as clk, inv4 is output as clkN,

The status signal output circuit is formed in parallel in the other direction by inverter inv5 and inv6, and the input of the output of inverter inv5 and inverter inv6 links to each other and forms signal HQN, and the output of the input of inverter inv5 and inverter inv6 links to each other and forms signal HQ,

The substrate of above-mentioned all PMOS pipes meets supply voltage VDDH, the substrate ground connection of all NMOS pipes, and inverter inv1, inv5, the supply voltage of inv6 are VDDH, inverter inv2, inv3, the supply voltage of inv4 are VDDL.

2, the CMOS level shift semi-dynamic trigger of condition discharge according to claim 1 and pulsed drive, it is characterized in that, described clock pulse signal forms the inverter inv2 of circuit by the VDDL power supply, inv3, inv4, NAND gate NAND1 and inv9 are composed in series, wherein another of the input of inv2 and NAND1 imported termination Clk, the output of inv9 is the Clk_Pulse signal, the Clk_Pulse signal is connected to the grid of n2 and n7 respectively, direct ground connection behind the source electrode short circuit n1 of n2, direct ground connection behind the source electrode short circuit n6 of n7.

3, the CMOS level shift semi-dynamic trigger of condition discharge according to claim 1 and pulsed drive is characterized in that,

The in2 that connects successively, inv3, inv4 inverter, PMOS pipe p9 and NMOS pipe n9, both source electrodes join, and drain electrode is joined, the grid of n9 pipe connects the input of inv4, the grid of p9 connects the output of inverter inv4, PMOS pipe p10 and NMOS pipe n10, and both source electrodes join, drain electrode is joined, the grid of n10 pipe connects the output of inv4, and the grid of p10 connects the input of inverter inv4

The input of inverter inv9 and n9, p9, n10, the source electrode of p10 joins, and inv9 is output as signal Clk_Pulse, n9, the drain electrode of p9 connects the clk signal, n10, the drain electrode of p10 connects the output of inv2.The source electrode of n2 pipe is the direct ground connection in short circuit n1 pipe back, and the grid of this n2 pipe meets signal Clk_Pulse, and the source electrode of n7 pipe is managed directly ground connection of back at short circuit n6, and the grid of this n7 pipe meets signal Clk_Pulse.

4, the CMOS level shift semi-dynamic trigger of condition discharge according to claim 1 and pulsed drive is characterized in that,

N4 in the described condition switch, the source electrode of n5 is connected to the grid of n2, is input to the signal clk of n2 grid with replacement, and the grid of p1 meets HQN, and the grid of n1 connects the clk signal,

Described clock-pulse circuit is by the inv2 of series connection successively, inv3, and inv4 and NAND gate NAND2 form.The output of this NAND gate NAND2 connects the grid of n3, the input termination internal node X of NAND2, and the output of another input termination inv3 of NAND2, the grid of n6 connects the output signal of inv4.

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