CN100471061C - CMOS level shift trigger of conditional discharge and differential I/O - Google Patents

Abstract

The invention relates to a CMOS voltage convert trigger. Wherein, it is characterized in that it comprises discharge/charge circuit, condition switch, clock window circuit, charging circuit of differential input and forming circuit of clock impulse; two symmetry condition switches control the cross discharge/charge circuit; two symmetry holding circuits hold the states of relative internal nodes; the clock window circuit allows the circuit to open trigger at the instant of ascending clock, and close trigger when the clock signal is high, to avoid error turnover caused in changed input signal in the stable period; and since it uses condition switch, it can eliminate internal abundant turnover, to reduce power consumption and realize the conversation from low to high voltage.

Description

The CMOS level conversion trigger of condition discharge and difference input and output

Technical field

" the CMOS level conversion triggers of condition discharge and difference input and output " direct applied technical field is the integrated circuit (IC) design of multi-power source voltage.The circuit that proposes is that a class is applicable to low amplitude of oscillation clock network, low amplitude of oscillation data-signal be used for the CMOS flip-flop circuit unit of low-voltage to the high voltage conversion.

Background technology

Along with the progress of CMOS integrated circuit fabrication process, the scale and the complexity of integrated circuit increase day by day, and power consumption of integrated circuit and heat dissipation problem more and more obtain the attention from industrial quarters and academia.CMOS power consumption of integrated circuit source mainly contains dynamic power consumption, quiescent dissipation, short circuit current power consumption and leakage current power consumption.For now, the dynamic power consumption of integrated circuit still accounts for major part.Under certain circuit performance constraint, the dynamic power consumption P of CMOS integrated circuit _DynamicCan be expressed as:

$P_{\mathrm{Dynamic}}=f{C}_{\mathrm{eff}}{V}_{\mathrm{dd}}^2---\left(1\right)$

Wherein $C_{\mathrm{eff}}=\underset{i=1}{\overset{N}{\mathrm{\Σ}}}{\mathrm{\α}}_i{k}_i{C}_i.$

Here, f is the operating frequency of circuit, α _iBe the upset probability of the signal of i node, k _iBe node i place voltage swing coefficient (if full swing, then k _i=1), C _iBe the total capacitance at node i place, V _DdBe supply voltage.From formula (1), as seen, reduce α _i, C _i, V _DdAnd k _iAll can reduce the dynamic power consumption of circuit.Yet because dynamic power consumption and supply voltage are square dependences, therefore reducing supply voltage can reduce dynamic power consumption greatly.So, allow the technology of a plurality of supply voltages in the integrated circuit to arise at the historic moment, such as containing two supply voltages.Represent low amplitude of oscillation supply voltage with VDDL.VDDH represents high amplitude of oscillation supply voltage.Fig. 1 has shown a kind of block diagram of multi-power source voltage design.

In the integrated circuit (IC) design of multi-power source voltage, level translator is indispensable circuit unit.They are placed between low supply voltage part unit and the high power supply voltage part unit as interface circuit.If without them, then the PMOS transistor in the high power supply voltage part unit is owing to directly driven by the signal of low supply voltage, can not thoroughly turn-off and causes occurring big leakage current.Insert the influence that level translator brings in order to reduce, lumped voltage reduces that technology (the clustered voltage scaling) person of being studied puts forward to be used to reduce area that level translator brings and the loss of time-delay (is seen document K.Usami and M.Horowitz, " Clustered voltage scaling technique for low-power design; " in Proc.Int.Symp.LowPower Design, Dana Point, CA, Apr.1995, pp.3-8.).In this method, level translator has been integrated in trigger inside.

What Fig. 2 showed is the flip-flop circuit cell schematics.Be illustrated in figure 3 as the traditional flip-flop circuit unit basic circuit structure that is widely used in the design of digital circuit standard cell lib, here with complementary output in the Chartered 0.18 μ m technology digital standard cell library, the flip-flop circuit cells D FNRB1 that rising edge triggers is example explanation (seeing document Manual of " Chartered0.18micron; 1.8 volt Optimum Silicon SC Library CSM18OS120 ", Version 1.2 February 2003.).The main feature of sort circuit structure is that circuit structure is fairly simple, but is not suitable for the design of low-clock signal excursion clock network system, because clock signal upset each time all can cause the upset of circuit internal node, circuit power consumption is bigger simultaneously.The flip-flop circuit of difference input and output is used widely because of having comparatively symmetrical output characteristic.In order to reduce power consumption, the researcher considered once that only clock signal was the low amplitude of oscillation, and data-signal is the situation of the high amplitude of oscillation.H.Kawaguchi propose a kind of flip-flop circuit RCSFF that can adopt low-voltage amplitude of oscillation clock signal to drive (see document H.Kawaguchi and T.Sakurai: " AReduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction " ', IEEE JOURNAL OFSOLID-STATE CIRCUITS, VOL.33, NO.5, MAY 1998, PP.807-811.), but the problem of sort circuit is when clock signal low level each time, extra energy consumption can be caused to the precharge of circuit internal node in the capital.On the basis of RCSFF circuit, the flip-flop circuit SAFF_CP that Y.Zhang proposes a kind of low-voltage amplitude of oscillation clock signal driving of condition presetting construction (sees document Y.Zhang, H.Yang, and H.Wang, " Low clock-swing conditional-prechargeflip-flop for more than 30% power reduction; " Electron.Lett., vol.36, no.9, pp.785-786, Apr.2000.), as shown in Figure 4.The maximum characteristics of this flip-flop circuit are can be operated under the low-voltage oscillation amplitude driving conditional except keeping; Simultaneously, if the flip-flop circuit input remains unchanged when the clock signal low level, circuit can be to its internal node precharge between the clock signal low period.The employing of this technology greatly reduces the power consumption of flip-flop circuit itself.But, in the SAFF_CP circuit, need an extra substrate bias supply, and owing to adopt condition presetting mechanism, make transistor MP1 and MP2 not to end fully, cause the leakage current power consumption of circuit to increase, this problem is especially more serious after adopting low amplitude of oscillation clock signal to drive.Even more serious is, more than all circuit all can not be operated in data-signal and clock signal and be low level situation, that is to say that they all can not be as the interface circuit of level conversion.At present can be also seldom as the trigger of high-low level translation function.People such as Fujio Ishihara proposed a kind of difference imput output circuit PSA that can be used for level conversion and (saw document Fujio Ishihara, Farhana Sheikh, and Borivoje Nikolic, " Level conversion for dual-supplysystems; " IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.12, No.2, Feb.2004).The level conversion trigger CSSA that people such as H.Hamada also proposed based on sense amplifier (sees document H.Hamadaet al., " A top-down low power design technique using clustered voltage scaling with variablesupply-voltage scheme; " Custom Integrated Circuits Conf., PP.495-498,1998.).But still there is the similar redundant turning problem of above-mentioned RCSFF in these circuit, thereby have bigger power wastage.People such as H.Mahmoodi-Meimand by analysis, proposed to adopt the differential level transition trigger device SPFF of conditional capture technology, eliminated inner redundancy upset, reduced power consumption (seeing document H.Mahmoodi-Meimand et al., " Self-precharging flip-flop (SPFF): A newlevel converting flip-flop ").But this circuit has adopted a lot of transistors (48), need take bigger area and power consumption.

Summary of the invention

The objective of the invention is to propose the CMOS difference input and output trigger D_LH_DEFF and the S_LH_DEFF of two kinds of integrated level conversion functions.Because circuit adopts new condition discharge mechanism and charging mechanism, eliminate the built-in redundancy upset of trigger and reduced leakage current, reduced the power consumption of circuit.Dynamically the basic structure of the D_LH_DCFF of output stage as Fig. 5 and shown in, the circuit of its explicit pulse drive mode be Fig. 9 and shown in Figure 10, wherein Fig. 9 be that clock is monolateral along triggering, Figure 10 is clock bilateral edge triggering.The basic structure of the S_LH_DCFF of static output stage as shown in Figure 6, the circuit of its explicit pulse drive mode be Figure 11 and shown in Figure 12, wherein Figure 11 be that clock is monolateral along triggering, Figure 12 is clock bilateral edge triggering.

With traditional digital standard unit triggers device circuit DFNRB1, the RCSFF flip-flop circuit, the SAFF_CP flip-flop circuit, PSA, the SPFF flip-flop circuit relatively, D_LH_DEFF that the present invention proposes and S_LH_DEFF trigger adopt less transistor, can be as interface circuit in the integrated circuit (IC) design environment of multi-power source voltage, simultaneously this circuit for eliminating the built-in redundancy upset, reduced dynamic power consumption, the circuit engineering that is proposed is suitable as the digital circuit standard cell and is applied in the design of multi-power source voltage low power consumption integrated circuit very much.

Description of drawings

Fig. 1. the design philosophy block diagram of modern multi-power source voltage integrated circuit.

Fig. 2. the flip-flop circuit cell schematics, D is the data-signal input, CLK is a clock signal input terminal, Q and Q _bBe the complementary signal output;

The flip-flop circuit cells D FNRB1 circuit structure diagram that complementary output and rising edge trigger in Fig. 3 .Chartered 0.18um technology digital standard cell library;

Fig. 4 .SAFF_CP flip-flop circuit structure chart;

Fig. 5. D_LH_DEFF flip-flop circuit structure chart of the present invention.PMOS transistor p1, p2, p3, p4, p5, the substrate of p6 meets VDDH.Nmos pass transistor n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, the substrate ground connection of n12.Inverter inv1, inv2, inv6, the supply voltage of inv7 are VDDH.Inverter inv3, inv4, the supply voltage of inv5 are VDDL.

Fig. 6. S_LH_DEFF flip-flop circuit structure chart of the present invention.PMOS transistor p3, p4, p5, the substrate of p6 meets VDDH.Nmos pass transistor n1, n2, n3, n4, n5, n6, n7, the substrate ground connection of n8.Inverter inv1, the supply voltage of inv2 are VDDH.Inverter inv3, inv4, the supply voltage of inv5 are VDDL.The supply voltage of NAND gate NAND3 and NAND2 is VDDH.

Fig. 7. the sequential chart of D_LH_DEFF of the present invention and S_LH_DEFF trigger.

Fig. 8. the HSPICE analogous diagram of D_LH_DEFF trigger of the present invention under multi-power source voltage.

Fig. 9. the explicit clock pulse driving circuit structure figure of D_LH_DEFF trigger of the present invention, this is that clock is monolateral along triggering.PMOS transistor p1, p2, p3, p4, p5, the substrate of p6 meets VDDH.Nmos pass transistor n2, n3, n4, n5, n6, n7, n8, n10, n11, the substrate ground connection of n12.Inverter inv1, inv2, inv6, the supply voltage of inv7 are VDDH.Inverter inv3, inv4, inv5, the supply voltage of inv9 are VDDL.The supply voltage of NAND gate NAND1 is VDDL.

Figure 10. the explicit clock pulse driving circuit structure figure of D_LH_DEFFD trigger of the present invention, this is that clock is bilateral along triggering.PMOS transistor p1, p2, p3, p4, p5, the substrate of p6 meets VDDH.PMOS transistor p9, the substrate of p10 meets VDDL.Nmos pass transistor n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, the substrate ground connection of n12.Inverter inv1, inv2, inv6, the supply voltage of inv7 are VDDH.Inverter inv3, inv4, inv5, the supply voltage of inv9 are VDDL.

Figure 11. the explicit clock pulse driving circuit structure figure of S_LH_DEFF trigger of the present invention, this is that clock is monolateral along triggering.PMOS transistor p3, p4, p5, the substrate of p6 meets VDDH.Nmos pass transistor n2, n3, n4, n5, n6, n7, the substrate ground connection of n8.Inverter inv1, the supply voltage of inv2 are VDDH.Inverter inv3, inv4, inv5, the supply voltage of inv9 are VDDL.The supply voltage of NAND gate NAND1 is VDDL.The supply voltage of NAND2 and NAND3 is VDDH.

Figure 12. the explicit clock pulse driving circuit structure figure of S_LH_DEFF trigger of the present invention, this is that clock is bilateral along triggering.PMOS transistor p3, p4, p5, the substrate of p6 meets VDDH.PMOS transistor p9, the substrate of p10 meets VDDL.Nmos pass transistor n2, n3, n4, n5, n6, n7, n8, n9, the substrate ground connection of n10.Inverter inv1, the supply voltage of inv2 are VDDH.Inverter inv3, inv4, inv5, the supply voltage of inv9 are VDDL.The supply voltage of NAND gate NAND2 and NAND3 is VDDH.

Figure 13. for the HSPICE simulation waveform figure of traditional SAFF circuit under multi-power source voltage.

Embodiment

The technical scheme that the present invention solves its technical problem is: the CMOS level conversion trigger D_LH_DEFF and the S_LH_DEFF of condition discharge and difference input and output, as shown in Figure 5 and Figure 6.D_LH_DEFF and S_LH_DEFF trigger have simultaneously can high-low level conversion and the condition of employing discharge technology reduce the characteristics of the power consumption of flip-flop circuit own.The sequential chart of this circuit as shown in Figure 7.

At first we analyze the D_LH_DEFF flip-flop circuit.With respect to the circuit of other condition presettings, the charging here is by p3, and the p4 transistor realizes, simultaneously because their grid meets the output feedback signal HQ of the high amplitude of oscillation, and HQN, so p3, p4 can be turn-offed fully, thereby reduces leakage current greatly.Be different from traditional SAFF_CP circuit, the data-signal input pipe n3 here, n4 connects condition switch, carries out the discharge control of internal node.When HQN is high, when D is high, the discharge of left side branch road, thereby HQN step-down, HQ uprises, and realizes the function of flip/flops latch D.Because this moment, HQN was low, so left side branch road internal node restarts charging, until the VDDH high level.For the right branch road, when HQ is high, D is when low, and the right branch road begins discharge, thereby HQN uprises, and the HQ step-down is realized the function of flip/flops latch D.This moment, the right branch road began to charge to again high level VDDH again owing to the HQ step-down.Because internal node often be high, so the inside holding circuit at circuit two ends managed by an inverter and a PMOS respectively and forms, as inv1, and inv2, p5 is shown in the p6.The condition discharging function here is meant with respect to traditional SAFF trigger, when the D input signal is continuously height or is continuously when low, and the charging and discharging that the SAFF internal node can continue, thus cause extra power consumption penalty.This charging and discharging is redundant, and the new LH_DEFF_CD that proposes then can eliminate this redundant upset.When D is continuously when high, HQ is continuously height, and HQN is continuously low, thereby the n3 pipe always ends, left side branch road originally should discharge recharge and do not carry out, eliminated the redundancy upset of left branch road.When D is continuously when low, HQN is continuously height, thereby the n4 pipe ends, the right branch road originally should discharge recharge and do not carry out, eliminated the redundancy upset of right branch road.The inverter inv3 that the clock signal of this circuit drives by VDDL, inv4, inv5 is connected into NMOS pipe n1, and NMOS pipe n2 then directly is connected to NMOS pipe n1, thus n1, only the opening in a flash of n2 branch road at rising edge clock.It is that D changes the mistake upset that causes between high period that sort circuit can prevent to work as clock, and assurance function is correct.

The another kind of form of the D_LH_DEFF that drives for explicit clock pulse as shown in Figure 9, here clock signal clk produces corresponding clock pulse Clk_Pulse by the clock generating circuit of a VDDL driving earlier, and Clk_Pulse is connected into the master flip-flop circuit more then.Owing to have a lot of triggers on the sheet, so this Clk_Pulse can be used as the total clock pulse signal of local circuit, thereby further reduces power consumption.The principle of this impulse circuit is to allow clk signal and clk time-delay inversion signal through a NAND gate and inverter, thereby obtains the clk signal pulse.

In order further to improve the rate of information throughput, can also do improvement for clock pulse signal, make can both produce pulse signal on the bilateral edge of clock clk.This impulse circuit as shown in figure 10.

Because the discharge paths of internal circuit has been lacked a NMOS pipe, therefore, the D_LH_DEFF trigger internal discharge speed that explicit clock pulse drives is faster, and the time-delay from Clk_Pulse to D reduces.

Secondly we analyze the S_LH_DEFF flip-flop circuit, as shown in Figure 6.The charging here is by p3, and the p4 transistor realizes, simultaneously because their grid meets the output feedback signal HQ of the high amplitude of oscillation, and HQN, so p3, p4 can be turn-offed fully, thereby reduces leakage current greatly.Be different from traditional SAFF_CP circuit, the data-signal input pipe n3 here, n4 connects condition switch, carries out the discharge control of internal node.When HQN is high, when D is high, the discharge of left side branch road, thereby HQN step-down, HQ uprises, and realizes the function of flip/flops latch D.Because this moment, HQN was low, so left side branch road internal node restarts charging, until the VDDH high level.For the right branch road, when HQ is high, D is when low, and the right branch road begins discharge, thereby HQN uprises, and the HQ step-down is realized the function of flip/flops latch D.This moment, the right branch road began to charge to again high level VDDH again owing to the HQ step-down.Because internal node often be high, so the inside holding circuit at circuit two ends managed by an inverter and a PMOS respectively and forms, as inv1, and inv2, p5 is shown in the p6.The condition discharging function here is meant with respect to traditional SAFF trigger, when the D input signal is continuously height or is continuously when low, and the charging and discharging that the SAFF internal node can continue, thus cause extra power consumption penalty.This charging and discharging is redundant, and the new S_LH_DEFF that proposes then can eliminate this redundant upset.When D is continuously when high, HQ is continuously height, and HQN is continuously low, thereby the n3 pipe always ends, left side branch road originally should discharge recharge and do not carry out, eliminated the redundancy upset of left branch road.When D is continuously when low, HQN is continuously height, thereby the n4 pipe ends, the right branch road originally should discharge recharge and do not carry out, eliminated the redundancy upset of right branch road.The inverter inv3 that the clock signal of this circuit drives by VDDL, inv4, inv5 is connected into NMOS pipe n1, and NMOS pipe n2 then directly is connected to NMOS pipe n1, thus n1, only the opening in a flash of n2 branch road at rising edge clock.It is that D changes the mistake upset that causes between high period that sort circuit can prevent to work as clock, and assurance function is correct.

The S_LH_DEFF that drives for explicit clock pulse as shown in figure 11, the clock generating circuit that drives by a VDDL earlier of clock signal clk produces corresponding clock pulse Clk_Pulse here, Clk_Pulse is connected into the master flip-flop circuit more then.Owing to have a lot of triggers on the sheet, so this Clk_Pulse can be used as the total clock pulse signal of local circuit, thereby further reduces power consumption.The principle of this impulse circuit is to allow clk signal and clk time-delay inversion signal through a NAND gate and inverter, thereby obtains the Clk_Pulse signal pulse.

In order further to improve the rate of information throughput, can also do improvement for clock pulse signal, the bilateral edge of the clk that makes at clock can both produce pulse signal.This impulse circuit as shown in figure 12.

Because the discharge paths of internal circuit has been lacked a NMOS pipe, therefore, the S_LH_DEFF trigger internal discharge speed that explicit clock pulse drives is faster, and the time-delay from Clk_Pulse to D reduces.

Adopt circuit engineering of the present invention, can obtain advantage on power consumption and the performance, mainly show by improved circuit engineering:

1. circuit can adopt low amplitude of oscillation clock signal to drive and hang down the input of amplitude of oscillation data-signal, and the high amplitude of oscillation signal of carry-out bit is suitable as the interface circuit in the multi-power source voltage integrated circuit (IC) design simultaneously.

2. flip-flop circuit adopts by input data signal D and output HQ, and the condition charge/discharge control circuit of HQN FEEDBACK CONTROL is finished the control to former input D signal node.

3. this trigger charge inside is eliminated the upset of unnecessary redundancy by output feedback signal HQ and HQN control, thereby reduces dynamic power consumption.The grid of PMOS pipe are HQ because charge with this moment simultaneously, HQN.Its high level is high amplitude of oscillation signal, has therefore reduced Leakage Current.

4. owing to trigger internal node XL, XR often remains height, and therefore inner level holding circuit is reduced to an inverter and adds a PMOS pipe, thereby reduces power consumption.

5. the chain of inverters formed of the odd number inverter that drives by VDDL of clock is received the grid of two series connection NMOS pipes in the circuit, at the internal clock pulse window, and the discharge of control trigger internal node.

6. the principle of pulse generation circuit is to allow clk signal and clk time-delay inversion signal through a NAND gate and inverter, thereby obtains the Clk_Pulse signal pulse

7. the principle of dipulse generation circuit is to allow the clk signal through the anti-phase step by step time-delay of inverter, controls two complementary transmission gate outputs then, at last by an inverter output

In order to show D_LH_DEFF trigger performance characteristics proposed by the invention, we adopt HJTC1.8-V0.18 μ m technology, use circuit simulation tools HSPICE that circuit structure has been carried out emulation.Oscillogram when Fig. 8 has shown this trigger operate as normal.Here high power supply voltage VDDH is 1.8V, and low supply voltage VDDL is set to 1V.Input clock signal is the VDDL signal, and clock frequency is 100MHz, and duty ratio is 50%.Input data signal also is the VDDL signal, signal change frequency 20MHz, and duty ratio is 50%.Can see that output HQ and HQN finish function smoothly, and high level is VDDH.Equally, identical condition has been applied on traditional circuit SAFF.Can obviously see, when input data D is perseverance height or permanent hanging down, the upset of the inner existence redundancy of circuit.Equally also can see this redundant upset for the PSA circuit.In addition, we can also see from Figure 13, because clk is low amplitude of oscillation signal, the PMOS pipe of charging can not turn-off fully, therefore again internal node such as XL is charged, and causes logic error.Then there is not this problem in circuit of the present invention.

Claims (5)

1, the CMOS level conversion trigger of condition discharge and difference input and output is characterized in that this trigger contains charge-discharge circuit, condition switch, and holding circuit, the clock window circuit, the charging of difference input and the formation circuit of clock pulse, wherein:

Charge-discharge circuit, be formed by connecting by two discharge paths, wherein, article one, form by the 3rd PMOS pipe (p3) and the 3rd NMOS pipe (n3) serial connection, another is managed (p4) and the 4th NMOS pipe (n4) serial connection by the 4th PMOS and forms, be connected first power supply (VDDH) of the high amplitude of oscillation of the source electrode that described the 3rd PMOS pipe (p3) and the 4th PMOS manage (p4); Condition switch, totally two, wherein:

The first condition switch, form by the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5), two source electrodes of the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5) connect first supplied with digital signal (D) and earth signal 0 respectively, two signals connect first status signal (HQN) and second status signal (HQ) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that first status signal (HQN) is connected to the 3rd PMOS pipe (p3) control of charging, and two drain electrodes connect the grid that the 3rd NMOS manages (n3) after linking to each other, carry out discharge control

The second condition switch, form by the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7), two source electrodes of the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7) connect second supplied with digital signal (DN) and earth signal 0 respectively, second supplied with digital signal (DN) is the inversion signal of described first supplied with digital signal (D), two signals connect second status signal (HQ) and first status signal (HQN) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that second status signal (HQ) is connected to the 4th PMOS pipe (p4) control of charging, and two drain electrodes connect the grid that the 4th NMOS manages (n4) after linking to each other, and carry out discharge control;

Holding circuit, totally two, wherein:

First holding circuit, form by first inverter (inv1) and the 5th PMOS pipe (p5), the output of this first inverter (inv1) links to each other with the grid that the 5th PMOS manages (p5), the input of first inverter (inv1) links to each other with the drain electrode that the 3rd PMOS manages (p3), form first output (XL) of discharge circuit, the source electrode of the 5th PMOS pipe (p5) connects described first power supply (VDDH), and the drain electrode of the 5th PMOS pipe (p5) connects described first output (XL)

Second holding circuit, form by second inverter (inv2) and the 6th PMOS pipe (p6), the output of this second inverter (inv2) links to each other with the grid that the 6th PMOS manages (p6), the input of second inverter (inv2) links to each other with the drain electrode that the 4th PMOS manages (p4), form second output (XR) of discharge circuit, the source electrode of the 6th PMOS pipe (p6) connects described first power supply (VDDH), and the drain electrode of the 6th PMOS pipe (p6) connects described second output (XR); The clock window circuit, be in series by the 2nd NMOS pipe (n2) and NMOS pipe (n1), the drain electrode of the 2nd NMOS pipe (n2) links to each other with the source electrode of discharge paths the 3rd NMOS pipe (n3) with the 4th NMOS pipe (n4) simultaneously, the grid of the 2nd NMOS pipe (n2) connects first clock signal (clk), the grid of the one NMOS pipe (n1) connects the inversion signal (clkN) of first clock signal, and the source ground of NMOS pipe (n1), this window circuit is open-minded in a flash at rising edge clock only, prevented that clock from being between high period because first supplied with digital signal (D) changes the mistake upset that causes;

The difference imput output circuit, contain:

Manage the difference channel that (n11) is in series by PMOS pipe (p1) and the 11 NMOS, the grid of the one PMOS pipe (p1) connects first output (XL) of described discharge circuit, and the grid of the 11 NMOS pipe (n11) connects second supplied with digital signal (DN), connects described second status signal (HQ) after the drain electrode of the drain electrode of PMOS pipe (p1) and the 11 NMOS pipe (n11) is connected;

Manage the difference channel that (n12) is in series by the 2nd PMOS pipe (p2) and the 12 NMOS, the grid of the 2nd PMOS pipe (p2) connects second output (XR) of described discharge circuit, and the grid of the 12 NMOS pipe (n12) connects first supplied with digital signal (D), after being connected, the drain electrode of the drain electrode of the 2nd PMOS pipe (p2) and the 12 NMOS pipe (n12) connects described first status signal (HQN), parallel branch of serial connection between the drain electrode of the 11 NMOS pipe (n11) and the 12 NMOS pipe (n12), this parallel branch is formed in parallel by hex inverter (inv6) and the 7th inverter (inv7)

Manage (n9) be in series window circuit of output stage by the tenth NMOS pipe (n10) and the 9th NMOS, the drain electrode of the tenth NMOS pipe (n10) links to each other with the source electrode of branch road the 11 NMOS pipe (n11) with the 12 NMOS pipe (n12) simultaneously, the grid of the tenth NMOS pipe (n10) connects first clock signal (clk), the grid of the 9th NMOS pipe (n9) connects the inversion signal (clkN) of first clock signal, and the source ground of the 9th NMOS pipe (n9), this window circuit is open-minded in a flash at rising edge clock only, prevented that clock from being between high period because first supplied with digital signal (D) changes the mistake upset that causes;

Clock pulse forms circuit, by the 3rd inverter (inv3), the 4th inverter (inv4), the 5th inverter (inv5) is in series successively, described the 3rd inverter (inv3), the 4th inverter (inv4), the 5th inverter (inv5) is by second source (VDDL) power supply of the low amplitude of oscillation, the input signal of the 3rd inverter (inv3) is first clock signal (clk), and the 5th inverter (inv5) output signal is the inversion signal (clkN) of first clock signal;

The one PMOS manages (p1), the 2nd PMOS manages (p2), the 3rd PMOS manages (p3), the 4th PMOS manages (p4), and the 5th PMOS manages (p5), and the substrate of the 6th PMOS pipe (p6) connects described first power supply (VDDH), the one NMOS manages (n1), the 2nd NMOS manages (n2), and the 3rd NMOS manages (n3), and the 4th NMOS manages (n4), the 5th NMOS manages (n5), the 6th NMOS manages (n6), and the 7th NMOS manages (n7), and the 8th NMOS manages (n8), the 9th NMOS manages (n9), the tenth NMOS manages (n10), and the 11 NMOS manages (n11), the substrate ground connection of the 12 NMOS pipe (n12); First inverter (inv1), second inverter (inv2), the power supply of hex inverter (inv6) and the 7th inverter (inv7) is first power supply (VDDH).

2, the CMOS level conversion trigger of condition discharge and difference input and output is characterized in that this trigger contains charge-discharge circuit, condition switch, and holding circuit, the charging of difference input and the formation circuit of clock pulse, wherein:

Charge-discharge circuit, be formed by connecting by two discharge paths, wherein, article one, form by the 3rd PMOS pipe (p3) and the 3rd NMOS pipe (n3) serial connection, another is managed (p4) and the 4th NMOS pipe (n4) serial connection by the 4th PMOS and forms, be connected first power supply (VDDH) of the high amplitude of oscillation of the source electrode that described the 3rd PMOS pipe (p3) and the 4th PMOS manage (p4); Condition switch, totally two, wherein:

The first condition switch, form by the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5), two source electrodes of the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5) connect first supplied with digital signal (D) and earth signal 0 respectively, two signals connect first status signal (HQN) and second status signal (HQ) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that first status signal (HQN) is connected to the 3rd PMOS pipe (p3) control of charging, and two drain electrodes connect the grid that the 3rd NMOS manages (n3) after linking to each other, carry out discharge control

The second condition switch, form by the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7), two source electrodes of the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7) connect second supplied with digital signal (DN) and earth signal 0 respectively, second supplied with digital signal (DN) is the inversion signal of described first supplied with digital signal (D), two signals connect second status signal (HQ) and first status signal (HQN) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that second status signal (HQ) is connected to the 4th PMOS pipe (p4) control of charging, and two drain electrodes connect the grid that the 4th NMOS manages (n4) after linking to each other, and carry out discharge control;

Holding circuit, totally two, wherein:

First holding circuit, form by first inverter (inv1) and the 5th PMOS pipe (p5), the output of this first inverter (inv1) links to each other with the grid that the 5th PMOS manages (p5), the input of first inverter (inv1) links to each other with the drain electrode that the 3rd PMOS manages (p3), form first output (XL) of discharge circuit, the source electrode of the 5th PMOS pipe (p5) connects described first power supply (VDDH), and the drain electrode of the 5th PMOS pipe (p5) connects described first output (XL)

Second holding circuit, form by second inverter (inv2) and the 6th PMOS pipe (p6), the output of this second inverter (inv2) links to each other with the grid that the 6th PMOS manages (p6), the input of second inverter (inv2) links to each other with the drain electrode that the 4th PMOS manages (p4), form second output (XR) of discharge circuit, the source electrode of the 6th PMOS pipe (p6) connects described first power supply (VDDH), and the drain electrode of the 6th PMOS pipe (p6) connects described second output (XR);

The drain electrode of the 2nd NMOS pipe (n2) links to each other with the source electrode of discharge paths the 3rd NMOS pipe (n3) with the 4th NMOS pipe (n4) simultaneously, and the grid of the 2nd NMOS pipe (n2) connects first clock pulse signal (Clk_Pulse), the source ground of the 2nd NMOS pipe (n2);

The difference imput output circuit, contain:

Manage the difference channel that (n11) is in series by PMOS pipe (p1) and the 11 NMOS, the grid of the one PMOS pipe (p1) connects first output (XL) of described discharge circuit, and the grid of the 11 NMOS pipe (n11) connects second supplied with digital signal (DN), connects described second status signal (HQ) after the drain electrode of the drain electrode of PMOS pipe (p1) and the 11 NMOS pipe (n11) is connected;

Manage the difference channel that (n12) is in series by the 2nd PMOS pipe (p2) and the 12 NMOS, the grid of the 2nd PMOS pipe (p2) connects second output (XR) of described discharge circuit, and the grid of the 12 NMOS pipe (n12) connects first supplied with digital signal (D), after being connected, the drain electrode of the drain electrode of the 2nd PMOS pipe (p2) and the 12 NMOS pipe (n12) connects described first status signal (HQN), parallel branch of serial connection between the drain electrode of the 11 NMOS pipe (n11) and the 12 NMOS pipe (n12), this parallel branch is formed in parallel by hex inverter (inv6) and the 7th inverter (inv7)

The drain electrode of the tenth NMOS pipe (n10) links to each other with the source electrode of branch road the 11 NMOS pipe (n11) with the 12 NMOS pipe (n12) simultaneously, the grid of the tenth NMOS pipe (n10) connects first clock pulse signal (Clk_Pulse), the source ground of the tenth NMOS pipe (n10);

Clock pulse forms circuit by the 3rd inverter (inv3) of connecting successively, the 4th inverter (inv4), the 5th inverter (inv5), first NAND gate (NAND1), the 9th inverter (inv9) is formed, described first NAND gate (NAND1), the 3rd inverter (inv3), the 4th inverter (inv4), the 5th inverter (inv5), the supply power voltage of the 9th inverter (inv9) is second source (VDDL), and another input of described inverter and NAND gate connects first clock signal (clk), and the 9th inverter (inv9) is output as first clock pulse signal (Clk_Pulse);

The one PMOS manages (p1), the 2nd PMOS manages (p2), the 3rd PMOS manages (p3), the 4th PMOS manages (p4), the 5th PMOS manages (p5), the substrate of the 6th PMOS pipe (p6) connects described first power supply (VDDH), and the 2nd NMOS manages (n2), and the 3rd NMOS manages (n3), the 4th NMOS manages (n4), the 5th NMOS manages (n5), and the 6th NMOS manages (n6), and the 7th NMOS manages (n7), the 8th NMOS manages (n8), the tenth NMOS manages (n10), and the 11 NMOS manages (n11), the substrate ground connection of the 12 NMOS pipe (n12); First inverter (inv1), second inverter (inv2), the power supply of hex inverter (inv6) and the 7th inverter (inv7) is first power supply (VDDH).

3, the CMOS level conversion trigger of condition discharge and difference input and output is characterized in that this trigger contains charge-discharge circuit, condition switch, and holding circuit, the charging of difference input and the formation circuit of clock pulse, wherein:

Charge-discharge circuit, be formed by connecting by two discharge paths, wherein, article one, form by the 3rd PMOS pipe (p3) and the 3rd NMOS pipe (n3) serial connection, another is managed (p4) and the 4th NMOS pipe (n4) serial connection by the 4th PMOS and forms, be connected first power supply (VDDH) of the high amplitude of oscillation of the source electrode that described the 3rd PMOS pipe (p3) and the 4th PMOS manage (p4); Condition switch, totally two, wherein:

The first condition switch, form by the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5), two source electrodes of the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5) connect first supplied with digital signal (D) and earth signal 0 respectively, two signals connect first status signal (HQN) and second status signal (HQ) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that first status signal (HQN) is connected to the 3rd PMOS pipe (p3) control of charging, and two drain electrodes connect the grid that the 3rd NMOS manages (n3) after linking to each other, carry out discharge control

The second condition switch, form by the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7), two source electrodes of the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7) connect second supplied with digital signal (DN) and earth signal 0 respectively, second supplied with digital signal (DN) is the inversion signal of described first supplied with digital signal (D), two signals connect second status signal (HQ) and first status signal (HQN) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that second status signal (HQ) is connected to the 4th PMOS pipe (p4) control of charging, and two drain electrodes connect the grid that the 4th NMOS manages (n4) after linking to each other, and carry out discharge control;

Holding circuit, totally two, wherein:

First holding circuit, form by first inverter (inv1) and the 5th PMOS pipe (p5), the output of this first inverter (inv1) links to each other with the grid that the 5th PMOS manages (p5), the input of first inverter (inv1) links to each other with the drain electrode that the 3rd PMOS manages (p3), form first output (XL) of discharge circuit, the source electrode of the 5th PMOS pipe (p5) connects described first power supply (VDDH), and the drain electrode of the 5th PMOS pipe (p5) connects described first output (XL)

Second holding circuit, form by second inverter (inv2) and the 6th PMOS pipe (p6), the output of this second inverter (inv2) links to each other with the grid that the 6th PMOS manages (p6), the input of second inverter (inv2) links to each other with the drain electrode that the 4th PMOS manages (p4), form second output (XR) of discharge circuit, the source electrode of the 6th PMOS pipe (p6) connects described first power supply (VDDH), and the drain electrode of the 6th PMOS pipe (p6) connects described second output (XR);

The drain electrode of the 2nd NMOS pipe (n2) links to each other with the source electrode of discharge paths the 3rd NMOS pipe (n3) with the 4th NMOS pipe (n4) simultaneously, and the grid of the 2nd NMOS pipe (n2) connects first clock pulse signal (Clk_Pulse), and the source ground of the 2nd NMOS pipe (n2);

The difference imput output circuit, contain:

Manage the difference channel that (n11) is in series by PMOS pipe (p1) and the 11 NMOS, the grid of the one PMOS pipe (p1) connects first output (XL) of described discharge circuit, and the grid of the 11 NMOS pipe (n11) connects second supplied with digital signal (DN), connects described second status signal (HQ) after the drain electrode of the drain electrode of PMOS pipe (p1) and the 11 NMOS pipe (n11) is connected;

Manage the difference channel that (n12) is in series by the 2nd PMOS pipe (p2) and the 12 NMOS, the grid of the 2nd PMOS pipe (p2) connects second output (XR) of described discharge circuit, and the grid of the 12 NMOS pipe (n12) connects first supplied with digital signal (D), after being connected, the drain electrode of the drain electrode of the 2nd PMOS pipe (p2) and the 12 NMOS pipe (n12) connects described first status signal (HQN), parallel branch of serial connection between the drain electrode of the 11 NMOS pipe (n11) and the 12 NMOS pipe (n12), this parallel branch is formed in parallel by hex inverter (inv6) and the 7th inverter (inv7)

The drain electrode of the tenth NMOS pipe (n10) links to each other with the source electrode of branch road the 11 NMOS pipe (n11) with the 12 NMOS pipe (n12) simultaneously, the grid of the tenth NMOS pipe (n10) connects first clock pulse signal (Clk_Pulse), the source ground of the tenth NMOS pipe (n10);

Clock pulse forms circuit and contains:

The 3rd inverter (inv3) of connecting successively, the 4th inverter (inv4), the 5th inverter (inv5), the 9th PMOS pipe (p9) and the 9th NMOS pipe (n9), both source electrodes join, drain electrode is joined, the grid of the 9th NMOS pipe (n9) connects the input of the 5th inverter (inv5), the grid of the 9th PMOS pipe (p9) connects the output of the 5th inverter (inv5), the tenth PMOS pipe (p10) and NMOS pipe (n1), and both source electrodes join, drain electrode is joined, the grid of the one NMOS pipe (n1) connects the output of the 5th inverter (inv5), and the grid of the tenth PMOS pipe (p10) connects the input of the 5th inverter (inv5)

The input of the 9th inverter (inv9) and the 9th NMOS pipe (n9), the 9th PMOS manages (p9), the one NMOS manages (n1), the source electrode of the tenth PMOS pipe (p10) joins, the 9th inverter (inv9) is output as first clock pulse signal (Clk_Pulse), and the 9th NMOS manages (n9), and the drain electrode of the 9th PMOS pipe (p9) connects first clock signal (clk), the one NMOS manages (n1), and the drain electrode of the tenth PMOS pipe (p10) connects the output of the 3rd inverter (inv3);

The one PMOS manages (p1), the 2nd PMOS manages (p2), the 3rd PMOS manages (p3), and the 4th PMOS manages (p4), and the 5th PMOS manages (p5), the substrate of the 6th PMOS pipe (p6) connects described first power supply (VDDH), the substrate of the 9th PMOS pipe (p9) and the tenth PMOS pipe (p10) connects described second source (VDDL), and a NMOS manages (n1), and the 2nd NMOS manages (n2), the 3rd NMOS manages (n3), the 4th NMOS manages (n4), and the 5th NMOS manages (n5), and the 6th NMOS manages (n6), the 7th NMOS manages (n7), the 8th NMOS manages (n8), and the 9th NMOS manages (n9), and the tenth NMOS manages (n10), the 11 NMOS manages (n11), the substrate ground connection of the 12 NMOS pipe (n12); The 3rd inverter (inv3), the 4th inverter (inv4), the 5th inverter (inv5) and the 9th inverter (inv9) are powered by described second source (VDDL), first inverter (inv1), second inverter (inv2), the power supply of hex inverter (inv6) and the 7th inverter (inv7) is first power supply (VDDH).

4, the CMOS level conversion trigger of condition discharge and difference input and output is characterized in that this trigger contains charge-discharge circuit, condition switch, and holding circuit, the clock window circuit, the charging of difference input and the formation circuit of clock pulse, wherein:

Charge-discharge circuit, be formed by connecting by two discharge paths, wherein, article one, form by the 3rd PMOS pipe (p3) and the 3rd NMOS pipe (n3) serial connection, another is managed (p4) and the 4th NMOS pipe (n4) serial connection by the 4th PMOS and forms, be connected first power supply (VDDH) of the high amplitude of oscillation of the source electrode that described the 3rd PMOS pipe (p3) and the 4th PMOS manage (p4); Condition switch, totally two, wherein:

The first condition switch, form by the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5), two source electrodes of the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5) connect first supplied with digital signal (D) and earth signal 0 respectively, two signals connect first status signal (HQN) and second status signal (HQ) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that first status signal (HQN) is connected to the 3rd PMOS pipe (p3) control of charging, and two drain electrodes connect the grid that the 3rd NMOS manages (n3) after linking to each other, carry out discharge control

The second condition switch, form by the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7), two source electrodes of the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7) connect second supplied with digital signal (DN) and earth signal 0 respectively, second supplied with digital signal (DN) is the inversion signal of described first supplied with digital signal (D), two signals connect second status signal (HQ) and first status signal (HQN) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that second status signal (HQ) is connected to the 4th PMOS pipe (p4) control of charging, and two drain electrodes connect the grid that the 4th NMOS manages (n4) after linking to each other, and carry out discharge control;

Holding circuit, totally two, wherein:

First holding circuit, form by first inverter (inv1) and the 5th PMOS pipe (p5), the output of this first inverter (inv1) links to each other with the grid that the 5th PMOS manages (p5), the input of first inverter (inv1) links to each other with the drain electrode that the 3rd PMOS manages (p3), form first output (XL) of discharge circuit, the source electrode of the 5th PMOS pipe (p5) connects described first power supply (VDDH), and the drain electrode of the 5th PMOS pipe (p5) connects described first output (XL)

Second holding circuit, form by second inverter (inv2) and the 6th PMOS pipe (p6), the output of this second inverter (inv2) links to each other with the grid that the 6th PMOS manages (p6), the input of second inverter (inv2) links to each other with the drain electrode that the 4th PMOS manages (p4), form second output (XR) of discharge circuit, the source electrode of the 6th PMOS pipe (p6) connects described first power supply (VDDH), and the drain electrode of the 6th PMOS pipe (p6) connects described second output (XR); The clock window circuit, be in series by the 2nd NMOS pipe (n2) and NMOS pipe (n1), the drain electrode of the 2nd NMOS pipe (n2) links to each other with the source electrode of discharge paths the 3rd NMOS pipe (n3) with the 4th NMOS pipe (n4) simultaneously, the grid of the 2nd NMOS pipe (n2) connects first clock signal (clk), the grid of the one NMOS pipe (n1) connects the inversion signal (clkN) of first clock signal, and the source ground of NMOS pipe (n1), this window circuit is open-minded in a flash at rising edge clock only, prevented that clock from being between high period because first supplied with digital signal (D) changes the mistake upset that causes;

Clock pulse forms circuit, by the 3rd inverter (inv3), the 4th inverter (inv4), the 5th inverter (inv5) is in series successively, described the 3rd inverter (inv3), the 4th inverter (inv4), the 5th inverter (inv5) is by second source (VDDL) power supply of the low amplitude of oscillation, the input signal of the 3rd inverter (inv3) is first clock signal (clk), and the 5th inverter (inv5) output signal is the inversion signal (clkN) of first clock signal;

The difference imput output circuit contains:

The 3rd NAND gate (NAND3) and second NAND gate (NAND2), described first status signal of the output termination of this second NAND gate (NAND2) (HQN), feedback is connected to an input of the 3rd NAND gate (NAND3) again, described second status signal of the output termination of the 3rd NAND gate (NAND3) (HQ), feedback is connected to an input of second NAND gate (NAND2) again, second output (XR) of the described discharge circuit of another input termination of second NAND gate (NAND2), first output (XL) of the described discharge circuit of another input termination of the 3rd NAND gate (NAND3);

Described second NAND gate (NAND2) and the 3rd NAND gate (NAND3) are powered by described first power supply (VDDH);

The 3rd PMOS manages (p3), the 4th PMOS manages (p4), and the 5th PMOS manages (p5), and the substrate of the 6th PMOS pipe (p6) connects described first power supply (VDDH), the one NMOS manages (n1), the 2nd NMOS manages (n2), and the 3rd NMOS manages (n3), and the 4th NMOS manages (n4), the 5th NMOS manages (n5), the 6th NMOS manages (n6), and the 7th NMOS manages (n7), the substrate ground connection of the 8th NMOS pipe (n8); First inverter (inv1), the power supply of second inverter (inv2) connects first power supply (VDDH), the 3rd inverter (inv3), the power supply of the 4th inverter (inv4) and the 5th inverter (inv5) is second source (VDDL).

5, the CMOS level conversion trigger of condition discharge and difference input and output is characterized in that this trigger contains charge-discharge circuit, condition switch, and holding circuit, the charging of difference input and the formation circuit of clock pulse, wherein:

Charge-discharge circuit, be formed by connecting by two discharge paths, wherein, article one, form by the 3rd PMOS pipe (p3) and the 3rd NMOS pipe (n3) serial connection, another is managed (p4) and the 4th NMOS pipe (n4) serial connection by the 4th PMOS and forms, be connected first power supply (VDDH) of the high amplitude of oscillation of the source electrode that described the 3rd PMOS pipe (p3) and the 4th PMOS manage (p4); Condition switch, totally two, wherein:

The first condition switch, form by the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5), two source electrodes of the 6th NMOS pipe (n6) and the 5th NMOS pipe (n5) connect first supplied with digital signal (D) and earth signal 0 respectively, two signals connect first status signal (HQN) and second status signal (HQ) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that first status signal (HQN) is connected to the 3rd PMOS pipe (p3) control of charging, and two drain electrodes connect the grid that the 3rd NMOS manages (n3) after linking to each other, carry out discharge control

The second condition switch, form by the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7), two source electrodes of the 8th NMOS pipe (n8) and the 7th NMOS pipe (n7) connect second supplied with digital signal (DN) and earth signal 0 respectively, second supplied with digital signal (DN) is the inversion signal of described first supplied with digital signal (D), two signals connect second status signal (HQ) and first status signal (HQN) output of this trigger respectively, this first status signal (HQN) is the inversion signal of second status signal (HQ), the grid that second status signal (HQ) is connected to the 4th PMOS pipe (p4) control of charging, and two drain electrodes connect the grid that the 4th NMOS manages (n4) after linking to each other, and carry out discharge control;

Holding circuit, totally two, wherein:

First holding circuit, form by first inverter (inv1) and the 5th PMOS pipe (p5), the output of this first inverter (inv1) links to each other with the grid that the 5th PMOS manages (p5), the input of first inverter (inv1) links to each other with the drain electrode that the 3rd PMOS manages (p3), form first output (XL) of discharge circuit, the source electrode of the 5th PMOS pipe (p5) connects described first power supply (VDDH), and the drain electrode of the 5th PMOS pipe (p5) connects described first output (XL)

Second holding circuit, form by second inverter (inv2) and the 6th PMOS pipe (p6), the output of this second inverter (inv2) links to each other with the grid that the 6th PMOS manages (p6), the input of second inverter (inv2) links to each other with the drain electrode that the 4th PMOS manages (p4), form second output (XR) of discharge circuit, the source electrode of the 6th PMOS pipe (p6) connects described first power supply (VDDH), and the drain electrode of the 6th PMOS pipe (p6) connects described second output (XR);

The drain electrode of the 2nd NMOS pipe (n2) links to each other with the source electrode of discharge paths the 3rd NMOS pipe (n3) with the 4th NMOS pipe (n4) simultaneously, and the grid of the 2nd NMOS pipe (n2) connects first clock pulse signal (Clk_Pulse), the source ground of the 2nd NMOS pipe (n2);

The difference imput output circuit contains:

The 3rd NAND gate (NAND3) and second NAND gate (NAND2), described first status signal of the output termination of this second NAND gate (NAND2) (HQN), feedback is connected to an input of the 3rd NAND gate (NAND3) again, described second status signal of the output termination of the 3rd NAND gate (NAND3) (HQ), feedback is connected to an input of second NAND gate (NAND2) again, second output (XR) of the described discharge circuit of another input termination of second NAND gate (NAND2), first output (XL) of the described discharge circuit of another input termination of the 3rd NAND gate (NAND3);

Described second NAND gate (NAND2) and the 3rd NAND gate (NAND3) are powered by described first power supply (VDDH);

Clock pulse forms circuit and contains:

By the 3rd inverter (inv3) of connecting successively, the 4th inverter (inv4), the 5th inverter (inv5), first NAND gate (NAND1), the 9th inverter (inv9) is formed, described first NAND gate (NAND1), the 3rd inverter (inv3), the 4th inverter (inv4), the 5th inverter (inv5), the supply power voltage of the 9th inverter (inv9) is second source (VDDL), and another input of described inverter and NAND gate connects first clock signal (clk), and the 9th inverter (inv9) is output as first clock pulse signal (Clk_Pulse);

The 3rd PMOS manages (p3), the 4th PMOS manages (p4), the 5th PMOS manages (p5), and the substrate of the 6th PMOS pipe (p6) connects described first power supply (VDDH), and the 2nd NMOS manages (n2), the 3rd NMOS manages (n3), the 4th NMOS manages (n4), and the 5th NMOS manages (n5), and the 6th NMOS manages (n6), the 7th NMOS manages (n7), the substrate ground connection of the 8th NMOS pipe (n8); The power supply of first inverter (inv1) and second inverter (inv2) is first power supply (VDDH).

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